diff options
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/o3/mips/cpu_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/ozone/cpu.hh | 10 | ||||
-rw-r--r-- | src/cpu/simple_thread.hh | 6 |
5 files changed, 24 insertions, 10 deletions
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 1754300d2..7f8f0547b 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -293,14 +293,16 @@ template <class Impl> TheISA::IntReg AlphaO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid); } template <class Impl> void AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { - this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid); } template <class Impl> diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index d1135f048..09d73b4a2 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -196,14 +196,16 @@ template <class Impl> TheISA::IntReg MipsO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(MipsISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(MipsISA::ArgumentReg[i], tid); } template <class Impl> void MipsO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid) { - this->setArchIntReg(MipsISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(MipsISA::ArgumentReg[i], val, tid); } template <class Impl> diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 2e398577e..068057fc0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -270,8 +270,9 @@ template <class Impl> TheISA::IntReg SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); TheISA::IntReg val = this->readArchIntReg(idx, tid); if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) val = bits(val, 31, 0); @@ -282,8 +283,9 @@ template <class Impl> void SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); this->setArchIntReg(idx, val, tid); } diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 2432df55e..92b00af26 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -253,11 +253,17 @@ class OzoneCPU : public BaseCPU #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) - { return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); } + { + assert(i < TheISA::NumArgumentRegs); + return thread->renameTable[TheISA::ArgumentReg[i]]->readIntResult(); + } // used to shift args for indirect syscall void setSyscallArg(int i, TheISA::IntReg val) - { thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); } + { + assert(i < TheISA::NumArgumentRegs); + thread->renameTable[TheISA::ArgumentReg[i]]->setIntResult(i); + } void setSyscallReturn(SyscallReturn return_value) { cpu->setSyscallReturn(return_value, thread->readTid()); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index c20fe3d90..6c6d5f842 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -377,15 +377,17 @@ class SimpleThread : public ThreadState #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { + assert(i < TheISA::NumArgumentRegs); return regs.readIntReg(TheISA::flattenIntIndex(getTC(), - TheISA::ArgumentReg0 + i)); + TheISA::ArgumentReg[i])); } // used to shift args for indirect syscall void setSyscallArg(int i, TheISA::IntReg val) { + assert(i < TheISA::NumArgumentRegs); regs.setIntReg(TheISA::flattenIntIndex(getTC(), - TheISA::ArgumentReg0 + i), val); + TheISA::ArgumentReg[i]), val); } void setSyscallReturn(SyscallReturn return_value) |