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-rw-r--r--src/cpu/SConscript116
-rw-r--r--src/cpu/base.cc22
-rw-r--r--src/cpu/base.hh2
-rw-r--r--src/cpu/memtest/SConscript34
-rw-r--r--src/cpu/memtest/memtest.cc2
-rwxr-xr-xsrc/cpu/o3/SConscript86
-rw-r--r--src/cpu/o3/SConsopts34
-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh8
-rw-r--r--src/cpu/o3/cpu.cc39
-rw-r--r--src/cpu/o3/cpu.hh4
-rw-r--r--src/cpu/o3/lsq.hh7
-rw-r--r--src/cpu/o3/lsq_impl.hh13
-rw-r--r--src/cpu/o3/sparc/dyn_inst.hh8
-rw-r--r--src/cpu/ozone/SConscript45
-rw-r--r--src/cpu/ozone/SConsopts33
-rw-r--r--src/cpu/pc_event.cc2
-rw-r--r--src/cpu/simple/SConscript43
-rw-r--r--src/cpu/simple/SConsopts34
-rw-r--r--src/cpu/simple/atomic.cc30
-rw-r--r--src/cpu/simple/atomic.hh17
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/cpu/simple/base.hh8
-rw-r--r--src/cpu/simple/timing.cc61
-rw-r--r--src/cpu/simple/timing.hh2
-rw-r--r--src/cpu/thread_state.cc10
-rw-r--r--src/cpu/trace/SConscript40
26 files changed, 475 insertions, 227 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 4d4b7574c..1c2278f6f 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -28,11 +28,7 @@
#
# Authors: Steve Reinhardt
-import os
-import os.path
-
-# Import build environment variable from SConstruct.
-Import('env')
+Import('*')
#################################################################
#
@@ -107,89 +103,24 @@ env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
# and one of these are not being used.
CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
-#################################################################
-#
-# Include CPU-model-specific files based on set of models
-# specified in CPU_MODELS build option.
-#
-#################################################################
-
-# Keep a list of CPU models that support SMT
-env['SMT_CPU_MODELS'] = []
-
-sources = []
-
-need_simple_base = False
-if 'AtomicSimpleCPU' in env['CPU_MODELS']:
- need_simple_base = True
- sources += Split('simple/atomic.cc')
-
-if 'TimingSimpleCPU' in env['CPU_MODELS']:
- need_simple_base = True
- sources += Split('simple/timing.cc')
-
-if need_simple_base:
- sources += Split('simple/base.cc')
-
-if 'FastCPU' in env['CPU_MODELS']:
- sources += Split('fast/cpu.cc')
-
-need_bp_unit = False
-if 'O3CPU' in env['CPU_MODELS']:
- need_bp_unit = True
- sources += SConscript('o3/SConscript', exports = 'env')
- sources += Split('''
- o3/base_dyn_inst.cc
- o3/bpred_unit.cc
- o3/commit.cc
- o3/decode.cc
- o3/fetch.cc
- o3/free_list.cc
- o3/fu_pool.cc
- o3/cpu.cc
- o3/iew.cc
- o3/inst_queue.cc
- o3/lsq_unit.cc
- o3/lsq.cc
- o3/mem_dep_unit.cc
- o3/rename.cc
- o3/rename_map.cc
- o3/rob.cc
- o3/scoreboard.cc
- o3/store_set.cc
- ''')
- sources += Split('memtest/memtest.cc')
- if env['USE_CHECKER']:
- sources += Split('o3/checker_builder.cc')
- else:
- env['SMT_CPU_MODELS'].append('O3CPU') # Checker doesn't support SMT right now
-
-if 'OzoneCPU' in env['CPU_MODELS']:
- need_bp_unit = True
- sources += Split('''
- ozone/base_dyn_inst.cc
- ozone/bpred_unit.cc
- ozone/cpu.cc
- ozone/cpu_builder.cc
- ozone/dyn_inst.cc
- ozone/front_end.cc
- ozone/lw_back_end.cc
- ozone/lw_lsq.cc
- ozone/rename_table.cc
- ''')
- if env['USE_CHECKER']:
- sources += Split('ozone/checker_builder.cc')
-
-if need_bp_unit:
- sources += Split('''
- o3/2bit_local_pred.cc
- o3/btb.cc
- o3/ras.cc
- o3/tournament_pred.cc
- ''')
+Source('activity.cc')
+Source('base.cc')
+Source('cpuevent.cc')
+Source('exetrace.cc')
+Source('func_unit.cc')
+Source('op_class.cc')
+Source('pc_event.cc')
+Source('quiesce_event.cc')
+Source('static_inst.cc')
+Source('simple_thread.cc')
+Source('thread_state.cc')
+
+if env['FULL_SYSTEM']:
+ Source('intr_control.cc')
+ Source('profile.cc')
if env['USE_CHECKER']:
- sources += Split('checker/cpu.cc')
+ Source('checker/cpu.cc')
checker_supports = False
for i in CheckerSupportedCPUList:
if i in env['CPU_MODELS']:
@@ -198,16 +129,5 @@ if env['USE_CHECKER']:
print "Checker only supports CPU models",
for i in CheckerSupportedCPUList:
print i,
- print ", please set USE_CHECKER=False or use one of those CPU models"
+ print ", please set USE_CHECKER=False or use one of those CPU models"
Exit(1)
-
-
-# FullCPU sources are included from src/SConscript since they're not
-# below this point in the file hierarchy.
-
-# Convert file names to SCons File objects. This takes care of the
-# path relative to the top of the directory tree.
-sources = [File(s) for s in sources]
-
-Return('sources')
-
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 104b3b6bb..3e0be6ad8 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -319,7 +319,7 @@ BaseCPU::switchOut()
}
void
-BaseCPU::takeOverFrom(BaseCPU *oldCPU)
+BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
@@ -352,6 +352,26 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
// if (profileEvent)
// profileEvent->schedule(curTick);
#endif
+
+ // Connect new CPU to old CPU's memory only if new CPU isn't
+ // connected to anything. Also connect old CPU's memory to new
+ // CPU.
+ Port *peer;
+ if (ic->getPeer() == NULL) {
+ peer = oldCPU->getPort("icache_port")->getPeer();
+ ic->setPeer(peer);
+ } else {
+ peer = ic->getPeer();
+ }
+ peer->setPeer(ic);
+
+ if (dc->getPeer() == NULL) {
+ peer = oldCPU->getPort("dcache_port")->getPeer();
+ dc->setPeer(peer);
+ } else {
+ peer = dc->getPeer();
+ }
+ peer->setPeer(dc);
}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 85f5b7725..4d8300186 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -202,7 +202,7 @@ class BaseCPU : public MemObject
/// Take over execution from the given CPU. Used for warm-up and
/// sampling.
- virtual void takeOverFrom(BaseCPU *);
+ virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
/**
* Number of threads we're actually simulating (<= SMT_MAX_THREADS).
diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript
new file mode 100644
index 000000000..7b4d6d2c5
--- /dev/null
+++ b/src/cpu/memtest/SConscript
@@ -0,0 +1,34 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+if 'O3CPU' in env['CPU_MODELS']:
+ Source('memtest.cc')
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 8b3e9a11e..607cf1066 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -369,7 +369,7 @@ MemTest::tick()
//This means we assume CPU does write forwarding to reads that alias something
//in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
- delete result;
+ delete [] result;
delete req;
return;
}
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index afbd4c533..bb1dfb613 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -26,52 +26,56 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-# Authors: Korey Sewell
+# Authors: Nathan Binkert
-import os
-import os.path
import sys
-# Import build environment variable from SConstruct.
-Import('env')
+Import('*')
+if 'O3CPU' in env['CPU_MODELS']:
+ Source('base_dyn_inst.cc')
+ Source('bpred_unit.cc')
+ Source('commit.cc')
+ Source('cpu.cc')
+ Source('decode.cc')
+ Source('fetch.cc')
+ Source('free_list.cc')
+ Source('fu_pool.cc')
+ Source('iew.cc')
+ Source('inst_queue.cc')
+ Source('lsq.cc')
+ Source('lsq_unit.cc')
+ Source('mem_dep_unit.cc')
+ Source('rename.cc')
+ Source('rename_map.cc')
+ Source('rob.cc')
+ Source('scoreboard.cc')
+ Source('store_set.cc')
-#################################################################
-#
-# Include ISA-specific files for the O3 CPU-model
-#
-#################################################################
-
-sources = []
-
-if env['TARGET_ISA'] == 'alpha':
- sources += Split('''
- alpha/dyn_inst.cc
- alpha/cpu.cc
- alpha/thread_context.cc
- alpha/cpu_builder.cc
- ''')
-elif env['TARGET_ISA'] == 'mips':
- sources += Split('''
- mips/dyn_inst.cc
- mips/cpu.cc
- mips/thread_context.cc
- mips/cpu_builder.cc
- ''')
-elif env['TARGET_ISA'] == 'sparc':
- sources += Split('''
- sparc/dyn_inst.cc
- sparc/cpu.cc
- sparc/thread_context.cc
- sparc/cpu_builder.cc
- ''')
-else:
- sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
-
+ if env['TARGET_ISA'] == 'alpha':
+ Source('alpha/cpu.cc')
+ Source('alpha/cpu_builder.cc')
+ Source('alpha/dyn_inst.cc')
+ Source('alpha/thread_context.cc')
+ elif env['TARGET_ISA'] == 'mips':
+ Source('mips/cpu.cc')
+ Source('mips/cpu_builder.cc')
+ Source('mips/dyn_inst.cc')
+ Source('mips/thread_context.cc')
+ elif env['TARGET_ISA'] == 'sparc':
+ Source('sparc/cpu.cc')
+ Source('sparc/cpu_builder.cc')
+ Source('sparc/dyn_inst.cc')
+ Source('sparc/thread_context.cc')
+ else:
+ sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
-# Convert file names to SCons File objects. This takes care of the
-# path relative to the top of the directory tree.
-sources = [File(s) for s in sources]
+ if env['USE_CHECKER']:
+ Source('checker_builder.cc')
-Return('sources')
+if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
+ Source('2bit_local_pred.cc')
+ Source('btb.cc')
+ Source('ras.cc')
+ Source('tournament_pred.cc')
diff --git a/src/cpu/o3/SConsopts b/src/cpu/o3/SConsopts
new file mode 100644
index 000000000..040352e6a
--- /dev/null
+++ b/src/cpu/o3/SConsopts
@@ -0,0 +1,34 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+all_cpu_list.append('O3CPU')
+default_cpus.append('O3CPU')
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 6c27e890a..20759d849 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -125,7 +125,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -135,7 +135,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -143,7 +143,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
/** Sets a misc. register. */
- void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val)
+ void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscRegNoEffect(
@@ -154,7 +154,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscRegOperandWithEffect(const StaticInst *si, int idx,
+ void setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
return this->cpu->setMiscReg(
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 785165636..38e6a0b5b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -557,12 +557,6 @@ template <class Impl>
void
FullO3CPU<Impl>::activateContext(int tid, int delay)
{
-#if FULL_SYSTEM
- // Connect the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- threadContexts[tid]->connectMemPorts();
-#endif
-
// Needs to set each stage to running as well.
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
@@ -781,6 +775,18 @@ FullO3CPU<Impl>::activateWhenReady(int tid)
}
}
+#if FULL_SYSTEM
+template <class Impl>
+void
+FullO3CPU<Impl>::updateMemPorts()
+{
+ // Update all ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ for (int i = 0; i < thread.size(); ++i)
+ thread[i]->connectMemPorts();
+}
+#endif
+
template <class Impl>
void
FullO3CPU<Impl>::serialize(std::ostream &os)
@@ -941,7 +947,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
activityRec.reset();
- BaseCPU::takeOverFrom(oldCPU);
+ BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
fetch.takeOverFrom();
decode.takeOverFrom();
@@ -978,25 +984,6 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
if (!tickEvent.scheduled())
tickEvent.schedule(curTick);
-
- Port *peer;
- Port *icachePort = fetch.getIcachePort();
- if (icachePort->getPeer() == NULL) {
- peer = oldCPU->getPort("icache_port")->getPeer();
- icachePort->setPeer(peer);
- } else {
- peer = icachePort->getPeer();
- }
- peer->setPeer(icachePort);
-
- Port *dcachePort = iew.getDcachePort();
- if (dcachePort->getPeer() == NULL) {
- peer = oldCPU->getPort("dcache_port")->getPeer();
- dcachePort->setPeer(peer);
- } else {
- peer = dcachePort->getPeer();
- }
- peer->setPeer(dcachePort);
}
template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index d217a3e85..ea374dd57 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -357,6 +357,10 @@ class FullO3CPU : public BaseO3CPU
{ return globalSeqNum++; }
#if FULL_SYSTEM
+ /** Update the Virt and Phys ports of all ThreadContexts to
+ * reflect change in memory connections. */
+ void updateMemPorts();
+
/** Check if this address is a valid instruction address. */
bool validInstAddr(Addr addr) { return true; }
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index e68085cfd..80f53a726 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -300,6 +300,8 @@ class LSQ {
bool snoopRangeSent;
+ virtual void setPeer(Port *port);
+
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
@@ -327,6 +329,11 @@ class LSQ {
/** D-cache port. */
DcachePort dcachePort;
+#if FULL_SYSTEM
+ /** Tell the CPU to update the Phys and Virt ports. */
+ void updateMemPorts() { cpu->updateMemPorts(); }
+#endif
+
protected:
/** The LSQ policy for SMT mode. */
LSQPolicy lsqPolicy;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index fb738f7c9..d4994fcb7 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -34,6 +34,19 @@
#include "cpu/o3/lsq.hh"
+template<class Impl>
+void
+LSQ<Impl>::DcachePort::setPeer(Port *port)
+{
+ Port::setPeer(port);
+
+#if FULL_SYSTEM
+ // Update the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ lsq->updateMemPorts();
+#endif
+}
+
template <class Impl>
Tick
LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh
index bd61b0384..72242b161 100644
--- a/src/cpu/o3/sparc/dyn_inst.hh
+++ b/src/cpu/o3/sparc/dyn_inst.hh
@@ -107,7 +107,7 @@ class SparcDynInst : public BaseDynInst<Impl>
}
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -117,7 +117,7 @@ class SparcDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+ TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -125,7 +125,7 @@ class SparcDynInst : public BaseDynInst<Impl>
}
/** Sets a misc. register. */
- void setMiscRegOperand(const StaticInst * si,
+ void setMiscRegOperandNoEffect(const StaticInst * si,
int idx, const TheISA::MiscReg &val)
{
this->instResult.integer = val;
@@ -137,7 +137,7 @@ class SparcDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscRegOperandWithEffect(
+ void setMiscRegOperand(
const StaticInst *si, int idx, const TheISA::MiscReg &val)
{
return this->cpu->setMiscReg(
diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript
new file mode 100644
index 000000000..4a040684a
--- /dev/null
+++ b/src/cpu/ozone/SConscript
@@ -0,0 +1,45 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+if 'OzoneCPU' in env['CPU_MODELS']:
+ need_bp_unit = True
+ Source('base_dyn_inst.cc')
+ Source('bpred_unit.cc')
+ Source('cpu.cc')
+ Source('cpu_builder.cc')
+ Source('dyn_inst.cc')
+ Source('front_end.cc')
+ Source('lw_back_end.cc')
+ Source('lw_lsq.cc')
+ Source('rename_table.cc')
+ if env['USE_CHECKER']:
+ Source('checker_builder.cc')
diff --git a/src/cpu/ozone/SConsopts b/src/cpu/ozone/SConsopts
new file mode 100644
index 000000000..341644dcd
--- /dev/null
+++ b/src/cpu/ozone/SConsopts
@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+all_cpu_list.append('OzoneCPU')
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index 7ab8bfcb8..438218df2 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -138,14 +138,12 @@ BreakPCEvent::process(ThreadContext *tc)
}
#if FULL_SYSTEM
-extern "C"
void
sched_break_pc_sys(System *sys, Addr addr)
{
new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
}
-extern "C"
void
sched_break_pc(Addr addr)
{
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
new file mode 100644
index 000000000..9a6a80473
--- /dev/null
+++ b/src/cpu/simple/SConscript
@@ -0,0 +1,43 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+need_simple_base = False
+if 'AtomicSimpleCPU' in env['CPU_MODELS']:
+ need_simple_base = True
+ Source('atomic.cc')
+
+if 'TimingSimpleCPU' in env['CPU_MODELS']:
+ need_simple_base = True
+ Source('timing.cc')
+
+if need_simple_base:
+ Source('base.cc')
diff --git a/src/cpu/simple/SConsopts b/src/cpu/simple/SConsopts
new file mode 100644
index 000000000..32dbda1a5
--- /dev/null
+++ b/src/cpu/simple/SConsopts
@@ -0,0 +1,34 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+all_cpu_list.extend(('AtomicSimpleCPU', 'TimingSimpleCPU'))
+default_cpus.extend(('AtomicSimpleCPU', 'TimingSimpleCPU'))
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0361db012..6f69b5ac4 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -126,6 +126,17 @@ AtomicSimpleCPU::CpuPort::recvRetry()
panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
}
+void
+AtomicSimpleCPU::DcachePort::setPeer(Port *port)
+{
+ Port::setPeer(port);
+
+#if FULL_SYSTEM
+ // Update the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ cpu->tcBase()->connectMemPorts();
+#endif
+}
AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
: BaseSimpleCPU(p), tickEvent(this),
@@ -211,7 +222,7 @@ AtomicSimpleCPU::switchOut()
void
AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
{
- BaseCPU::takeOverFrom(oldCPU);
+ BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
assert(!tickEvent.scheduled());
@@ -242,12 +253,6 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
notIdleFraction++;
-#if FULL_SYSTEM
- // Connect the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- tc->connectMemPorts();
-#endif
-
//Make sure ticks are still on multiples of cycles
tickEvent.schedule(nextCycle(curTick + cycles(delay)));
_status = Running;
@@ -441,6 +446,17 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+AtomicSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+AtomicSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
template
Fault
AtomicSimpleCPU::write(uint64_t data, Addr addr,
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 5bffb7666..ad4aa4708 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -81,9 +81,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
class CpuPort : public Port
{
-
- AtomicSimpleCPU *cpu;
-
public:
CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
@@ -94,6 +91,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
protected:
+ AtomicSimpleCPU *cpu;
+
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
@@ -110,7 +109,17 @@ class AtomicSimpleCPU : public BaseSimpleCPU
};
CpuPort icachePort;
- CpuPort dcachePort;
+
+ class DcachePort : public CpuPort
+ {
+ public:
+ DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
+ : CpuPort(_name, _cpu)
+ { }
+
+ virtual void setPeer(Port *port);
+ };
+ DcachePort dcachePort;
Request *ifetch_req;
PacketPtr ifetch_pkt;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 2ad328542..cd139492a 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -301,7 +301,7 @@ BaseSimpleCPU::post_interrupt(int int_num, int index)
BaseCPU::post_interrupt(int_num, index);
if (thread->status() == ThreadContext::Suspended) {
- DPRINTF(IPI,"Suspended Processor awoke\n");
+ DPRINTF(Quiesce,"Suspended Processor awoke\n");
thread->activate();
}
}
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index a7686bbb1..787259c96 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -311,25 +311,25 @@ class BaseSimpleCPU : public BaseCPU
return thread->setMiscReg(misc_reg, val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscRegNoEffect(reg_idx);
}
- MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
+ MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscReg(reg_idx);
}
- void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
+ void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscRegNoEffect(reg_idx, val);
}
- void setMiscRegOperandWithEffect(
+ void setMiscRegOperand(
const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7f857c68d..45da7c3eb 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -194,7 +194,7 @@ TimingSimpleCPU::switchOut()
void
TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
{
- BaseCPU::takeOverFrom(oldCPU);
+ BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
// if any of this CPU's ThreadContexts are active, mark the CPU as
// running and schedule its tick event.
@@ -209,23 +209,6 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
if (_status != Running) {
_status = Idle;
}
-
- Port *peer;
- if (icachePort.getPeer() == NULL) {
- peer = oldCPU->getPort("icache_port")->getPeer();
- icachePort.setPeer(peer);
- } else {
- peer = icachePort.getPeer();
- }
- peer->setPeer(&icachePort);
-
- if (dcachePort.getPeer() == NULL) {
- peer = oldCPU->getPort("dcache_port")->getPeer();
- dcachePort.setPeer(peer);
- } else {
- peer = dcachePort.getPeer();
- }
- peer->setPeer(&dcachePort);
}
@@ -240,12 +223,6 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
notIdleFraction++;
_status = Running;
-#if FULL_SYSTEM
- // Connect the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- tc->connectMemPorts();
-#endif
-
// kick things off by initiating the fetch of the next instruction
fetchEvent =
new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
@@ -298,14 +275,14 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// memory system takes ownership of packet
dcache_pkt = NULL;
}
+
+ // This will need a new way to tell if it has a dcache attached.
+ if (req->isUncacheable())
+ recordEvent("Uncached Read");
} else {
delete req;
}
- // This will need a new way to tell if it has a dcache attached.
- if (req->isUncacheable())
- recordEvent("Uncached Read");
-
return fault;
}
@@ -404,13 +381,13 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_pkt = NULL;
}
}
+ // This will need a new way to tell if it's hooked up to a cache or not.
+ if (req->isUncacheable())
+ recordEvent("Uncached Write");
} else {
delete req;
}
- // This will need a new way to tell if it's hooked up to a cache or not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");
// If the write needs to have a fault on the access, consider calling
// changeStatus() and changing it to "bad addr write" or something.
@@ -421,6 +398,16 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault
+TimingSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+TimingSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
TimingSimpleCPU::write(uint64_t data, Addr addr,
unsigned flags, uint64_t *res);
@@ -649,6 +636,18 @@ TimingSimpleCPU::completeDrain()
drainEvent->process();
}
+void
+TimingSimpleCPU::DcachePort::setPeer(Port *port)
+{
+ Port::setPeer(port);
+
+#if FULL_SYSTEM
+ // Update the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ cpu->tcBase()->connectMemPorts();
+#endif
+}
+
bool
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index abcb224bf..ef062d24a 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -144,6 +144,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
: CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
{ }
+ virtual void setPeer(Port *port);
+
protected:
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 93dd1e2eb..4b65ca4b8 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -125,7 +125,10 @@ ThreadState::connectPhysPort()
// @todo: For now this disregards any older port that may have
// already existed. Fix this memory leak once the bus port IDs
// for functional ports is resolved.
- physPort = new FunctionalPort(csprintf("%s-%d-funcport",
+ if (physPort)
+ physPort->removeConn();
+ else
+ physPort = new FunctionalPort(csprintf("%s-%d-funcport",
baseCpu->name(), tid));
connectToMemFunc(physPort);
}
@@ -136,7 +139,10 @@ ThreadState::connectVirtPort()
// @todo: For now this disregards any older port that may have
// already existed. Fix this memory leak once the bus port IDs
// for functional ports is resolved.
- virtPort = new VirtualPort(csprintf("%s-%d-vport",
+ if (virtPort)
+ virtPort->removeConn();
+ else
+ virtPort = new VirtualPort(csprintf("%s-%d-vport",
baseCpu->name(), tid));
connectToMemFunc(virtPort);
}
diff --git a/src/cpu/trace/SConscript b/src/cpu/trace/SConscript
new file mode 100644
index 000000000..f166b2f23
--- /dev/null
+++ b/src/cpu/trace/SConscript
@@ -0,0 +1,40 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+if False:
+ Source('opt_cpu.cc')
+ Source('trace_cpu.cc')
+
+ Source('reader/mem_trace_reader.cc')
+ Source('reader/ibm_reader.cc')
+ Source('reader/itx_reader.cc')
+ Source('reader/m5_reader.cc')
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-04 12:31:55 +0000