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-rw-r--r--src/cpu/checker/cpu.cc6
-rw-r--r--src/cpu/checker/cpu_impl.hh4
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc4
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh3
-rw-r--r--src/cpu/o3/lsq_unit.hh18
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh6
-rw-r--r--src/cpu/ozone/front_end_impl.hh3
-rw-r--r--src/cpu/ozone/lw_lsq.hh5
-rw-r--r--src/cpu/ozone/lw_lsq_impl.hh2
-rw-r--r--src/cpu/simple/atomic.cc9
-rw-r--r--src/cpu/simple/timing.cc7
-rw-r--r--src/cpu/testers/directedtest/InvalidateGenerator.cc4
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.cc2
-rw-r--r--src/cpu/testers/memtest/memtest.cc6
-rw-r--r--src/cpu/testers/networktest/networktest.cc3
-rw-r--r--src/cpu/testers/rubytest/Check.cc8
17 files changed, 39 insertions, 55 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 66341b0e0..901c3900f 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -170,9 +170,9 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
if (fault == NoFault &&
!memReq->getFlags().isSet(Request::NO_ACCESS)) {
PacketPtr pkt = new Packet(memReq,
- memReq->isLLSC() ?
- MemCmd::LoadLockedReq : MemCmd::ReadReq,
- Packet::Broadcast);
+ memReq->isLLSC() ?
+ MemCmd::LoadLockedReq :
+ MemCmd::ReadReq);
pkt->dataStatic(data);
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 167c3531f..dcc6b01f9 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -281,9 +281,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
break;
}
} else {
- PacketPtr pkt = new Packet(memReq,
- MemCmd::ReadReq,
- Packet::Broadcast);
+ PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
pkt->dataStatic(&machInst);
icachePort->sendFunctional(pkt);
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 10046f7f2..a5bb9cd24 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -814,7 +814,6 @@ CacheUnit::buildDataPacket(CacheRequest *cache_req)
cache_req->dataPkt = new CacheReqPacket(cache_req,
cache_req->pktCmd,
- Packet::Broadcast,
cache_req->instIdx);
DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
cache_req->getSlot(),
@@ -1035,8 +1034,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
cpu->dataMasterId(),
0);
- split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd,
- Packet::Broadcast);
+ split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd);
split_pkt->dataStatic(inst->splitMemData);
DPRINTF(InOrderCachePort, "Completing Split Access.\n");
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 3f3ef12e6..f0878d24d 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -252,8 +252,8 @@ class CacheReqPacket : public Packet
{
public:
CacheReqPacket(CacheRequest *_req,
- Command _cmd, short _dest, int _idx = 0)
- : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
+ Command _cmd, int _idx = 0)
+ : Packet(&(*_req->memReq), _cmd), cacheReq(_req),
instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
{
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 0ff515855..2480211e4 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -611,8 +611,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
}
// Build packet here.
- PacketPtr data_pkt = new Packet(mem_req,
- MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
cacheDataPC[tid] = block_PC;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 44898eb38..44c3df0bf 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -605,18 +605,15 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
ThreadContext *thread = cpu->tcBase(lsqID);
Tick delay;
- PacketPtr data_pkt =
- new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
data_pkt->dataStatic(load_inst->memData);
delay = TheISA::handleIprRead(thread, data_pkt);
} else {
assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
- PacketPtr fst_data_pkt =
- new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
- PacketPtr snd_data_pkt =
- new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
+ PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
fst_data_pkt->dataStatic(load_inst->memData);
snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
@@ -689,8 +686,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
"addr %#x, data %#x\n",
store_idx, req->getVaddr(), data);
- PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
- Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
data_pkt->dataStatic(load_inst->memData);
WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
@@ -772,7 +768,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
if (!lsq->cacheBlocked()) {
MemCmd command =
req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
- PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, command);
PacketPtr fst_data_pkt = NULL;
PacketPtr snd_data_pkt = NULL;
@@ -791,8 +787,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
} else {
// Create the split packets.
- fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
- snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
+ fst_data_pkt = new Packet(sreqLow, command);
+ snd_data_pkt = new Packet(sreqHigh, command);
fst_data_pkt->dataStatic(load_inst->memData);
snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 2de349242..f4182e30d 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -823,13 +823,13 @@ LSQUnit<Impl>::writebackStores()
if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
// Build a single data packet if the store isn't split.
- data_pkt = new Packet(req, command, Packet::Broadcast);
+ data_pkt = new Packet(req, command);
data_pkt->dataStatic(inst->memData);
data_pkt->senderState = state;
} else {
// Create two packets if the store is split in two.
- data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
- snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
+ data_pkt = new Packet(sreqLow, command);
+ snd_data_pkt = new Packet(sreqHigh, command);
data_pkt->dataStatic(inst->memData);
snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 12aa0a321..66bcc6227 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -477,8 +477,7 @@ FrontEnd<Impl>::fetchCacheLine()
#endif
// Build packet here.
- PacketPtr data_pkt = new Packet(memReq,
- Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(memReq, Packet::ReadReq);
data_pkt->dataStatic(cacheData);
if (!icachePort.sendTiming(data_pkt)) {
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index a581b242f..db8e53b43 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -571,7 +571,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
(*sq_it).inst->seqNum, inst->seqNum, req->getVaddr(),
*(inst->memData));
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, Packet::ReadReq);
data_pkt->dataStatic(inst->memData);
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
@@ -635,8 +635,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
PacketPtr data_pkt =
new Packet(req,
(req->isLLSC() ?
- MemCmd::LoadLockedReq : Packet::ReadReq),
- Packet::Broadcast);
+ MemCmd::LoadLockedReq : Packet::ReadReq));
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index c0c6d7276..79b2b8f16 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -577,7 +577,7 @@ OzoneLWLSQ<Impl>::writebackStores()
MemCmd command =
req->isSwap() ? MemCmd::SwapReq :
(req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
- PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, command);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 90f4fa579..87f41a721 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -272,8 +272,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
Packet pkt = Packet(req,
- req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
- Packet::Broadcast);
+ req->isLLSC() ? MemCmd::LoadLockedReq :
+ MemCmd::ReadReq);
pkt.dataStatic(data);
if (req->isMmappedIpr())
@@ -374,7 +374,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
}
if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
- Packet pkt = Packet(req, cmd, Packet::Broadcast);
+ Packet pkt = Packet(req, cmd);
pkt.dataStatic(data);
if (req->isMmappedIpr()) {
@@ -473,8 +473,7 @@ AtomicSimpleCPU::tick()
//if(predecoder.needMoreBytes())
//{
icache_access = true;
- Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
- Packet::Broadcast);
+ Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
ifetch_pkt.dataStatic(&inst);
if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d52003f19..5dba51842 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -355,7 +355,7 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
cmd = MemCmd::SwapReq;
}
}
- pkt = new Packet(req, cmd, Packet::Broadcast);
+ pkt = new Packet(req, cmd);
}
void
@@ -376,8 +376,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
buildPacket(pkt2, req2, read);
req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
- PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
- Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
pkt->dataDynamicArray<uint8_t>(data);
pkt1->dataStatic<uint8_t>(data);
@@ -578,7 +577,7 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
if (fault == NoFault) {
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
req->getVaddr(), req->getPaddr());
- ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ ifetch_pkt = new Packet(req, MemCmd::ReadReq);
ifetch_pkt->dataStatic(&inst);
DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index f01e6fb50..4c248ea05 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -68,13 +68,13 @@ InvalidateGenerator::initiate()
cmd = MemCmd::ReadReq;
port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
getCpuPort(m_active_read_node));
- pkt = new Packet(req, cmd, m_active_read_node);
+ pkt = new Packet(req, cmd);
} else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
DPRINTF(DirectedTest, "initiating invalidating write\n");
cmd = MemCmd::WriteReq;
port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
getCpuPort(m_active_inv_node));
- pkt = new Packet(req, cmd, m_active_inv_node);
+ pkt = new Packet(req, cmd);
} else {
panic("initiate was unexpectedly called\n");
}
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 137d24b21..92dc46f85 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -67,7 +67,7 @@ SeriesRequestGenerator::initiate()
} else {
cmd = MemCmd::ReadReq;
}
- PacketPtr pkt = new Packet(req, cmd, m_active_node);
+ PacketPtr pkt = new Packet(req, cmd);
uint8_t* dummyData = new uint8_t;
*dummyData = 0;
pkt->dataDynamic(dummyData);
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 7e34c2833..809b4dd93 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -328,8 +328,7 @@ MemTest::tick()
id, do_functional ? "functional " : "", req->getPaddr(),
blockAddr(req->getPaddr()), *result);
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
- pkt->setSrc(0);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
@@ -360,8 +359,7 @@ MemTest::tick()
do_functional ? "functional " : "", req->getPaddr(),
blockAddr(req->getPaddr()), data & 0xff);
- PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
- pkt->setSrc(0);
+ PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 45a414539..aa8b54b8e 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -259,8 +259,7 @@ NetworkTest::generatePkt()
"Generated packet with destination %d, embedded in address %x\n",
destination, req->getPaddr());
- PacketPtr pkt = new Packet(req, requestType, 0);
- pkt->setSrc(0); //Not used
+ PacketPtr pkt = new Packet(req, requestType);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
pkt->senderState = NULL;
diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index 6f119af06..892e05dd0 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -108,7 +108,7 @@ Check::initiatePrefetch()
m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
req->setThreadContext(index, 0);
- PacketPtr pkt = new Packet(req, cmd, port->idx);
+ PacketPtr pkt = new Packet(req, cmd);
// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
@@ -149,7 +149,7 @@ Check::initiateFlush()
cmd = MemCmd::FlushReq;
- PacketPtr pkt = new Packet(req, cmd, port->idx);
+ PacketPtr pkt = new Packet(req, cmd);
// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
@@ -191,7 +191,7 @@ Check::initiateAction()
cmd = MemCmd::WriteReq;
// }
- PacketPtr pkt = new Packet(req, cmd, port->idx);
+ PacketPtr pkt = new Packet(req, cmd);
uint8_t* writeData = new uint8_t;
*writeData = m_value + m_store_count;
pkt->dataDynamic(writeData);
@@ -248,7 +248,7 @@ Check::initiateCheck()
m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
req->setThreadContext(index, 0);
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
uint8_t* dataArray = new uint8_t[CHECK_SIZE];
pkt->dataDynamicArray(dataArray);
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 19:58:47 +0000