diff options
Diffstat (limited to 'src/cpu')
40 files changed, 89 insertions, 263 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index fe840cd35..f9ae9ce5d 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -371,8 +371,10 @@ BaseCPU::switchOut() } void -BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) +BaseCPU::takeOverFrom(BaseCPU *oldCPU) { + Port *ic = getPort("icache_port"); + Port *dc = getPort("dcache_port"); assert(threadContexts.size() == oldCPU->threadContexts.size()); _cpuId = oldCPU->cpuId(); diff --git a/src/cpu/base.hh b/src/cpu/base.hh index d4de55453..f6c0da3d3 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -61,7 +61,7 @@ #include "arch/interrupts.hh" #endif -class BaseCPUParams; +struct BaseCPUParams; class BranchPred; class CheckerCPU; class ThreadContext; @@ -241,16 +241,16 @@ class BaseCPU : public MemObject /// Notify the CPU that the indicated context is now active. The /// delay parameter indicates the number of ticks to wait before /// executing (typically 0 or 1). - virtual void activateContext(int thread_num, int delay) {} + virtual void activateContext(ThreadID thread_num, int delay) {} /// Notify the CPU that the indicated context is now suspended. - virtual void suspendContext(int thread_num) {} + virtual void suspendContext(ThreadID thread_num) {} /// Notify the CPU that the indicated context is now deallocated. - virtual void deallocateContext(int thread_num) {} + virtual void deallocateContext(ThreadID thread_num) {} /// Notify the CPU that the indicated context is now halted. - virtual void haltContext(int thread_num) {} + virtual void haltContext(ThreadID thread_num) {} /// Given a Thread Context pointer return the thread num int findContext(ThreadContext *tc); @@ -279,7 +279,7 @@ class BaseCPU : public MemObject /// Take over execution from the given CPU. Used for warm-up and /// sampling. - virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); + virtual void takeOverFrom(BaseCPU *); /** * Number of threads we're actually simulating (<= SMT_MAX_THREADS). diff --git a/src/cpu/func_unit.hh b/src/cpu/func_unit.hh index 59c5ee8a0..3745bb7d1 100644 --- a/src/cpu/func_unit.hh +++ b/src/cpu/func_unit.hh @@ -47,8 +47,9 @@ // // -struct OpDesc : public SimObject +class OpDesc : public SimObject { + public: OpClass opClass; unsigned opLat; unsigned issueLat; @@ -58,8 +59,9 @@ struct OpDesc : public SimObject issueLat(p->issueLat) {}; }; -struct FUDesc : public SimObject +class FUDesc : public SimObject { + public: std::vector<OpDesc *> opDescList; unsigned number; diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 9614a5df2..5c806589d 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -83,7 +83,7 @@ InOrderCPU::TickEvent::process() const char * -InOrderCPU::TickEvent::description() +InOrderCPU::TickEvent::description() const { return "InOrderCPU tick event"; } @@ -168,7 +168,7 @@ InOrderCPU::CPUEvent::process() const char * -InOrderCPU::CPUEvent::description() +InOrderCPU::CPUEvent::description() const { return "InOrderCPU event"; } @@ -1168,11 +1168,11 @@ InOrderCPU::activateNextReadyContext(int delay) } void -InOrderCPU::haltContext(ThreadID tid, int delay) +InOrderCPU::haltContext(ThreadID tid) { DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid); - scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay); + scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]); activityRec.activity(); } @@ -1193,9 +1193,9 @@ InOrderCPU::haltThread(ThreadID tid) } void -InOrderCPU::suspendContext(ThreadID tid, int delay) +InOrderCPU::suspendContext(ThreadID tid) { - scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay); + scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]); } void diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 1559874cd..813179828 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -148,7 +148,7 @@ class InOrderCPU : public BaseCPU void process(); /** Returns the description of the tick event. */ - const char *description(); + const char *description() const; }; /** The tick event used for scheduling CPU ticks. */ @@ -230,7 +230,7 @@ class InOrderCPU : public BaseCPU void process(); /** Returns the description of the CPU event. */ - const char *description(); + const char *description() const; /** Schedule Event */ void scheduleEvent(int delay); @@ -472,13 +472,13 @@ class InOrderCPU : public BaseCPU void deactivateThread(ThreadID tid); /** Schedule a thread suspension on the CPU */ - void suspendContext(ThreadID tid, int delay = 0); + void suspendContext(ThreadID tid); /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */ void suspendThread(ThreadID tid); /** Schedule a thread halt on the CPU */ - void haltContext(ThreadID tid, int delay = 0); + void haltContext(ThreadID tid); /** Halt Thread, Remove from Active Thread List, Place Thread on Halted * Threads List diff --git a/src/cpu/inorder/resource.cc b/src/cpu/inorder/resource.cc index d2327795e..2ddce13c3 100644 --- a/src/cpu/inorder/resource.cc +++ b/src/cpu/inorder/resource.cc @@ -512,7 +512,7 @@ ResourceEvent::process() } const char * -ResourceEvent::description() +ResourceEvent::description() const { string desc = resource->name() + "-event:slot[" + to_string(slotIdx) + "]"; diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh index 78e5af5de..972925d94 100644 --- a/src/cpu/inorder/resource.hh +++ b/src/cpu/inorder/resource.hh @@ -51,6 +51,9 @@ class ResourceRequest; typedef ResourceRequest ResReq; typedef ResourceRequest* ResReqPtr; +class CacheRequest; +typedef CacheRequest* CacheReqPtr; + class Resource { public: typedef ThePipeline::DynInstPtr DynInstPtr; @@ -154,8 +157,9 @@ class Resource { * if instruction is actually in resource before * trying to do access.Needs to be defined for derived units. */ - virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL) - { panic("doCacheAccess undefined for %s", name()); return NoFault; } + virtual void doCacheAccess(DynInstPtr inst, uint64_t *write_result = NULL, + CacheReqPtr split_req = NULL) + { panic("doCacheAccess undefined for %s", name()); } /** Setup Squash to be sent out to pipeline and resource pool */ void setupSquash(DynInstPtr inst, int stage_num, ThreadID tid); @@ -283,7 +287,7 @@ class ResourceEvent : public Event virtual void process(); /** Returns the description of the resource event. */ - const char *description(); + const char *description() const; /** Set slot idx for event */ void setSlot(int slot) { slotIdx = slot; } @@ -320,7 +324,7 @@ class ResourceRequest int reqID; - virtual void setRequest(DynInstPtr _inst, int stage_num, + void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num, unsigned _cmd); virtual void clearRequest(); diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc index 0e89a7650..50d667ea7 100644 --- a/src/cpu/inorder/resource_pool.cc +++ b/src/cpu/inorder/resource_pool.cc @@ -485,7 +485,7 @@ ResourcePool::ResPoolEvent::process() const char * -ResourcePool::ResPoolEvent::description() +ResourcePool::ResPoolEvent::description() const { return "Resource Pool event"; } diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh index e892d750a..4f05494c4 100644 --- a/src/cpu/inorder/resource_pool.hh +++ b/src/cpu/inorder/resource_pool.hh @@ -118,7 +118,7 @@ class ResourcePool { void process(); /** Returns the description of the resource event. */ - const char *description(); + const char *description() const; /** Schedule Event */ void scheduleEvent(int delay); diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 6ca300163..209de4864 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -49,9 +49,6 @@ #include "params/InOrderCPU.hh" #include "sim/sim_object.hh" -class CacheRequest; -typedef CacheRequest* CacheReqPtr; - class CacheReqPacket; typedef CacheReqPacket* CacheReqPktPtr; diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc index 82e681f04..b062951ad 100644 --- a/src/cpu/inorder/thread_context.cc +++ b/src/cpu/inorder/thread_context.cc @@ -131,7 +131,7 @@ InOrderThreadContext::suspend(int delay) return; thread->setStatus(ThreadContext::Suspended); - cpu->suspendContext(thread->threadId(), delay); + cpu->suspendContext(thread->threadId()); } void @@ -144,7 +144,7 @@ InOrderThreadContext::halt(int delay) return; thread->setStatus(ThreadContext::Halted); - cpu->haltContext(thread->threadId(), delay); + cpu->haltContext(thread->threadId()); } diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh index 9869853c4..f6bf63d76 100644 --- a/src/cpu/nativetrace.hh +++ b/src/cpu/nativetrace.hh @@ -108,7 +108,7 @@ class NativeTrace : public ExeTracer { size_t soFar = 0; while (soFar < size) { - size_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar); + ssize_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar); if (res < 0) panic("Read call failed! %s\n", strerror(errno)); else diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh index 84f2dc8c1..8dbba9085 100644 --- a/src/cpu/o3/bpred_unit.hh +++ b/src/cpu/o3/bpred_unit.hh @@ -41,7 +41,7 @@ #include "cpu/pred/tournament.hh" #include "cpu/inst_seq.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; /** * Basically a wrapper class to hold both the branch predictor diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index ffc2c16d2..9f76d597f 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -51,10 +51,10 @@ #include "cpu/inst_seq.hh" #include "cpu/timebuf.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; template <class> -class O3ThreadState; +struct O3ThreadState; /** * DefaultCommit handles single threaded and SMT commit. Its width is diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 49843ee9b..cede7ae18 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -76,7 +76,7 @@ #include "debug/Activity.hh" #endif -class BaseCPUParams; +struct BaseCPUParams; using namespace TheISA; using namespace std; @@ -766,7 +766,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay) template <class Impl> bool -FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) +FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, + int delay) { // Schedule removal of thread data from CPU if (delay){ @@ -787,7 +788,7 @@ void FullO3CPU<Impl>::suspendContext(ThreadID tid) { DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); - bool deallocated = deallocateContext(tid, false, 1); + bool deallocated = scheduleDeallocateContext(tid, false, 1); // If this was the last thread then unschedule the tick event. if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0) @@ -804,7 +805,7 @@ FullO3CPU<Impl>::haltContext(ThreadID tid) { //For now, this is the same as deallocate DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); - deallocateContext(tid, true, 1); + scheduleDeallocateContext(tid, true, 1); } template <class Impl> @@ -1230,7 +1231,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) activityRec.reset(); - BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); + BaseCPU::takeOverFrom(oldCPU); fetch.takeOverFrom(); decode.takeOverFrom(); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index a874b1e9f..b5050854d 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -79,7 +79,7 @@ class Checkpoint; class MemObject; class Process; -class BaseCPUParams; +struct BaseCPUParams; class BaseO3CPU : public BaseCPU { @@ -401,7 +401,7 @@ class FullO3CPU : public BaseO3CPU /** Remove Thread from Active Threads List && * Possibly Remove Thread Context from CPU. */ - bool deallocateContext(ThreadID tid, bool remove, int delay = 1); + bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1); /** Remove Thread from Active Threads List && * Remove Thread Context from CPU. diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh index 482b4b7fc..663831254 100644 --- a/src/cpu/o3/decode.hh +++ b/src/cpu/o3/decode.hh @@ -36,7 +36,7 @@ #include "base/statistics.hh" #include "cpu/timebuf.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; /** * DefaultDecode class handles both single threaded and SMT diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index a523a8b45..7fa25106a 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -38,7 +38,9 @@ #include "debug/Decode.hh" #include "params/DerivO3CPU.hh" -using namespace std; +// clang complains about std::set being overloaded with Packet::set if +// we open up the entire namespace std +using std::list; template<class Impl> DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index f5d275593..b61ae2c7b 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -56,7 +56,7 @@ #include "mem/port.hh" #include "sim/eventq.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; /** * DefaultFetch class handles both single threaded and SMT fetch. Its diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc index b7c972b09..3f0e46543 100644 --- a/src/cpu/o3/fu_pool.cc +++ b/src/cpu/o3/fu_pool.cc @@ -252,7 +252,7 @@ FUPool::switchOut() } void -FUPool::takeOverFrom() +FUPool::takeOver() { for (int i = 0; i < numFU; i++) { unitBusy[i] = false; diff --git a/src/cpu/o3/fu_pool.hh b/src/cpu/o3/fu_pool.hh index ea4b53e1a..66804b534 100644 --- a/src/cpu/o3/fu_pool.hh +++ b/src/cpu/o3/fu_pool.hh @@ -37,7 +37,6 @@ #include <vector> #include "cpu/op_class.hh" -#include "cpu/sched_list.hh" #include "params/FUPool.hh" #include "sim/sim_object.hh" @@ -162,7 +161,7 @@ class FUPool : public SimObject void switchOut(); /** Takes over from another CPU's thread. */ - void takeOverFrom(); + void takeOver(); }; #endif // __CPU_O3_FU_POOL_HH__ diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index c58361cd6..d3d1a7dbb 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -54,7 +54,7 @@ #include "cpu/timebuf.hh" #include "debug/IEW.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; class FUPool; /** @@ -94,9 +94,6 @@ class DefaultIEW typedef typename CPUPol::RenameStruct RenameStruct; typedef typename CPUPol::IssueStruct IssueStruct; - friend class Impl::O3CPU; - friend class CPUPol::IQ; - public: /** Overall IEW stage status. Used to determine if the CPU can * deschedule itself due to a lack of activity. diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 698dd15c4..97b41ad9f 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -412,7 +412,7 @@ DefaultIEW<Impl>::takeOverFrom() instQueue.takeOverFrom(); ldstQueue.takeOverFrom(); - fuPool->takeOverFrom(); + fuPool->takeOver(); initStage(); cpu->activityThisCycle(); diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index eb35fd285..9ceab1525 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -56,7 +56,7 @@ #include "cpu/timebuf.hh" #include "sim/eventq.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; class FUPool; class MemInterface; @@ -93,8 +93,6 @@ class InstructionQueue // Typedef of iterator through the list of instructions. typedef typename std::list<DynInstPtr>::iterator ListIt; - friend class Impl::O3CPU; - /** FU completion event class. */ class FUCompletion : public Event { private: diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index b2016cc9c..2c0779a03 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -51,7 +51,9 @@ #include "params/DerivO3CPU.hh" #include "sim/core.hh" -using namespace std; +// clang complains about std::set being overloaded with Packet::set if +// we open up the entire namespace std +using std::list; template <class Impl> InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 731c67ae6..78738fc45 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -52,7 +52,7 @@ #include "mem/port.hh" #include "sim/sim_object.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; template <class Impl> class LSQ { diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index a11d95f3b..4a2369de3 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -52,7 +52,7 @@ #include "mem/packet.hh" #include "mem/port.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; /** * Class that implements the actual LQ and SQ for each specific diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc index ac0db4784..234a6f9c4 100644 --- a/src/cpu/o3/mem_dep_unit.cc +++ b/src/cpu/o3/mem_dep_unit.cc @@ -32,10 +32,6 @@ #include "cpu/o3/mem_dep_unit_impl.hh" #include "cpu/o3/store_set.hh" -// Force instantation of memory dependency unit using store sets and -// O3CPUImpl. -template class MemDepUnit<StoreSet, O3CPUImpl>; - #ifdef DEBUG template <> int @@ -47,3 +43,7 @@ template <> int MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0; #endif + +// Force instantation of memory dependency unit using store sets and +// O3CPUImpl. +template class MemDepUnit<StoreSet, O3CPUImpl>; diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index 7d00369d3..ce5a62ef8 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -49,7 +49,7 @@ struct SNHash { } }; -class DerivO3CPUParams; +struct DerivO3CPUParams; template <class Impl> class InstructionQueue; diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index e2472a62d..a5c83dfea 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -37,7 +37,7 @@ #include "config/the_isa.hh" #include "cpu/timebuf.hh" -class DerivO3CPUParams; +struct DerivO3CPUParams; /** * DefaultRename handles both single threaded and SMT rename. Its diff --git a/src/cpu/o3/sat_counter.hh b/src/cpu/o3/sat_counter.hh index 7dd840f31..17ff8546b 100644 --- a/src/cpu/o3/sat_counter.hh +++ b/src/cpu/o3/sat_counter.hh @@ -65,7 +65,8 @@ class SatCounter * @param initial_val Starting value for each counter. */ SatCounter(unsigned bits, uint8_t initial_val) - : initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val) + : initialVal(initial_val), maxVal((1 << bits) - 1), + counter(initial_val) { // Check to make sure initial value doesn't exceed the max // counter value. diff --git a/src/cpu/quiesce_event.hh b/src/cpu/quiesce_event.hh index 85c88ab32..74db27481 100644 --- a/src/cpu/quiesce_event.hh +++ b/src/cpu/quiesce_event.hh @@ -36,8 +36,9 @@ class ThreadContext; /** Event for timing out quiesce instruction */ -struct EndQuiesceEvent : public Event +class EndQuiesceEvent : public Event { + public: /** A pointer to the thread context that is quiesced */ ThreadContext *tc; diff --git a/src/cpu/sched_list.hh b/src/cpu/sched_list.hh deleted file mode 100644 index 4d3b0dd71..000000000 --- a/src/cpu/sched_list.hh +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Raasch - */ - -#ifndef SCHED_LIST_HH -#define SCHED_LIST_HH - -#include <list> - -#include "base/intmath.hh" -#include "base/misc.hh" - -// Any types you use this class for must be covered here... -namespace { - void ClearEntry(int &i) { i = 0; }; - void ClearEntry(unsigned &i) { i = 0; }; - void ClearEntry(double &i) { i = 0; }; - template <class T> void ClearEntry(std::list<T> &l) { l.clear(); }; -}; - - -// -// this is a special list type that allows the user to insert elements at a -// specified positive offset from the "current" element, but only allow them -// be extracted from the "current" element -// - - -template <class T> -class SchedList -{ - T *data_array; - unsigned position; - unsigned size; - unsigned mask; - - public: - SchedList(unsigned size); - SchedList(void); - - void init(unsigned size); - - T &operator[](unsigned offset); - - void advance(void); - - void clear(void); -}; - - - -// -// Constructor -// -template<class T> -SchedList<T>::SchedList(unsigned _size) -{ - size = _size; - - // size must be a power of two - if (!isPowerOf2(size)) { - panic("SchedList: size must be a power of two"); - } - - if (size < 2) { - panic("SchedList: you don't want a list that small"); - } - - // calculate the bit mask for the modulo operation - mask = size - 1; - - data_array = new T[size]; - - if (!data_array) { - panic("SchedList: could not allocate memory"); - } - - clear(); -} - -template<class T> -SchedList<T>::SchedList(void) -{ - data_array = 0; - size = 0; -} - - -template<class T> void -SchedList<T>::init(unsigned _size) -{ - size = _size; - - if (!data_array) { - // size must be a power of two - if (size & (size-1)) { - panic("SchedList: size must be a power of two"); - } - - if (size < 2) { - panic("SchedList: you don't want a list that small"); - } - - // calculate the bit mask for the modulo operation - mask = size - 1; - - data_array = new T[size]; - - if (!data_array) { - panic("SchedList: could not allocate memory"); - } - - clear(); - } -} - - -template<class T> void -SchedList<T>::advance(void) -{ - ClearEntry(data_array[position]); - - // position = (++position % size); - position = ++position & mask; -} - - -template<class T> void -SchedList<T>::clear(void) -{ - for (unsigned i=0; i<size; ++i) { - ClearEntry(data_array[i]); - } - - position = 0; -} - - -template<class T> T& -SchedList<T>::operator[](unsigned offset) -{ - if (offset >= size) { - panic("SchedList: can't access element beyond current pointer"); - } - - // unsigned p = (position + offset) % size; - unsigned p = (position + offset) & mask; - - return data_array[p]; -} - - - -#endif diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 425c8b1f1..5fcfeb7de 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -174,7 +174,7 @@ AtomicSimpleCPU::switchOut() void AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) { - BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); + BaseCPU::takeOverFrom(oldCPU); assert(!tickEvent.scheduled()); @@ -200,7 +200,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) void -AtomicSimpleCPU::activateContext(int thread_num, int delay) +AtomicSimpleCPU::activateContext(ThreadID thread_num, int delay) { DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); @@ -220,7 +220,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay) void -AtomicSimpleCPU::suspendContext(int thread_num) +AtomicSimpleCPU::suspendContext(ThreadID thread_num) { DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 77a9d6b0d..f677ed49b 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -112,8 +112,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU void switchOut(); void takeOverFrom(BaseCPU *oldCPU); - virtual void activateContext(int thread_num, int delay); - virtual void suspendContext(int thread_num); + virtual void activateContext(ThreadID thread_num, int delay); + virtual void suspendContext(ThreadID thread_num); Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 2ec9e661f..e56dc0fbb 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -139,7 +139,7 @@ BaseSimpleCPU::~BaseSimpleCPU() } void -BaseSimpleCPU::deallocateContext(int thread_num) +BaseSimpleCPU::deallocateContext(ThreadID thread_num) { // for now, these are equivalent suspendContext(thread_num); @@ -147,7 +147,7 @@ BaseSimpleCPU::deallocateContext(int thread_num) void -BaseSimpleCPU::haltContext(int thread_num) +BaseSimpleCPU::haltContext(ThreadID thread_num) { // for now, these are equivalent suspendContext(thread_num); diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 56e5e5608..3535539d0 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -92,7 +92,7 @@ namespace Trace { class InstRecord; } -class BaseSimpleCPUParams; +struct BaseSimpleCPUParams; class BaseSimpleCPU : public BaseCPU @@ -189,8 +189,8 @@ class BaseSimpleCPU : public BaseCPU void postExecute(); void advancePC(Fault fault); - virtual void deallocateContext(int thread_num); - virtual void haltContext(int thread_num); + virtual void deallocateContext(ThreadID thread_num); + virtual void haltContext(ThreadID thread_num); // statistics virtual void regStats(); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index f8d13efd9..a0a773236 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -176,7 +176,7 @@ TimingSimpleCPU::switchOut() void TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) { - BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); + BaseCPU::takeOverFrom(oldCPU); // if any of this CPU's ThreadContexts are active, mark the CPU as // running and schedule its tick event. @@ -197,7 +197,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) void -TimingSimpleCPU::activateContext(int thread_num, int delay) +TimingSimpleCPU::activateContext(ThreadID thread_num, int delay) { DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); @@ -215,7 +215,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay) void -TimingSimpleCPU::suspendContext(int thread_num) +TimingSimpleCPU::suspendContext(ThreadID thread_num) { DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index dce3c58ff..ed91524cf 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -244,8 +244,8 @@ class TimingSimpleCPU : public BaseSimpleCPU void switchOut(); void takeOverFrom(BaseCPU *oldCPU); - virtual void activateContext(int thread_num, int delay); - virtual void suspendContext(int thread_num); + virtual void activateContext(ThreadID thread_num, int delay); + virtual void suspendContext(ThreadID thread_num); Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index adda82c49..7c5fcaa3a 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -52,7 +52,7 @@ class ThreadContext; class DynInst; class Packet; -class O3CPUImpl; +struct O3CPUImpl; template <class Impl> class BaseO3DynInst; typedef BaseO3DynInst<O3CPUImpl> O3DynInst; template <class Impl> class OzoneDynInst; |