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-rw-r--r--src/cpu/SConscript3
-rw-r--r--src/cpu/base.cc4
-rw-r--r--src/cpu/exetrace.cc4
-rw-r--r--src/cpu/func_unit.cc54
-rw-r--r--src/cpu/intr_control.cc21
-rw-r--r--src/cpu/memtest/memtest.cc54
-rw-r--r--src/cpu/o3/alpha/cpu_builder.cc254
-rw-r--r--src/cpu/o3/checker_builder.cc72
-rw-r--r--src/cpu/o3/cpu.cc18
-rw-r--r--src/cpu/o3/fu_pool.cc25
-rw-r--r--src/cpu/o3/inst_queue_impl.hh10
-rw-r--r--src/cpu/o3/mips/cpu_builder.cc230
-rw-r--r--src/cpu/o3/sparc/cpu_builder.cc255
-rw-r--r--src/cpu/op_class.cc52
-rw-r--r--src/cpu/op_class.hh52
-rw-r--r--src/cpu/ozone/checker_builder.cc72
-rw-r--r--src/cpu/ozone/cpu_builder.cc273
-rw-r--r--src/cpu/ozone/simple_cpu_builder.cc261
-rw-r--r--src/cpu/simple/atomic.cc85
-rw-r--r--src/cpu/simple/base.cc1
-rw-r--r--src/cpu/simple/timing.cc85
-rw-r--r--src/cpu/trace/opt_cpu.cc32
-rw-r--r--src/cpu/trace/reader/ibm_reader.cc25
-rw-r--r--src/cpu/trace/reader/itx_reader.cc25
-rw-r--r--src/cpu/trace/reader/m5_reader.cc23
-rw-r--r--src/cpu/trace/reader/mem_trace_reader.cc39
-rw-r--r--src/cpu/trace/trace_cpu.cc28
27 files changed, 142 insertions, 1915 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index cce13a072..adf47fa4d 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -72,7 +72,7 @@ temp_cpu_list = env['CPU_MODELS'][:]
if env['USE_CHECKER']:
temp_cpu_list.append('CheckerCPU')
-# Generate header.
+# Generate header.
def gen_cpu_exec_signatures(target, source, env):
f = open(str(target[0]), 'w')
print >> f, '''
@@ -111,7 +111,6 @@ Source('base.cc')
Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
-Source('op_class.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index f86313da0..17c04907a 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -42,7 +42,6 @@
#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
#include "sim/sim_exit.hh"
-#include "sim/param.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "sim/system.hh"
@@ -455,6 +454,3 @@ BaseCPU::traceFunctionsInternal(Addr pc)
functionEntryTick = curTick;
}
}
-
-
-DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 85df19348..25d41811e 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -46,7 +46,7 @@
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
-#include "sim/param.hh"
+#include "enums/OpClass.hh"
#include "sim/system.hh"
#if FULL_SYSTEM
@@ -355,7 +355,7 @@ Trace::InstRecord::dump()
outs << " : ";
if (IsOn(ExecOpClass)) {
- outs << opClassStrings[staticInst->opClass()] << " : ";
+ outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
}
if (IsOn(ExecResult) && data_status != DataInvalid) {
diff --git a/src/cpu/func_unit.cc b/src/cpu/func_unit.cc
index c20578a43..d7aeb5b37 100644
--- a/src/cpu/func_unit.cc
+++ b/src/cpu/func_unit.cc
@@ -32,7 +32,8 @@
#include "base/misc.hh"
#include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/OpDesc.hh"
+#include "params/FUDesc.hh"
using namespace std;
@@ -116,56 +117,17 @@ FuncUnit::issueLatency(OpClass capability)
//
// The operation-class description object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
- SimpleEnumParam<OpClass> opClass;
- Param<unsigned> opLat;
- Param<unsigned> issueLat;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
- INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
- INIT_PARAM(opLat, "cycles until result is available"),
- INIT_PARAM(issueLat, "cycles until another can be issued")
-
-END_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-
-CREATE_SIM_OBJECT(OpDesc)
+OpDesc *
+OpDescParams::create()
{
- return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
+ return new OpDesc(name, opClass, opLat, issueLat);
}
-REGISTER_SIM_OBJECT("OpDesc", OpDesc)
-
-
//
// The FuDesc object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
- SimObjectVectorParam<OpDesc *> opList;
- Param<unsigned> count;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
- INIT_PARAM(opList, "list of operation classes for this FU type"),
- INIT_PARAM(count, "number of these FU's available")
-
-END_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-
-CREATE_SIM_OBJECT(FUDesc)
+FUDesc *
+FUDescParams::create()
{
- return new FUDesc(getInstanceName(), opList, count);
+ return new FUDesc(name, opList, count);
}
-
-REGISTER_SIM_OBJECT("FUDesc", FUDesc)
-
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index be0f6599b..e9f27e9ed 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -35,7 +35,7 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
-#include "sim/builder.hh"
+#include "params/IntrControl.hh"
#include "sim/sim_object.hh"
using namespace std;
@@ -76,21 +76,8 @@ IntrControl::clear(int cpu_id, int int_num, int index)
temp->clear_interrupt(int_num, index);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
- SimObjectParam<System *> sys;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
- INIT_PARAM(sys, "the system we are part of")
-
-END_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-CREATE_SIM_OBJECT(IntrControl)
+IntrControl *
+IntrControlParams::create()
{
- return new IntrControl(getInstanceName(), sys);
+ return new IntrControl(name, sys);
}
-
-REGISTER_SIM_OBJECT("IntrControl", IntrControl)
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 15774904a..23e2297fe 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -46,7 +46,7 @@
#include "mem/packet.hh"
//#include "mem/physical.hh"
#include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/MemTest.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
@@ -496,53 +496,15 @@ MemTest::doRetry()
}
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-// SimObjectParam<BaseCache *> cache;
-// SimObjectParam<PhysicalMemory *> main_mem;
-// SimObjectParam<PhysicalMemory *> check_mem;
- Param<unsigned> memory_size;
- Param<unsigned> percent_reads;
- Param<unsigned> percent_functional;
- Param<unsigned> percent_uncacheable;
- Param<unsigned> progress_interval;
- Param<unsigned> percent_source_unaligned;
- Param<unsigned> percent_dest_unaligned;
- Param<Addr> trace_addr;
- Param<Counter> max_loads;
- Param<bool> atomic;
-
-END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-// INIT_PARAM(cache, "L1 cache"),
-// INIT_PARAM(main_mem, "hierarchical memory"),
-// INIT_PARAM(check_mem, "check memory"),
- INIT_PARAM(memory_size, "memory size"),
- INIT_PARAM(percent_reads, "target read percentage"),
- INIT_PARAM(percent_functional, "percentage of access that are functional"),
- INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
- INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
- INIT_PARAM(percent_source_unaligned,
- "percent of copy source address that are unaligned"),
- INIT_PARAM(percent_dest_unaligned,
- "percent of copy dest address that are unaligned"),
- INIT_PARAM(trace_addr, "address to trace"),
- INIT_PARAM(max_loads, "terminate when we have reached this load count"),
- INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
-
-END_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-
-CREATE_SIM_OBJECT(MemTest)
+MemTest *
+MemTestParams::create()
{
- return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
- /*check_mem,*/ memory_size, percent_reads, percent_functional,
+ return new MemTest(name,
+#if 0
+ cache->getInterface(), main_mem, check_mem,
+#endif
+ memory_size, percent_reads, percent_functional,
percent_uncacheable, progress_interval,
percent_source_unaligned, percent_dest_unaligned,
trace_addr, max_loads, atomic);
}
-
-REGISTER_SIM_OBJECT("MemTest", MemTest)
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index 34754d3c5..58ee52a39 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -30,12 +30,13 @@
#include <string>
+#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/alpha/cpu.hh"
#include "cpu/o3/alpha/impl.hh"
#include "cpu/o3/alpha/params.hh"
#include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
{
@@ -45,245 +46,8 @@ class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
{ }
};
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- Param<int> clock;
- Param<int> phase;
- Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-SimObjectParam<AlphaISA::ITB *> itb;
-SimObjectParam<AlphaISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
- INIT_PARAM(profile, ""),
-
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
- INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(dispatchWidth, "Dispatch width"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(wbWidth, "Writeback width"),
- INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
- INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
- INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
- INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
- INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
@@ -294,8 +58,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
- (numThreads.isValid() && numThreads >= workload.size()) ?
- numThreads : workload.size();
+ (numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
@@ -307,7 +70,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->clock = clock;
params->phase = phase;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
@@ -325,7 +88,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->workload = workload;
#endif // FULL_SYSTEM
+#if USE_CHECKER
params->checker = checker;
+#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@@ -429,6 +194,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 8b028e3a0..97425b08c 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -34,7 +34,7 @@
#include "cpu/inst_seq.hh"
#include "cpu/o3/alpha/dyn_inst.hh"
#include "cpu/o3/alpha/impl.hh"
-#include "sim/builder.hh"
+#include "params/O3Checker.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@@ -58,73 +58,11 @@ class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> >
//
// CheckerCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
- Param<Tick> profile;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
- Param<int> clock;
-
- Param<bool> defer_registration;
- Param<bool> exitOnError;
- Param<bool> updateOnError;
- Param<bool> warnOnlyOnLoadError;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(profile, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
-
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(exitOnError, "exit on error"),
- INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
- INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
- "result errors", false),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
-
-CREATE_SIM_OBJECT(O3Checker)
+O3Checker *
+O3CheckerParams::create()
{
O3Checker::Params *params = new O3Checker::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = 0;
params->max_insts_all_threads = 0;
@@ -161,5 +99,3 @@ CREATE_SIM_OBJECT(O3Checker)
O3Checker *cpu = new O3Checker(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("O3Checker", O3Checker)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 6a3eb9c43..20ed5df63 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -32,22 +32,22 @@
#include "config/full_system.hh"
#include "config/use_checker.hh"
-#if FULL_SYSTEM
-#include "cpu/quiesce_event.hh"
-#include "sim/system.hh"
-#else
-#include "sim/process.hh"
-#endif
-
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/cpu.hh"
-
+#include "enums/MemoryMode.hh"
#include "sim/core.hh"
#include "sim/stat_control.hh"
+#if FULL_SYSTEM
+#include "cpu/quiesce_event.hh"
+#include "sim/system.hh"
+#else
+#include "sim/process.hh"
+#endif
+
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#endif
@@ -882,7 +882,7 @@ FullO3CPU<Impl>::resume()
return;
#if FULL_SYSTEM
- assert(system->getMemoryMode() == System::Timing);
+ assert(system->getMemoryMode() == Enums::timing);
#endif
if (!tickEvent.scheduled())
diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc
index 42e329aca..09d271b10 100644
--- a/src/cpu/o3/fu_pool.cc
+++ b/src/cpu/o3/fu_pool.cc
@@ -32,7 +32,7 @@
#include "cpu/o3/fu_pool.hh"
#include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/FUPool.hh"
using namespace std;
@@ -275,25 +275,8 @@ FUPool::takeOverFrom()
//
// The FuPool object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool)
-
- SimObjectVectorParam<FUDesc *> FUList;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUPool)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool)
-
- INIT_PARAM(FUList, "list of FU's for this pool")
-
-END_INIT_SIM_OBJECT_PARAMS(FUPool)
-
-
-CREATE_SIM_OBJECT(FUPool)
+FUPool *
+FUPoolParams::create()
{
- return new FUPool(getInstanceName(), FUList);
+ return new FUPool(name, FUList);
}
-
-REGISTER_SIM_OBJECT("FUPool", FUPool)
-
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index bdf5f07aa..bbdd4ddd5 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -32,10 +32,10 @@
#include <limits>
#include <vector>
-#include "sim/core.hh"
-
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
+#include "enums/OpClass.hh"
+#include "sim/core.hh"
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
@@ -259,12 +259,12 @@ InstructionQueue<Impl>::regStats()
}
*/
statIssuedInstType
- .init(numThreads,Num_OpClasses)
+ .init(numThreads,Enums::Num_OpClass)
.name(name() + ".ISSUE:FU_type")
.desc("Type of FU issued")
.flags(total | pdf | dist)
;
- statIssuedInstType.ysubnames(opClassStrings);
+ statIssuedInstType.ysubnames(Enums::OpClassStrings);
//
// How long did instructions for a particular FU type wait prior to issue
@@ -297,7 +297,7 @@ InstructionQueue<Impl>::regStats()
.flags(pdf | dist)
;
for (int i=0; i < Num_OpClasses; ++i) {
- statFuBusy.subname(i, opClassStrings[i]);
+ statFuBusy.subname(i, Enums::OpClassStrings[i]);
}
fuBusy
diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc
index c6acc0bfb..6a30ff099 100644
--- a/src/cpu/o3/mips/cpu_builder.cc
+++ b/src/cpu/o3/mips/cpu_builder.cc
@@ -31,12 +31,13 @@
#include <string>
+#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/mips/cpu.hh"
#include "cpu/o3/mips/impl.hh"
#include "cpu/o3/mips/params.hh"
#include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
{
@@ -46,229 +47,15 @@ class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
{ }
};
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-Param<int> clock;
-Param<int> phase;
-Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-SimObjectVectorParam<Process *> workload;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
- INIT_PARAM(workload, "Processes to run"),
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(dispatchWidth, "Dispatch width"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(wbWidth, "Writeback width"),
- INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
- INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
- INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
- INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
- INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
- (numThreads.isValid() && numThreads >= workload.size()) ?
- numThreads : workload.size();
+ (numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
@@ -279,14 +66,16 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->clock = clock;
params->phase = phase;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
params->workload = workload;
+#if USE_CHECKER
params->checker = checker;
+#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@@ -389,6 +178,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc
index 35badce2c..35d9e2895 100644
--- a/src/cpu/o3/sparc/cpu_builder.cc
+++ b/src/cpu/o3/sparc/cpu_builder.cc
@@ -30,12 +30,14 @@
#include <string>
+#include "config/full_system.hh"
+#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/sparc/cpu.hh"
#include "cpu/o3/sparc/impl.hh"
#include "cpu/o3/sparc/params.hh"
#include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
{
@@ -45,245 +47,8 @@ class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
{ }
};
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- Param<int> clock;
- Param<int> phase;
- Param<int> numThreads;
- Param<int> cpu_id;
- Param<int> activity;
-
-#if FULL_SYSTEM
- SimObjectParam<System *> system;
- SimObjectParam<SparcISA::ITB *> itb;
- SimObjectParam<SparcISA::DTB *> dtb;
- Param<Tick> profile;
-
- Param<bool> do_quiesce;
- Param<bool> do_checkpoint_insts;
- Param<bool> do_statistics_insts;
-#else
- SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
- SimObjectParam<BaseCPU *> checker;
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
-
- Param<unsigned> cachePorts;
-
- Param<unsigned> decodeToFetchDelay;
- Param<unsigned> renameToFetchDelay;
- Param<unsigned> iewToFetchDelay;
- Param<unsigned> commitToFetchDelay;
- Param<unsigned> fetchWidth;
-
- Param<unsigned> renameToDecodeDelay;
- Param<unsigned> iewToDecodeDelay;
- Param<unsigned> commitToDecodeDelay;
- Param<unsigned> fetchToDecodeDelay;
- Param<unsigned> decodeWidth;
-
- Param<unsigned> iewToRenameDelay;
- Param<unsigned> commitToRenameDelay;
- Param<unsigned> decodeToRenameDelay;
- Param<unsigned> renameWidth;
-
- Param<unsigned> commitToIEWDelay;
- Param<unsigned> renameToIEWDelay;
- Param<unsigned> issueToExecuteDelay;
- Param<unsigned> dispatchWidth;
- Param<unsigned> issueWidth;
- Param<unsigned> wbWidth;
- Param<unsigned> wbDepth;
- SimObjectParam<FUPool *> fuPool;
-
- Param<unsigned> iewToCommitDelay;
- Param<unsigned> renameToROBDelay;
- Param<unsigned> commitWidth;
- Param<unsigned> squashWidth;
- Param<Tick> trapLatency;
-
- Param<unsigned> backComSize;
- Param<unsigned> forwardComSize;
-
- Param<std::string> predType;
- Param<unsigned> localPredictorSize;
- Param<unsigned> localCtrBits;
- Param<unsigned> localHistoryTableSize;
- Param<unsigned> localHistoryBits;
- Param<unsigned> globalPredictorSize;
- Param<unsigned> globalCtrBits;
- Param<unsigned> globalHistoryBits;
- Param<unsigned> choicePredictorSize;
- Param<unsigned> choiceCtrBits;
-
- Param<unsigned> BTBEntries;
- Param<unsigned> BTBTagSize;
-
- Param<unsigned> RASSize;
-
- Param<unsigned> LQEntries;
- Param<unsigned> SQEntries;
- Param<unsigned> LFSTSize;
- Param<unsigned> SSITSize;
-
- Param<unsigned> numPhysIntRegs;
- Param<unsigned> numPhysFloatRegs;
- Param<unsigned> numIQEntries;
- Param<unsigned> numROBEntries;
-
- Param<unsigned> smtNumFetchingThreads;
- Param<std::string> smtFetchPolicy;
- Param<std::string> smtLSQPolicy;
- Param<unsigned> smtLSQThreshold;
- Param<std::string> smtIQPolicy;
- Param<unsigned> smtIQThreshold;
- Param<std::string> smtROBPolicy;
- Param<unsigned> smtROBThreshold;
- Param<std::string> smtCommitPolicy;
-
- Param<unsigned> instShiftAmt;
-
- Param<bool> defer_registration;
-
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
- INIT_PARAM(profile, ""),
-
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
- INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(dispatchWidth, "Dispatch width"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(wbWidth, "Writeback width"),
- INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
- INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
- INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
- INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
- INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
@@ -294,8 +59,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
- (numThreads.isValid() && numThreads >= workload.size()) ?
- numThreads : workload.size();
+ (numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
@@ -307,7 +71,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->clock = clock;
params->phase = phase;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
@@ -325,7 +89,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->workload = workload;
#endif // FULL_SYSTEM
+#if USE_CHECKER
params->checker = checker;
+#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@@ -429,6 +195,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
diff --git a/src/cpu/op_class.cc b/src/cpu/op_class.cc
deleted file mode 100644
index 02cb4a08a..000000000
--- a/src/cpu/op_class.cc
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#include "cpu/op_class.hh"
-
-/** OpClass enum -> description string */
-const char *
-opClassStrings[Num_OpClasses] =
-{
- "No_OpClass",
- "IntAlu",
- "IntMult",
- "IntDiv",
- "FloatAdd",
- "FloatCmp",
- "FloatCvt",
- "FloatMult",
- "FloatDiv",
- "FloatSqrt",
- "MemRead",
- "MemWrite",
- "IprAccess",
- "InstPrefetch"
-};
-
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 71819c904..8cbe10f91 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -25,43 +25,35 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Steve Reinhardt
- * Nathan Binkert
+ * Authors: Nathan Binkert
*/
#ifndef __CPU__OP_CLASS_HH__
#define __CPU__OP_CLASS_HH__
-/**
- * @file
- * Definition of operation classes.
- */
+#include "enums/OpClass.hh"
-/**
- * Instruction operation classes. These classes are used for
- * assigning instructions to functional units.
+/*
+ * Do a bunch of wonky stuff to maintain backward compatability so I
+ * don't have to change code in a zillion places.
*/
-enum OpClass {
- No_OpClass = 0, ///< Instruction does not use a functional unit
- IntAluOp, ///< Integer ALU operaton (add/sub/logical)
- IntMultOp, ///< Integer multiply
- IntDivOp, ///< Integer divide
- FloatAddOp, ///< Floating point add/subtract
- FloatCmpOp, ///< Floating point comparison
- FloatCvtOp, ///< Floating point<->integer conversion
- FloatMultOp, ///< Floating point multiply
- FloatDivOp, ///< Floating point divide
- FloatSqrtOp, ///< Floating point square root
- MemReadOp, ///< Memory read port
- MemWriteOp, ///< Memory write port
- IprAccessOp, ///< Internal Processor Register read/write port
- InstPrefetchOp, ///< Instruction prefetch port (on I-cache)
- Num_OpClasses ///< Total number of operation classes
-};
+using Enums::OpClass;
+using Enums::No_OpClass;
+using Enums::Num_OpClass;
-/**
- * Array mapping OpClass enum values to strings. Defined in op_class.cc.
- */
-extern const char *opClassStrings[Num_OpClasses];
+const OpClass IntAluOp = Enums::IntAlu;
+const OpClass IntMultOp = Enums::IntMult;
+const OpClass IntDivOp = Enums::IntDiv;
+const OpClass FloatAddOp = Enums::FloatAdd;
+const OpClass FloatCmpOp = Enums::FloatCmp;
+const OpClass FloatCvtOp = Enums::FloatCvt;
+const OpClass FloatMultOp = Enums::FloatMult;
+const OpClass FloatDivOp = Enums::FloatDiv;
+const OpClass FloatSqrtOp = Enums::FloatSqrt;
+const OpClass MemReadOp = Enums::MemRead;
+const OpClass MemWriteOp = Enums::MemWrite;
+const OpClass IprAccessOp = Enums::IprAccess;
+const OpClass InstPrefetchOp = Enums::InstPrefetch;
+const OpClass Num_OpClasses = Num_OpClass;
#endif // __CPU__OP_CLASS_HH__
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index 9ad1e639f..f813e5df2 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -34,7 +34,7 @@
#include "cpu/inst_seq.hh"
#include "cpu/ozone/dyn_inst.hh"
#include "cpu/ozone/ozone_impl.hh"
-#include "sim/builder.hh"
+#include "params/OzoneChecker.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@@ -59,73 +59,11 @@ class OzoneChecker :
//
// CheckerCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
- Param<Tick> profile;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
- Param<int> clock;
-
- Param<bool> defer_registration;
- Param<bool> exitOnError;
- Param<bool> updateOnError;
- Param<bool> warnOnlyOnLoadError;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(profile, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
-
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(exitOnError, "exit on error"),
- INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
- INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
- "result errors", false),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
-
-CREATE_SIM_OBJECT(OzoneChecker)
+OzoneChecker *
+OzoneCheckerParams::create()
{
OzoneChecker::Params *params = new OzoneChecker::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = 0;
params->max_insts_all_threads = 0;
@@ -162,5 +100,3 @@ CREATE_SIM_OBJECT(OzoneChecker)
OzoneChecker *cpu = new OzoneChecker(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index e7ecfc496..60ee9c4f9 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -35,7 +35,7 @@
#include "cpu/ozone/cpu.hh"
#include "cpu/ozone/ozone_impl.hh"
#include "cpu/ozone/simple_params.hh"
-#include "sim/builder.hh"
+#include "params/DerivOzoneCPU.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@@ -52,271 +52,8 @@ class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
//
// OzoneCPU Simulation Object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
- Param<int> clock;
- Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-//SimObjectParam<BaseCache *> icache;
-//SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndLatency;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndLatency;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-Param<unsigned> maxOutstandingMemOps;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<bool> lsqLimits;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
- INIT_PARAM(profile, ""),
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "Processes to run"),
-// INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
- INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-// INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
-// INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
- INIT_PARAM_DFLT(width, "Width", 1),
- INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
- INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
- INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
- INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
- INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
- INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
- INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
- INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(executeWidth, "Execute width"),
- INIT_PARAM(executeIntWidth, "Integer execute width"),
- INIT_PARAM(executeFloatWidth, "Floating point execute width"),
- INIT_PARAM(executeBranchWidth, "Branch execute width"),
- INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
- INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
- INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-CREATE_SIM_OBJECT(DerivOzoneCPU)
+DerivOzoneCPU *
+DerivOzoneCPUParams::create()
{
DerivOzoneCPU *cpu;
@@ -339,7 +76,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->clock = clock;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
#if FULL_SYSTEM
@@ -464,5 +201,3 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index e7214d2ba..df8e25fd0 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -36,7 +36,7 @@
#include "cpu/ozone/simple_impl.hh"
#include "cpu/ozone/simple_params.hh"
#include "mem/cache/base_cache.hh"
-#include "sim/builder.hh"
+#include "sim/SimpleOzoneCPU.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@@ -55,258 +55,8 @@ class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
//
// OzoneCPU Simulation Object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
- Param<int> clock;
- Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<FunctionalMemory *> mem;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-SimObjectParam<BaseCache *> icache;
-SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> backEndLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
-#else
- INIT_PARAM(workload, "Processes to run"),
-// INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(mem, "Memory", NULL),
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
-
- INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
- INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
- INIT_PARAM_DFLT(width, "Width", 1),
- INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
- INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
- INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
- INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
- INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
- INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(executeWidth, "Execute width"),
- INIT_PARAM(executeIntWidth, "Integer execute width"),
- INIT_PARAM(executeFloatWidth, "Floating point execute width"),
- INIT_PARAM(executeBranchWidth, "Branch execute width"),
- INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
- INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
- INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-CREATE_SIM_OBJECT(SimpleOzoneCPU)
+SimpleOzoneCPU *
+SimpleOzoneCPUParams::create()
{
SimpleOzoneCPU *cpu;
@@ -329,7 +79,7 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
params->clock = clock;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
#if FULL_SYSTEM
@@ -447,6 +197,3 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
return cpu;
}
-
-REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
-
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 03ff1282b..b2c24daad 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -36,7 +36,7 @@
#include "cpu/simple/atomic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/AtomicSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
@@ -198,7 +198,7 @@ void
AtomicSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
- assert(system->getMemoryMode() == System::Atomic);
+ assert(system->getMemoryMode() == Enums::atomic);
changeState(SimObject::Running);
if (thread->status() == ThreadContext::Active) {
@@ -570,79 +570,11 @@ AtomicSimpleCPU::tick()
//
// AtomicSimpleCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- Param<Tick> profile;
-
- Param<bool> do_quiesce;
- Param<bool> do_checkpoint_insts;
- Param<bool> do_statistics_insts;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
- Param<int> clock;
- Param<int> phase;
-
- Param<bool> defer_registration;
- Param<int> width;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
- Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM(progress_interval, "Progress interval"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(profile, ""),
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(width, "cpu width"),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace"),
- INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-
-CREATE_SIM_OBJECT(AtomicSimpleCPU)
+AtomicSimpleCPU *
+AtomicSimpleCPUParams::create()
{
AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@@ -667,12 +599,11 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
- params->process = workload;
+ if (workload.size() != 1)
+ panic("only one workload allowed");
+ params->process = workload[0];
#endif
AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
-
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 9285aa7b5..4359ebebf 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -47,7 +47,6 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
-#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7698a588d..754bd8c5f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -35,7 +35,7 @@
#include "cpu/simple/timing.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/TimingSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
@@ -158,7 +158,7 @@ void
TimingSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
- assert(system->getMemoryMode() == System::Timing);
+ assert(system->getMemoryMode() == Enums::timing);
// Delete the old event if it existed.
if (fetchEvent) {
@@ -701,79 +701,11 @@ TimingSimpleCPU::DcachePort::recvRetry()
//
// TimingSimpleCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- Param<Tick> profile;
-
- Param<bool> do_quiesce;
- Param<bool> do_checkpoint_insts;
- Param<bool> do_statistics_insts;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
- Param<int> clock;
- Param<int> phase;
-
- Param<bool> defer_registration;
- Param<int> width;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
- Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM(progress_interval, "Progress interval"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(profile, ""),
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(width, "cpu width"),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace"),
- INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-
-CREATE_SIM_OBJECT(TimingSimpleCPU)
+TimingSimpleCPU *
+TimingSimpleCPUParams::create()
{
TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@@ -796,12 +728,11 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
- params->process = workload;
+ if (workload.size() != 1)
+ panic("only one workload allowed");
+ params->process = workload[0];
#endif
TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
-
diff --git a/src/cpu/trace/opt_cpu.cc b/src/cpu/trace/opt_cpu.cc
index 996e89f01..467984252 100644
--- a/src/cpu/trace/opt_cpu.cc
+++ b/src/cpu/trace/opt_cpu.cc
@@ -38,8 +38,7 @@
#include "cpu/trace/opt_cpu.hh"
#include "cpu/trace/reader/mem_trace_reader.hh"
-
-#include "sim/builder.hh"
+#include "params/OptCPU.hh"
#include "sim/sim_events.hh"
using namespace std;
@@ -211,31 +210,8 @@ OptCPU::TickEvent::description()
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
-
- SimObjectParam<MemTraceReader *> data_trace;
- Param<int> size;
- Param<int> block_size;
-Param<int> assoc;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
- INIT_PARAM_DFLT(data_trace, "memory trace", NULL),
- INIT_PARAM(size, "cache size"),
- INIT_PARAM(block_size, "block size"),
- INIT_PARAM(assoc,"associativity")
-
-END_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
-CREATE_SIM_OBJECT(OptCPU)
+OptCPU *
+OptCPUParams::create()
{
- return new OptCPU(getInstanceName(),
- data_trace,
- block_size,
- size,
- assoc);
+ return new OptCPU(name, data_trace, block_size, size, assoc);
}
-
-REGISTER_SIM_OBJECT("OptCPU", OptCPU)
diff --git a/src/cpu/trace/reader/ibm_reader.cc b/src/cpu/trace/reader/ibm_reader.cc
index 87e13f307..e300385d6 100644
--- a/src/cpu/trace/reader/ibm_reader.cc
+++ b/src/cpu/trace/reader/ibm_reader.cc
@@ -34,9 +34,9 @@
*/
#include <sstream>
-#include "cpu/trace/reader/ibm_reader.hh"
-#include "sim/builder.hh"
#include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/ibm_reader.hh"
+#include "params/IBMReader.hh"
using namespace std;
@@ -100,23 +100,8 @@ IBMReader::getNextReq(MemReqPtr &req)
return 0;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
-
- Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
- INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
-
-CREATE_SIM_OBJECT(IBMReader)
+IBMReader *
+IBMReaderParams::create()
{
- return new IBMReader(getInstanceName(), filename);
+ return new IBMReader(name, filename);
}
-
-REGISTER_SIM_OBJECT("IBMReader", IBMReader)
diff --git a/src/cpu/trace/reader/itx_reader.cc b/src/cpu/trace/reader/itx_reader.cc
index e4738eed8..f27b82ff1 100644
--- a/src/cpu/trace/reader/itx_reader.cc
+++ b/src/cpu/trace/reader/itx_reader.cc
@@ -34,9 +34,9 @@
*/
#include <sstream>
-#include "cpu/trace/reader/itx_reader.hh"
-#include "sim/builder.hh"
#include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/itx_reader.hh"
+#include "params/ITXReader.hh"
using namespace std;
@@ -186,23 +186,8 @@ ITXReader::getNextReq(MemReqPtr &req)
return 0;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
-
- Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
- INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
-
-CREATE_SIM_OBJECT(ITXReader)
+ITXReader *
+ITXReaderParams::create()
{
- return new ITXReader(getInstanceName(), filename);
+ return new ITXReader(name, filename);
}
-
-REGISTER_SIM_OBJECT("ITXReader", ITXReader)
diff --git a/src/cpu/trace/reader/m5_reader.cc b/src/cpu/trace/reader/m5_reader.cc
index 8efcb022b..4e714a058 100644
--- a/src/cpu/trace/reader/m5_reader.cc
+++ b/src/cpu/trace/reader/m5_reader.cc
@@ -36,7 +36,7 @@
#include "cpu/trace/reader/m5_reader.hh"
#include "mem/trace/m5_format.hh"
#include "mem/mem_cmd.hh"
-#include "sim/builder.hh"
+#include "params/M5Reader.hh"
using namespace std;
@@ -77,23 +77,8 @@ M5Reader::getNextReq(MemReqPtr &req)
return ref.cycle;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
-
- Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
- INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
-
-CREATE_SIM_OBJECT(M5Reader)
+M5Reader *
+M5ReaderParams::create()
{
- return new M5Reader(getInstanceName(), filename);
+ return new M5Reader(name, filename);
}
-
-REGISTER_SIM_OBJECT("M5Reader", M5Reader)
diff --git a/src/cpu/trace/reader/mem_trace_reader.cc b/src/cpu/trace/reader/mem_trace_reader.cc
deleted file mode 100644
index 5623f168a..000000000
--- a/src/cpu/trace/reader/mem_trace_reader.cc
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- */
-
-/**
- * @file
- * SimObject Declaration of pure virtual MemTraceReader class.
- */
-
-#include "cpu/trace/reader/mem_trace_reader.hh"
-#include "sim/param.hh"
-
-DEFINE_SIM_OBJECT_CLASS_NAME("MemTraceReader", MemTraceReader);
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 3c9da4849..a3164221b 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -40,7 +40,7 @@
#include "cpu/trace/reader/mem_trace_reader.hh"
#include "mem/base_mem.hh" // For PARAM constructor
#include "mem/mem_interface.hh"
-#include "sim/builder.hh"
+#include "params/TraceCPU.hh"
#include "sim/sim_events.hh"
using namespace std;
@@ -151,31 +151,11 @@ TraceCPU::TickEvent::description()
return "TraceCPU tick event";
}
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
- SimObjectParam<BaseMem *> icache;
- SimObjectParam<BaseMem *> dcache;
- SimObjectParam<MemTraceReader *> data_trace;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
- INIT_PARAM_DFLT(icache, "instruction cache", NULL),
- INIT_PARAM_DFLT(dcache, "data cache", NULL),
- INIT_PARAM_DFLT(data_trace, "data trace", NULL)
-
-END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
-CREATE_SIM_OBJECT(TraceCPU)
+TraceCPU *
+TraceCPUParams::create()
{
- return new TraceCPU(getInstanceName(),
+ return new TraceCPU(name,
(icache) ? icache->getInterface() : NULL,
(dcache) ? dcache->getInterface() : NULL,
data_trace);
}
-
-REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
-