diff options
Diffstat (limited to 'src/cpu')
73 files changed, 644 insertions, 1157 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6800b4c91..19464acbc 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -43,28 +43,22 @@ default_tracer = ExeTracer() if buildEnv['TARGET_ISA'] == 'alpha': from AlphaTLB import AlphaDTB, AlphaITB - if buildEnv['FULL_SYSTEM']: - from AlphaInterrupts import AlphaInterrupts + from AlphaInterrupts import AlphaInterrupts elif buildEnv['TARGET_ISA'] == 'sparc': from SparcTLB import SparcTLB - if buildEnv['FULL_SYSTEM']: - from SparcInterrupts import SparcInterrupts + from SparcInterrupts import SparcInterrupts elif buildEnv['TARGET_ISA'] == 'x86': from X86TLB import X86TLB - if buildEnv['FULL_SYSTEM']: - from X86LocalApic import X86LocalApic + from X86LocalApic import X86LocalApic elif buildEnv['TARGET_ISA'] == 'mips': from MipsTLB import MipsTLB - if buildEnv['FULL_SYSTEM']: - from MipsInterrupts import MipsInterrupts + from MipsInterrupts import MipsInterrupts elif buildEnv['TARGET_ISA'] == 'arm': from ArmTLB import ArmTLB - if buildEnv['FULL_SYSTEM']: - from ArmInterrupts import ArmInterrupts + from ArmInterrupts import ArmInterrupts elif buildEnv['TARGET_ISA'] == 'power': from PowerTLB import PowerTLB - if buildEnv['FULL_SYSTEM']: - from PowerInterrupts import PowerInterrupts + from PowerInterrupts import PowerInterrupts class BaseCPU(MemObject): type = 'BaseCPU' @@ -84,50 +78,42 @@ class BaseCPU(MemObject): do_statistics_insts = Param.Bool(True, "enable statistics pseudo instructions") - if buildEnv['FULL_SYSTEM']: - profile = Param.Latency('0ns', "trace the kernel stack") - do_quiesce = Param.Bool(True, "enable quiesce instructions") - else: - workload = VectorParam.Process("processes to run") + profile = Param.Latency('0ns', "trace the kernel stack") + do_quiesce = Param.Bool(True, "enable quiesce instructions") + + workload = VectorParam.Process([], "processes to run") if buildEnv['TARGET_ISA'] == 'sparc': dtb = Param.SparcTLB(SparcTLB(), "Data TLB") itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.SparcInterrupts( + interrupts = Param.SparcInterrupts( SparcInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.AlphaInterrupts( + interrupts = Param.AlphaInterrupts( AlphaInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - _localApic = X86LocalApic(pio_addr=0x2000000000000000) - interrupts = \ - Param.X86LocalApic(_localApic, "Interrupt Controller") + _localApic = X86LocalApic(pio_addr=0x2000000000000000) + interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.MipsInterrupts( - MipsInterrupts(), "Interrupt Controller") + interrupts = Param.MipsInterrupts( + MipsInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'arm': dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.ArmInterrupts( - ArmInterrupts(), "Interrupt Controller") + interrupts = Param.ArmInterrupts( + ArmInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.PowerInterrupts( - PowerInterrupts(), "Interrupt Controller") + interrupts = Param.PowerInterrupts( + PowerInterrupts(), "Interrupt Controller") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] @@ -156,11 +142,11 @@ class BaseCPU(MemObject): dcache_port = Port("Data Port") _cached_ports = ['icache_port', 'dcache_port'] - if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: + if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] _uncached_ports = [] - if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: + if buildEnv['TARGET_ISA'] == 'x86': _uncached_ports = ["interrupts.pio", "interrupts.int_port"] def connectCachedPorts(self, bus): @@ -184,17 +170,16 @@ class BaseCPU(MemObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] - if buildEnv['FULL_SYSTEM']: - if buildEnv['TARGET_ISA'] in ['x86', 'arm']: - if iwc and dwc: - self.itb_walker_cache = iwc - self.dtb_walker_cache = dwc - self.itb.walker.port = iwc.cpu_side - self.dtb.walker.port = dwc.cpu_side - self._cached_ports += ["itb_walker_cache.mem_side", \ - "dtb_walker_cache.mem_side"] - else: - self._cached_ports += ["itb.walker.port", "dtb.walker.port"] + if buildEnv['TARGET_ISA'] in ['x86', 'arm']: + if iwc and dwc: + self.itb_walker_cache = iwc + self.dtb_walker_cache = dwc + self.itb.walker.port = iwc.cpu_side + self.dtb.walker.port = dwc.cpu_side + self._cached_ports += ["itb_walker_cache.mem_side", \ + "dtb_walker_cache.mem_side"] + else: + self._cached_ports += ["itb.walker.port", "dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) diff --git a/src/cpu/SConscript b/src/cpu/SConscript index a1074cb8b..ff731336a 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -109,6 +109,7 @@ SimObject('BaseCPU.py') SimObject('FuncUnit.py') SimObject('ExeTracer.py') SimObject('IntelTrace.py') +SimObject('IntrControl.py') SimObject('NativeTrace.py') Source('activity.cc') @@ -118,23 +119,19 @@ Source('decode.cc') Source('exetrace.cc') Source('func_unit.cc') Source('inteltrace.cc') +Source('intr_control.cc') Source('nativetrace.cc') Source('pc_event.cc') +Source('profile.cc') Source('quiesce_event.cc') Source('static_inst.cc') Source('simple_thread.cc') Source('thread_context.cc') Source('thread_state.cc') -if env['FULL_SYSTEM']: - SimObject('IntrControl.py') - - Source('intr_control.cc') - Source('profile.cc') - - if env['TARGET_ISA'] == 'sparc': - SimObject('LegionTrace.py') - Source('legiontrace.cc') +if env['TARGET_ISA'] == 'sparc': + SimObject('LegionTrace.py') + Source('legiontrace.cc') if env['USE_CHECKER']: Source('checker/cpu.cc') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 370be7ee1..d174995a9 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -59,6 +59,7 @@ #include "cpu/thread_context.hh" #include "debug/SyscallVerbose.hh" #include "params/BaseCPU.hh" +#include "sim/full_system.hh" #include "sim/process.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" @@ -112,18 +113,11 @@ CPUProgressEvent::description() const return "CPU Progress"; } -#if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), interrupts(p->interrupts), numThreads(p->numThreads), system(p->system), phase(p->phase) -#else -BaseCPU::BaseCPU(Params *p) - : MemObject(p), clock(p->clock), _cpuId(p->cpu_id), - numThreads(p->numThreads), system(p->system), - phase(p->phase) -#endif { // currentTick = curTick(); @@ -218,13 +212,13 @@ BaseCPU::BaseCPU(Params *p) schedule(event, p->function_trace_start); } } -#if FULL_SYSTEM interrupts->setCPU(this); - profileEvent = NULL; - if (params()->profile) - profileEvent = new ProfileEvent(this, params()->profile); -#endif + if (FullSystem) { + profileEvent = NULL; + if (params()->profile) + profileEvent = new ProfileEvent(this, params()->profile); + } tracer = params()->tracer; } @@ -248,10 +242,10 @@ BaseCPU::init() void BaseCPU::startup() { -#if FULL_SYSTEM - if (!params()->defer_registration && profileEvent) - schedule(profileEvent, curTick()); -#endif + if (FullSystem) { + if (!params()->defer_registration && profileEvent) + schedule(profileEvent, curTick()); + } if (params()->progress_interval) { Tick num_ticks = ticks(params()->progress_interval); @@ -290,9 +284,6 @@ BaseCPU::regStats() } } else if (size == 1) threadContexts[0]->regStats(name()); - -#if FULL_SYSTEM -#endif } Tick @@ -334,9 +325,9 @@ BaseCPU::registerThreadContexts() tc->setContextId(system->registerThreadContext(tc, _cpuId)); else tc->setContextId(system->registerThreadContext(tc)); -#if !FULL_SYSTEM - tc->getProcessPtr()->assignThreadContext(tc->contextId()); -#endif + + if (!FullSystem) + tc->getProcessPtr()->assignThreadContext(tc->contextId()); } } @@ -355,11 +346,8 @@ BaseCPU::findContext(ThreadContext *tc) void BaseCPU::switchOut() { -// panic("This CPU doesn't support sampling!"); -#if FULL_SYSTEM if (profileEvent && profileEvent->scheduled()) deschedule(profileEvent); -#endif } void @@ -410,16 +398,16 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) } } -#if FULL_SYSTEM interrupts = oldCPU->interrupts; interrupts->setCPU(this); - for (ThreadID i = 0; i < size; ++i) - threadContexts[i]->profileClear(); + if (FullSystem) { + for (ThreadID i = 0; i < size; ++i) + threadContexts[i]->profileClear(); - if (profileEvent) - schedule(profileEvent, curTick()); -#endif + if (profileEvent) + schedule(profileEvent, curTick()); + } // Connect new CPU to old CPU's memory only if new CPU isn't // connected to anything. Also connect old CPU's memory to new @@ -438,7 +426,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) } -#if FULL_SYSTEM BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) : cpu(_cpu), interval(_interval) { } @@ -469,8 +456,6 @@ BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) interrupts->unserialize(cp, section); } -#endif // FULL_SYSTEM - void BaseCPU::traceFunctionsInternal(Addr pc) { diff --git a/src/cpu/base.hh b/src/cpu/base.hh index d4de55453..41c79dff6 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -48,19 +48,16 @@ #include <vector> +#include "arch/interrupts.hh" #include "arch/isa_traits.hh" #include "arch/microcode_rom.hh" #include "base/statistics.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "mem/mem_object.hh" #include "sim/eventq.hh" +#include "sim/full_system.hh" #include "sim/insttracer.hh" -#if FULL_SYSTEM -#include "arch/interrupts.hh" -#endif - class BaseCPUParams; class BranchPred; class CheckerCPU; @@ -173,7 +170,6 @@ class BaseCPU : public MemObject TheISA::MicrocodeRom microcodeRom; -#if FULL_SYSTEM protected: TheISA::Interrupts *interrupts; @@ -190,7 +186,8 @@ class BaseCPU : public MemObject postInterrupt(int int_num, int index) { interrupts->post(int_num, index); - wakeup(); + if (FullSystem) + wakeup(); } void @@ -208,7 +205,7 @@ class BaseCPU : public MemObject bool checkInterrupts(ThreadContext *tc) const { - return interrupts->checkInterrupts(tc); + return FullSystem && interrupts->checkInterrupts(tc); } class ProfileEvent : public Event @@ -222,7 +219,6 @@ class BaseCPU : public MemObject void process(); }; ProfileEvent *profileEvent; -#endif protected: std::vector<ThreadContext *> threadContexts; @@ -305,7 +301,6 @@ class BaseCPU : public MemObject Tick phase; -#if FULL_SYSTEM /** * Serialize this object to the given output stream. * @param os The stream to serialize to. @@ -319,8 +314,6 @@ class BaseCPU : public MemObject */ virtual void unserialize(Checkpoint *cp, const std::string §ion); -#endif - /** * Return pointer to CPU's branch predictor (NULL if none). * @return Branch predictor pointer. diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 5719fc84d..9089d1069 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -53,7 +53,6 @@ #include "arch/utility.hh" #include "base/fast_alloc.hh" #include "base/trace.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/o3/comm.hh" #include "cpu/exetrace.hh" diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 0c7fe66bf..ec4496eb4 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -31,17 +31,14 @@ #include <list> #include <string> +#include "arch/kernel_stats.hh" +#include "arch/vtophys.hh" #include "cpu/checker/cpu.hh" #include "cpu/base.hh" #include "cpu/simple_thread.hh" #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" -#if FULL_SYSTEM -#include "arch/kernel_stats.hh" -#include "arch/vtophys.hh" -#endif // FULL_SYSTEM - using namespace std; //The CheckerCPU does alpha only using namespace AlphaISA; @@ -66,17 +63,14 @@ CheckerCPU::CheckerCPU(Params *p) exitOnError = p->exitOnError; warnOnlyOnLoadError = p->warnOnlyOnLoadError; -#if FULL_SYSTEM itb = p->itb; dtb = p->dtb; systemPtr = NULL; -#else process = p->process; thread = new SimpleThread(this, /* thread_num */ 0, process); tc = thread->getTC(); threadContexts.push_back(tc); -#endif result.integer = 0; } @@ -88,7 +82,6 @@ CheckerCPU::~CheckerCPU() void CheckerCPU::setSystem(System *system) { -#if FULL_SYSTEM systemPtr = system; thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false); @@ -97,7 +90,6 @@ CheckerCPU::setSystem(System *system) threadContexts.push_back(tc); delete thread->kernelStats; thread->kernelStats = NULL; -#endif } void @@ -301,13 +293,11 @@ CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) } -#if FULL_SYSTEM Addr CheckerCPU::dbg_vtophys(Addr addr) { return vtophys(tc, addr); } -#endif // FULL_SYSTEM bool CheckerCPU::checkFlags(Request *req) diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 1e3a17a34..a3e95137d 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -37,7 +37,6 @@ #include "arch/types.hh" #include "base/statistics.hh" -#include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/base_dyn_inst.hh" #include "cpu/pc_event.hh" @@ -46,25 +45,20 @@ #include "sim/eventq.hh" // forward declarations -#if FULL_SYSTEM namespace TheISA { class TLB; } -class Processor; -class PhysicalMemory; - -#else -class Process; - -#endif // FULL_SYSTEM template <class> class BaseDynInst; class CheckerCPUParams; -class ThreadContext; -class MemInterface; class Checkpoint; +class MemInterface; +class PhysicalMemory; +class Process; +class Processor; +class ThreadContext; class Request; /** @@ -129,9 +123,7 @@ class CheckerCPU : public BaseCPU TheISA::TLB *itb; TheISA::TLB *dtb; -#if FULL_SYSTEM Addr dbg_vtophys(Addr addr); -#endif union Result { uint64_t integer; @@ -273,14 +265,11 @@ class CheckerCPU : public BaseCPU this->dtb->demapPage(vaddr, asn); } -#if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } -#else // Assume that the normal CPU's call to syscall was successful. // The checker's state would have already been updated by the syscall. void syscall(uint64_t callnum) { } -#endif void handleError() { diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 8694dae21..7d8cc8a19 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -31,6 +31,7 @@ #include <list> #include <string> +#include "arch/vtophys.hh" #include "base/refcnt.hh" #include "config/the_isa.hh" #include "cpu/checker/cpu.hh" @@ -38,13 +39,10 @@ #include "cpu/simple_thread.hh" #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" +#include "sim/full_system.hh" #include "sim/sim_object.hh" #include "sim/stats.hh" -#if FULL_SYSTEM -#include "arch/vtophys.hh" -#endif // FULL_SYSTEM - using namespace std; //The CheckerCPU does alpha only using namespace AlphaISA; @@ -141,11 +139,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst) // Try to fetch the instruction -#if FULL_SYSTEM -#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 -#else -#define IFETCH_FLAGS(pc) 0 -#endif +#define IFETCH_FLAGS(pc) (FullSystem ? 0 : ((pc) & 1) ? PHYSICAL : 0) uint64_t fetch_PC = thread->readPC() & ~3; @@ -235,12 +229,10 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst) } if (fault != NoFault) { -#if FULL_SYSTEM fault->invoke(tc, curStaticInst); willChangePC = true; newPC = thread->readPC(); DPRINTF(Checker, "Fault, PC is now %#x\n", newPC); -#endif } else { #if THE_ISA != MIPS_ISA // go to the next instruction @@ -255,23 +247,23 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst) } -#if FULL_SYSTEM - // @todo: Determine if these should happen only if the - // instruction hasn't faulted. In the SimpleCPU case this may - // not be true, but in the O3 or Ozone case this may be true. - Addr oldpc; - int count = 0; - do { - oldpc = thread->readPC(); - system->pcEventQueue.service(tc); - count++; - } while (oldpc != thread->readPC()); - if (count > 1) { - willChangePC = true; - newPC = thread->readPC(); - DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC); + if (FullSystem) { + // @todo: Determine if these should happen only if the + // instruction hasn't faulted. In the SimpleCPU case this may + // not be true, but in the O3 or Ozone case this may be true. + Addr oldpc; + int count = 0; + do { + oldpc = thread->readPC(); + system->pcEventQueue.service(tc); + count++; + } while (oldpc != thread->readPC()); + if (count > 1) { + willChangePC = true; + newPC = thread->readPC(); + DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC); + } } -#endif // @todo: Optionally can check all registers. (Or just those // that have been modified). diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 4eb3eabfd..178ded80e 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -89,7 +89,6 @@ class CheckerThreadContext : public ThreadContext TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } -#if FULL_SYSTEM System *getSystemPtr() { return actualTC->getSystemPtr(); } PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } @@ -97,15 +96,14 @@ class CheckerThreadContext : public ThreadContext TheISA::Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } + Process *getProcessPtr() { return actualTC->getProcessPtr(); } + PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); } -#else - SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } - Process *getProcessPtr() { return actualTC->getProcessPtr(); } -#endif + SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } Status status() const { return actualTC->status(); } @@ -125,9 +123,7 @@ class CheckerThreadContext : public ThreadContext /// Set the status to Halted. void halt() { actualTC->halt(); } -#if FULL_SYSTEM void dumpFuncProfile() { actualTC->dumpFuncProfile(); } -#endif void takeOverFrom(ThreadContext *oldContext) { @@ -141,7 +137,6 @@ class CheckerThreadContext : public ThreadContext void unserialize(Checkpoint *cp, const std::string §ion) { actualTC->unserialize(cp, section); } -#if FULL_SYSTEM EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } Tick readLastActivate() { return actualTC->readLastActivate(); } @@ -149,7 +144,6 @@ class CheckerThreadContext : public ThreadContext void profileClear() { return actualTC->profileClear(); } void profileSample() { return actualTC->profileSample(); } -#endif int threadId() { return actualTC->threadId(); } @@ -253,9 +247,7 @@ class CheckerThreadContext : public ThreadContext // @todo: Fix this! bool misspeculating() { return actualTC->misspeculating(); } -#if !FULL_SYSTEM Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } -#endif }; #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 61c9b24a9..2f4d26976 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -111,7 +111,6 @@ class ExecContext { Fault writeMem(uint8_t *data, unsigned size, Addr addr, unsigned flags, uint64_t *res); -#if FULL_SYSTEM /** Somewhat Alpha-specific function that handles returning from * an error or interrupt. */ Fault hwrei(); @@ -121,10 +120,9 @@ class ExecContext { * return value is false, actual PAL call will be suppressed. */ bool simPalCheck(int palFunc); -#else + /** Executes a syscall specified by the callnum. */ void syscall(int64_t callnum); -#endif /** Finish a DTB address translation. */ void finishTranslation(WholeTranslationState *state); diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 40991652d..0b21a1270 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -83,10 +83,7 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran) std::string sym_str; Addr sym_addr; Addr cur_pc = pc.instAddr(); - if (debugSymbolTable && Debug::ExecSymbol -#if FULL_SYSTEM - && !inUserMode(thread) -#endif + if (debugSymbolTable && Debug::ExecSymbol && !inUserMode(thread) && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) { if (cur_pc != sym_addr) sym_str += csprintf("+%d",cur_pc - sym_addr); diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 9614a5df2..5a14e92a7 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -33,7 +33,6 @@ #include "arch/utility.hh" #include "base/bigint.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/inorder/resources/resource_list.hh" #include "cpu/inorder/cpu.hh" @@ -46,21 +45,20 @@ #include "cpu/activity.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" +#include "cpu/quiesce_event.hh" #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "debug/Activity.hh" #include "debug/InOrderCPU.hh" +#include "debug/Interrupt.hh" #include "debug/RefCount.hh" #include "debug/SkedCache.hh" #include "debug/Quiesce.hh" #include "params/InOrderCPU.hh" +#include "sim/full_system.hh" #include "sim/process.hh" #include "sim/stat_control.hh" - -#if FULL_SYSTEM -#include "cpu/quiesce_event.hh" #include "sim/system.hh" -#endif #if THE_ISA == ALPHA_ISA #include "arch/alpha/osfpal.hh" @@ -152,12 +150,11 @@ InOrderCPU::CPUEvent::process() cpu->trapPending[tid] = false; break; -#if !FULL_SYSTEM case Syscall: cpu->syscall(inst->syscallNum, tid); cpu->resPool->trap(fault, tid, inst); break; -#endif + default: fatal("Unrecognized Event Type %s", eventNames[cpuEventType]); } @@ -197,9 +194,7 @@ InOrderCPU::InOrderCPU(Params *params) timeBuffer(2 , 2), removeInstsThisCycle(false), activityRec(params->name, NumStages, 10, params->activity), -#if FULL_SYSTEM system(params->system), -#endif // FULL_SYSTEM #ifdef DEBUG cpuEventNum(0), resReqCount(0), @@ -217,33 +212,33 @@ InOrderCPU::InOrderCPU(Params *params) // Resize for Multithreading CPUs thread.resize(numThreads); -#if !FULL_SYSTEM ThreadID active_threads = params->workload.size(); + if (FullSystem) { + active_threads = 1; + } else { + active_threads = params->workload.size(); - if (active_threads > MaxThreads) { - panic("Workload Size too large. Increase the 'MaxThreads'" - "in your InOrder implementation or " - "edit your workload size."); - } + if (active_threads > MaxThreads) { + panic("Workload Size too large. Increase the 'MaxThreads'" + "in your InOrder implementation or " + "edit your workload size."); + } - - if (active_threads > 1) { - threadModel = (InOrderCPU::ThreadModel) params->threadModel; - - if (threadModel == SMT) { - DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n"); - } else if (threadModel == SwitchOnCacheMiss) { - DPRINTF(InOrderCPU, "Setting Thread Model to " - "Switch On Cache Miss\n"); + + if (active_threads > 1) { + threadModel = (InOrderCPU::ThreadModel) params->threadModel; + + if (threadModel == SMT) { + DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n"); + } else if (threadModel == SwitchOnCacheMiss) { + DPRINTF(InOrderCPU, "Setting Thread Model to " + "Switch On Cache Miss\n"); + } + + } else { + threadModel = Single; } - - } else { - threadModel = Single; } - - - -#endif // Bind the fetch & data ports from the resource pool. fetchPortIdx = resPool->getPortIdx(params->fetchMemPort); @@ -260,36 +255,34 @@ InOrderCPU::InOrderCPU(Params *params) pc[tid].set(0); lastCommittedPC[tid].set(0); -#if FULL_SYSTEM - // SMT is not supported in FS mode yet. - assert(numThreads == 1); - thread[tid] = new Thread(this, 0); -#else - if (tid < (ThreadID)params->workload.size()) { - DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n", - tid, params->workload[tid]->prog_fname); - thread[tid] = - new Thread(this, tid, params->workload[tid]); + if (FullSystem) { + // SMT is not supported in FS mode yet. + assert(numThreads == 1); + thread[tid] = new Thread(this, 0, NULL); } else { - //Allocate Empty thread so M5 can use later - //when scheduling threads to CPU - Process* dummy_proc = params->workload[0]; - thread[tid] = new Thread(this, tid, dummy_proc); + if (tid < (ThreadID)params->workload.size()) { + DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n", + tid, params->workload[tid]->prog_fname); + thread[tid] = + new Thread(this, tid, params->workload[tid]); + } else { + //Allocate Empty thread so M5 can use later + //when scheduling threads to CPU + Process* dummy_proc = params->workload[0]; + thread[tid] = new Thread(this, tid, dummy_proc); + } + + // Eventually set this with parameters... + asid[tid] = tid; } - - // Eventually set this with parameters... - asid[tid] = tid; -#endif // Setup the TC that will serve as the interface to the threads/CPU. InOrderThreadContext *tc = new InOrderThreadContext; tc->cpu = this; tc->thread = thread[tid]; -#if FULL_SYSTEM // Setup quiesce event. this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); -#endif // Give the thread the TC. thread[tid]->tc = tc; @@ -348,16 +341,17 @@ InOrderCPU::InOrderCPU(Params *params) dummyReq[tid] = new ResourceRequest(resPool->getResource(0)); -#if FULL_SYSTEM - // Use this dummy inst to force squashing behind every instruction - // in pipeline - dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0); - dummyTrapInst[tid]->seqNum = 0; - dummyTrapInst[tid]->squashSeqNum = 0; - dummyTrapInst[tid]->setTid(tid); -#endif - trapPending[tid] = false; + if (FullSystem) { + // Use this dummy inst to force squashing behind every instruction + // in pipeline + dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0); + dummyTrapInst[tid]->seqNum = 0; + dummyTrapInst[tid]->squashSeqNum = 0; + dummyTrapInst[tid]->setTid(tid); + } + + trapPending[tid] = false; } @@ -698,9 +692,7 @@ InOrderCPU::tick() ++numCycles; -#if FULL_SYSTEM checkForInterrupts(); -#endif bool pipes_idle = true; //Tick each of the stages @@ -761,14 +753,14 @@ InOrderCPU::init() for (ThreadID tid = 0; tid < numThreads; ++tid) thread[tid]->inSyscall = true; -#if FULL_SYSTEM - for (ThreadID tid = 0; tid < numThreads; tid++) { - ThreadContext *src_tc = threadContexts[tid]; - TheISA::initCPU(src_tc, src_tc->contextId()); - // Initialise the ThreadContext's memory proxies - thread[tid]->initMemProxies(thread[tid]->getTC()); + if (FullSystem) { + for (ThreadID tid = 0; tid < numThreads; tid++) { + ThreadContext *src_tc = threadContexts[tid]; + TheISA::initCPU(src_tc, src_tc->contextId()); + // Initialise the ThreadContext's memory proxies + thread[tid]->initMemProxies(thread[tid]->getTC()); + } } -#endif // Clear inSyscall. for (ThreadID tid = 0; tid < numThreads; ++tid) @@ -784,7 +776,6 @@ InOrderCPU::getPort(const std::string &if_name, int idx) return resPool->getPort(if_name, idx); } -#if FULL_SYSTEM Fault InOrderCPU::hwrei(ThreadID tid) { @@ -870,7 +861,6 @@ InOrderCPU::getInterrupts() return interrupts->getInterrupt(threadContexts[0]); } - void InOrderCPU::processInterrupts(Fault interrupt) { @@ -889,8 +879,6 @@ InOrderCPU::processInterrupts(Fault interrupt) trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst); } -#endif - void InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay) { @@ -1681,7 +1669,6 @@ InOrderCPU::wakeCPU() schedule(&tickEvent, nextCycle(curTick())); } -#if FULL_SYSTEM // Lots of copied full system code...place into BaseCPU class? void InOrderCPU::wakeup() @@ -1694,9 +1681,7 @@ InOrderCPU::wakeup() DPRINTF(Quiesce, "Suspended Processor woken\n"); threadContexts[0]->activate(); } -#endif -#if !FULL_SYSTEM void InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay) { @@ -1734,7 +1719,6 @@ InOrderCPU::syscall(int64_t callnum, ThreadID tid) // Clear Non-Speculative Block Variable nonSpecInstActive[tid] = false; } -#endif TheISA::TLB* InOrderCPU::getITBPtr() diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 1559874cd..7d22bc902 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -43,7 +43,6 @@ #include "arch/types.hh" #include "base/statistics.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/pipeline_stage.hh" @@ -413,7 +412,6 @@ class InOrderCPU : public BaseCPU /** Get a Memory Port */ Port* getPort(const std::string &if_name, int idx = 0); -#if FULL_SYSTEM /** HW return from error interrupt. */ Fault hwrei(ThreadID tid); @@ -435,14 +433,13 @@ class InOrderCPU : public BaseCPU /** Check if this address is a valid data address. */ bool validDataAddr(Addr addr) { return true; } -#else + /** Schedule a syscall on the CPU */ void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0); /** Executes a syscall.*/ void syscall(int64_t callnum, ThreadID tid); -#endif /** Schedule a trap on the CPU */ void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0); @@ -749,9 +746,7 @@ class InOrderCPU : public BaseCPU /** Wakes the CPU, rescheduling the CPU if it's not already active. */ void wakeCPU(); -#if FULL_SYSTEM virtual void wakeup(); -#endif /* LL/SC debug functionality unsigned stCondFails; @@ -780,10 +775,8 @@ class InOrderCPU : public BaseCPU return total; } -#if FULL_SYSTEM /** Pointer to the system. */ System *system; -#endif /** The global sequence number counter. */ InstSeqNum globalSeqNum[ThePipeline::MaxThreads]; diff --git a/src/cpu/inorder/inorder_cpu_builder.cc b/src/cpu/inorder/inorder_cpu_builder.cc index 99729577e..bde5b1e94 100644 --- a/src/cpu/inorder/inorder_cpu_builder.cc +++ b/src/cpu/inorder/inorder_cpu_builder.cc @@ -38,21 +38,23 @@ #include "cpu/inst_seq.hh" #include "cpu/static_inst.hh" #include "params/InOrderCPU.hh" +#include "sim/full_system.hh" InOrderCPU * InOrderCPUParams::create() { -#if FULL_SYSTEM - // Full-system only supports a single thread for the moment. - ThreadID actual_num_threads = 1; -#else - ThreadID actual_num_threads = - (numThreads >= workload.size()) ? numThreads : workload.size(); + ThreadID actual_num_threads; + if (FullSystem) { + // Full-system only supports a single thread for the moment. + actual_num_threads = 1; + } else { + actual_num_threads = + (numThreads >= workload.size()) ? numThreads : workload.size(); - if (workload.size() == 0) { - fatal("Must specify at least one workload!"); + if (workload.size() == 0) { + fatal("Must specify at least one workload!"); + } } -#endif numThreads = actual_num_threads; diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index ff178f6d3..043b21134 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -45,6 +45,7 @@ #include "cpu/exetrace.hh" #include "debug/InOrderDynInst.hh" #include "mem/request.hh" +#include "sim/full_system.hh" using namespace std; using namespace TheISA; @@ -269,8 +270,6 @@ InOrderDynInst::memAccess() } -#if FULL_SYSTEM - Fault InOrderDynInst::hwrei() { @@ -311,17 +310,16 @@ InOrderDynInst::simPalCheck(int palFunc) #endif return this->cpu->simPalCheck(palFunc, this->threadNumber); } -#endif void InOrderDynInst::syscall(int64_t callnum) { -#if FULL_SYSTEM - panic("Syscall emulation isn't available in FS mode.\n"); -#else - syscallNum = callnum; - cpu->syscallContext(NoFault, this->threadNumber, this); -#endif + if (FullSystem) { + panic("Syscall emulation isn't available in FS mode.\n"); + } else { + syscallNum = callnum; + cpu->syscallContext(NoFault, this->threadNumber, this); + } } void diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index f49476ec5..b49dd7594 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -45,7 +45,6 @@ #include "base/fast_alloc.hh" #include "base/trace.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/inorder/inorder_trace.hh" #include "cpu/inorder/pipeline_traits.hh" @@ -517,15 +516,12 @@ class InOrderDynInst : public FastAlloc, public RefCounted void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; } /** Calls a syscall. */ -#if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); /** Traps to handle specified fault. */ void trap(Fault fault); bool simPalCheck(int palFunc); -#else short syscallNum; -#endif /** Emulates a syscall. */ void syscall(int64_t callnum); diff --git a/src/cpu/inorder/params.hh b/src/cpu/inorder/params.hh index 51b7409ad..44f2a5018 100644 --- a/src/cpu/inorder/params.hh +++ b/src/cpu/inorder/params.hh @@ -50,10 +50,8 @@ class InOrderParams : public BaseCPU::Params public: // Workloads -#if !FULL_SYSTEM std::vector<Process *> workload; Process *process; -#endif // FULL_SYSTEM // // Memory System/Caches diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 856675e05..0ab9f0579 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -430,13 +430,11 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, } } -#if !FULL_SYSTEM void CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst) { tlbBlocked[tid] = false; } -#endif Fault CacheUnit::read(DynInstPtr inst, Addr addr, diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 6ca300163..2155c920c 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -149,9 +149,8 @@ class CacheUnit : public Resource bool processSquash(CacheReqPacket *cache_pkt); -#if !FULL_SYSTEM void trap(Fault fault, ThreadID tid, DynInstPtr inst); -#endif + void recvRetry(); /** Returns a specific port. */ diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc index a0a486269..16f737308 100644 --- a/src/cpu/inorder/resources/execution_unit.cc +++ b/src/cpu/inorder/resources/execution_unit.cc @@ -38,6 +38,7 @@ #include "debug/Fault.hh" #include "debug/InOrderExecute.hh" #include "debug/InOrderStall.hh" +#include "sim/full_system.hh" using namespace std; using namespace ThePipeline; @@ -219,14 +220,14 @@ ExecutionUnit::execute(int slot_num) seq_num, didx, inst->readIntResult(didx)); #endif -#if !FULL_SYSTEM - // The Syscall might change the PC, so conservatively - // squash everything behing it - if (inst->isSyscall()) { - inst->setSquashInfo(stage_num); - setupSquash(inst, stage_num, tid); + if (!FullSystem) { + // The Syscall might change the PC, so conservatively + // squash everything behing it + if (inst->isSyscall()) { + inst->setSquashInfo(stage_num); + setupSquash(inst, stage_num, tid); + } } -#endif } else { DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s " "fault.\n", inst->readTid(), seq_num, fault->name()); diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc index 82e681f04..acfcf0939 100644 --- a/src/cpu/inorder/thread_context.cc +++ b/src/cpu/inorder/thread_context.cc @@ -34,18 +34,16 @@ #include "cpu/inorder/thread_context.hh" #include "cpu/exetrace.hh" #include "debug/InOrderCPU.hh" +#include "sim/full_system.hh" using namespace TheISA; -#if FULL_SYSTEM - FSTranslatingPortProxy* InOrderThreadContext::getVirtProxy() { return thread->getVirtProxy(); } - void InOrderThreadContext::dumpFuncProfile() { @@ -79,26 +77,19 @@ InOrderThreadContext::profileSample() { thread->profileSample(); } -#endif void InOrderThreadContext::takeOverFrom(ThreadContext *old_context) { // some things should already be set up assert(getSystemPtr() == old_context->getSystemPtr()); -#if !FULL_SYSTEM assert(getProcessPtr() == old_context->getProcessPtr()); -#endif - - // copy over functional state setStatus(old_context->status()); copyArchRegs(old_context); -#if !FULL_SYSTEM thread->funcExeInst = old_context->readFuncExeInst(); -#endif old_context->setStatus(ThreadContext::Halted); @@ -151,11 +142,10 @@ InOrderThreadContext::halt(int delay) void InOrderThreadContext::regStats(const std::string &name) { -#if FULL_SYSTEM - thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); - thread->kernelStats->regStats(name + ".kern"); -#endif - ; + if (FullSystem) { + thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); + thread->kernelStats->regStats(name + ".kern"); + } } diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 5b67d7e8b..7fe0fb5ef 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -109,7 +109,6 @@ class InOrderThreadContext : public ThreadContext void setNextMicroPC(uint64_t val) { }; -#if FULL_SYSTEM /** Returns a pointer to physical memory. */ PhysicalMemory *getPhysMemPtr() { assert(0); return 0; /*return cpu->physmem;*/ } @@ -146,12 +145,11 @@ class InOrderThreadContext : public ThreadContext { return this->thread->quiesceEvent; } -#else + SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); } /** Returns a pointer to this thread's process. */ Process *getProcessPtr() { return thread->getProcessPtr(); } -#endif /** Returns this thread's status. */ Status status() const { return thread->status(); } @@ -273,11 +271,9 @@ class InOrderThreadContext : public ThreadContext * misspeculating, this is set as false. */ bool misspeculating() { return false; } -#if !FULL_SYSTEM /** Executes a syscall in SE mode. */ void syscall(int64_t callnum) { return cpu->syscall(callnum, thread->threadId()); } -#endif /** Reads the funcExeInst counter. */ Counter readFuncExeInst() { return thread->funcExeInst; } diff --git a/src/cpu/inorder/thread_state.cc b/src/cpu/inorder/thread_state.cc index b17f05c7d..040e29283 100644 --- a/src/cpu/inorder/thread_state.cc +++ b/src/cpu/inorder/thread_state.cc @@ -36,12 +36,9 @@ using namespace TheISA; -#if FULL_SYSTEM void InOrderThreadState::dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); profile->dump(tc, *os); } -#endif - diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh index 227097569..1ffc59f65 100644 --- a/src/cpu/inorder/thread_state.hh +++ b/src/cpu/inorder/thread_state.hh @@ -39,17 +39,13 @@ #include "cpu/thread_state.hh" #include "sim/sim_exit.hh" -class Event; -class InOrderCPU; - -#if FULL_SYSTEM class EndQuiesceEvent; -class FunctionProfile; -class ProfileNode; -#else +class Event; class FunctionalMemory; +class FunctionProfile; +class InOrderCPU; class Process; -#endif +class ProfileNode; /** * Class that has various thread state, such as the status, the @@ -76,28 +72,17 @@ class InOrderThreadState : public ThreadState { */ bool trapPending; -#if FULL_SYSTEM - InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num) - : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num), - cpu(_cpu), inSyscall(0), trapPending(0), lastGradIsBranch(false) - { } -#else InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num, Process *_process) : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num, _process), cpu(_cpu), inSyscall(0), trapPending(0), lastGradIsBranch(false) { } -#endif -#if !FULL_SYSTEM /** Handles the syscall. */ void syscall(int64_t callnum) { process->syscall(callnum, tc); } -#endif -#if FULL_SYSTEM void dumpFuncProfile(); -#endif /** Pointer to the ThreadContext of this thread. */ ThreadContext *tc; diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc index aa8e99fd1..75d30c894 100644 --- a/src/cpu/legiontrace.cc +++ b/src/cpu/legiontrace.cc @@ -36,11 +36,6 @@ #error Legion tracing only works with SPARC simulations! #endif -#include "config/full_system.hh" -#if !FULL_SYSTEM - #error Legion tracing only works in full system! -#endif - #include <sys/ipc.h> #include <sys/shm.h> @@ -50,28 +45,24 @@ #include "arch/sparc/predecoder.hh" #include "arch/sparc/registers.hh" #include "arch/sparc/utility.hh" +#include "arch/tlb.hh" #include "base/socket.hh" #include "cpu/base.hh" #include "cpu/decode.hh" #include "cpu/legiontrace.hh" #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" +#include "sim/full_system.hh" #include "sim/system.hh" -#if FULL_SYSTEM -#include "arch/tlb.hh" -#endif - //XXX This is temporary #include "cpu/m5legion_interface.h" using namespace std; using namespace TheISA; -#if FULL_SYSTEM static int diffcount = 0; static bool wasMicro = false; -#endif namespace Trace { SharedData *shared_data = NULL; @@ -597,5 +588,7 @@ Trace::LegionTraceRecord::dump() Trace::LegionTrace * LegionTraceParams::create() { + if (!FullSystem) + panic("Legion tracing only works in full system!"); return new Trace::LegionTrace(this); }; diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 9dfcc8b9e..ffc817e81 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -40,15 +40,11 @@ class DerivO3CPU(BaseCPU): activity = Param.Unsigned(0, "Initial count") if buildEnv['USE_CHECKER']: - if not buildEnv['FULL_SYSTEM']: - checker = Param.BaseCPU(O3Checker(workload=Parent.workload, - exitOnError=False, - updateOnError=True, - warnOnlyOnLoadError=False), - "checker") - else: - checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, - warnOnlyOnLoadError=False), "checker") + checker = Param.BaseCPU(O3Checker(workload=Parent.workload, + exitOnError=False, + updateOnError=True, + warnOnlyOnLoadError=False), + "checker") checker.itb = Parent.itb checker.dtb = Parent.dtb diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 5d0bd2ed2..b34613f68 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -90,11 +90,8 @@ O3CheckerParams::create() params->dtb = dtb; params->system = system; params->cpu_id = cpu_id; -#if FULL_SYSTEM params->profile = profile; -#else params->process = workload; -#endif O3Checker *cpu = new O3Checker(params); return cpu; diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index ffc2c16d2..b45d37df9 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -267,13 +267,11 @@ class DefaultCommit void squashAfter(ThreadID tid, DynInstPtr &head_inst, uint64_t squash_after_seq_num); -#if FULL_SYSTEM /** Handles processing an interrupt. */ void handleInterrupt(); /** Get fetch redirecting so we can handle an interrupt */ void propagateInterrupt(); -#endif // FULL_SYSTEM /** Commits as many instructions as possible. */ void commitInsts(); diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 9ff31a622..b6a4c0387 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -47,7 +47,6 @@ #include "arch/utility.hh" #include "base/loader/symtab.hh" #include "base/cp_annotate.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "config/use_checker.hh" #include "cpu/o3/commit.hh" @@ -62,6 +61,7 @@ #include "debug/O3PipeView.hh" #include "params/DerivO3CPU.hh" #include "sim/faults.hh" +#include "sim/full_system.hh" #if USE_CHECKER #include "cpu/checker/cpu.hh" @@ -149,9 +149,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) pc[tid].set(0); lastCommitedSeqNum[tid] = 0; } -#if FULL_SYSTEM interrupt = NoFault; -#endif } template <class Impl> @@ -701,7 +699,6 @@ DefaultCommit<Impl>::tick() updateStatus(); } -#if FULL_SYSTEM template <class Impl> void DefaultCommit<Impl>::handleInterrupt() @@ -767,22 +764,20 @@ DefaultCommit<Impl>::propagateInterrupt() toIEW->commitInfo[0].interruptPending = true; } -#endif // FULL_SYSTEM - template <class Impl> void DefaultCommit<Impl>::commit() { - -#if FULL_SYSTEM - // Check for any interrupt that we've already squashed for and start processing it. - if (interrupt != NoFault) - handleInterrupt(); - - // Check if we have a interrupt and get read to handle it - if (cpu->checkInterrupts(cpu->tcBase(0))) - propagateInterrupt(); -#endif // FULL_SYSTEM + if (FullSystem) { + // Check for any interrupt that we've already squashed for and start + // processing it. + if (interrupt != NoFault) + handleInterrupt(); + + // Check if we have a interrupt and get read to handle it + if (cpu->checkInterrupts(cpu->tcBase(0))) + propagateInterrupt(); + } //////////////////////////////////// // Check for any possible squashes, handle them first @@ -1176,22 +1171,22 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) updateComInstStats(head_inst); -#if FULL_SYSTEM - if (thread[tid]->profile) { - thread[tid]->profilePC = head_inst->instAddr(); - ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), - head_inst->staticInst); + if (FullSystem) { + if (thread[tid]->profile) { + thread[tid]->profilePC = head_inst->instAddr(); + ProfileNode *node = thread[tid]->profile->consume( + thread[tid]->getTC(), head_inst->staticInst); - if (node) - thread[tid]->profileNode = node; - } - if (CPA::available()) { - if (head_inst->isControl()) { - ThreadContext *tc = thread[tid]->getTC(); - CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); + if (node) + thread[tid]->profileNode = node; + } + if (CPA::available()) { + if (head_inst->isControl()) { + ThreadContext *tc = thread[tid]->getTC(); + CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); + } } } -#endif DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n", head_inst->seqNum, head_inst->pcState()); if (head_inst->traceData) { diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 7e0b4cee7..ef08c96f4 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -43,13 +43,14 @@ * Rick Strong */ -#include "config/full_system.hh" +#include "arch/kernel_stats.hh" #include "config/the_isa.hh" #include "config/use_checker.hh" #include "cpu/o3/cpu.hh" #include "cpu/o3/isa_specific.hh" #include "cpu/o3/thread_context.hh" #include "cpu/activity.hh" +#include "cpu/quiesce_event.hh" #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "debug/Activity.hh" @@ -57,15 +58,11 @@ #include "debug/Quiesce.hh" #include "enums/MemoryMode.hh" #include "sim/core.hh" +#include "sim/full_system.hh" +#include "sim/process.hh" #include "sim/stat_control.hh" #include "sim/system.hh" -#if FULL_SYSTEM -#include "cpu/quiesce_event.hh" -#else -#include "sim/process.hh" -#endif - #if USE_CHECKER #include "cpu/checker/cpu.hh" #endif @@ -270,18 +267,16 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) BaseCPU *temp_checker = params->checker; checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); checker->setIcachePort(&icachePort); -#if FULL_SYSTEM checker->setSystem(params->system); -#endif } else { checker = NULL; } #endif // USE_CHECKER -#if !FULL_SYSTEM - thread.resize(numThreads); - tids.resize(numThreads); -#endif + if (!FullSystem) { + thread.resize(numThreads); + tids.resize(numThreads); + } // The stages also need their CPU pointer setup. However this // must be done at the upper level CPU because they have pointers @@ -317,17 +312,18 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) rename.setIEWStage(&iew); rename.setCommitStage(&commit); -#if !FULL_SYSTEM - ThreadID active_threads = params->workload.size(); + ThreadID active_threads; + if (FullSystem) { + active_threads = 1; + } else { + active_threads = params->workload.size(); - if (active_threads > Impl::MaxThreads) { - panic("Workload Size too large. Increase the 'MaxThreads'" - "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " - "edit your workload size."); + if (active_threads > Impl::MaxThreads) { + panic("Workload Size too large. Increase the 'MaxThreads' " + "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " + "or edit your workload size."); + } } -#else - ThreadID active_threads = 1; -#endif //Make Sure That this a Valid Architeture assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); @@ -406,31 +402,31 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) this->thread.resize(this->numThreads); for (ThreadID tid = 0; tid < this->numThreads; ++tid) { -#if FULL_SYSTEM - // SMT is not supported in FS mode yet. - assert(this->numThreads == 1); - this->thread[tid] = new Thread(this, 0); -#else - if (tid < params->workload.size()) { - DPRINTF(O3CPU, "Workload[%i] process is %#x", - tid, this->thread[tid]); - this->thread[tid] = new typename FullO3CPU<Impl>::Thread( - (typename Impl::O3CPU *)(this), - tid, params->workload[tid]); - - //usedTids[tid] = true; - //threadMap[tid] = tid; + if (FullSystem) { + // SMT is not supported in FS mode yet. + assert(this->numThreads == 1); + this->thread[tid] = new Thread(this, 0, NULL); } else { - //Allocate Empty thread so M5 can use later - //when scheduling threads to CPU - Process* dummy_proc = NULL; - - this->thread[tid] = new typename FullO3CPU<Impl>::Thread( - (typename Impl::O3CPU *)(this), - tid, dummy_proc); - //usedTids[tid] = false; + if (tid < params->workload.size()) { + DPRINTF(O3CPU, "Workload[%i] process is %#x", + tid, this->thread[tid]); + this->thread[tid] = new typename FullO3CPU<Impl>::Thread( + (typename Impl::O3CPU *)(this), + tid, params->workload[tid]); + + //usedTids[tid] = true; + //threadMap[tid] = tid; + } else { + //Allocate Empty thread so M5 can use later + //when scheduling threads to CPU + Process* dummy_proc = NULL; + + this->thread[tid] = new typename FullO3CPU<Impl>::Thread( + (typename Impl::O3CPU *)(this), + tid, dummy_proc); + //usedTids[tid] = false; + } } -#endif // !FULL_SYSTEM ThreadContext *tc; @@ -452,10 +448,10 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) assert(o3_tc->cpu); o3_tc->thread = this->thread[tid]; -#if FULL_SYSTEM - // Setup quiesce event. - this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); -#endif + if (FullSystem) { + // Setup quiesce event. + this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); + } // Give the thread the TC. this->thread[tid]->tc = tc; @@ -608,9 +604,8 @@ FullO3CPU<Impl>::tick() commit.tick(); -#if !FULL_SYSTEM - doContextSwitch(); -#endif + if (!FullSystem) + doContextSwitch(); // Now advance the time buffers timeBuffer.advance(); @@ -642,9 +637,8 @@ FullO3CPU<Impl>::tick() } } -#if !FULL_SYSTEM - updateThreadPriority(); -#endif + if (!FullSystem) + updateThreadPriority(); } template <class Impl> @@ -665,14 +659,14 @@ FullO3CPU<Impl>::init() if (icachePort.isConnected()) fetch.setIcache(); -#if FULL_SYSTEM - for (ThreadID tid = 0; tid < numThreads; tid++) { - ThreadContext *src_tc = threadContexts[tid]; - TheISA::initCPU(src_tc, src_tc->contextId()); - // Initialise the ThreadContext's memory proxies - thread[tid]->initMemProxies(thread[tid]->getTC()); + if (FullSystem) { + for (ThreadID tid = 0; tid < numThreads; tid++) { + ThreadContext *src_tc = threadContexts[tid]; + TheISA::initCPU(src_tc, src_tc->contextId()); + // Initialise the ThreadContext's memory proxies + thread[tid]->initMemProxies(thread[tid]->getTC()); + } } -#endif // Clear inSyscall. for (int tid = 0; tid < numThreads; ++tid) @@ -813,11 +807,11 @@ FullO3CPU<Impl>::insertThread(ThreadID tid) DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); // Will change now that the PC and thread state is internal to the CPU // and not in the ThreadContext. -#if FULL_SYSTEM - ThreadContext *src_tc = system->threadContexts[tid]; -#else - ThreadContext *src_tc = tcBase(tid); -#endif + ThreadContext *src_tc; + if (FullSystem) + src_tc = system->threadContexts[tid]; + else + src_tc = tcBase(tid); //Bind Int Regs to Rename Map for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { @@ -968,7 +962,6 @@ FullO3CPU<Impl>::activateWhenReady(ThreadID tid) } } -#if FULL_SYSTEM template <class Impl> Fault FullO3CPU<Impl>::hwrei(ThreadID tid) @@ -1035,8 +1028,6 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt) this->trap(interrupt, 0, NULL); } -#endif - template <class Impl> void FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) @@ -1045,8 +1036,6 @@ FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) fault->invoke(this->threadContexts[tid], inst); } -#if !FULL_SYSTEM - template <class Impl> void FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) @@ -1067,8 +1056,6 @@ FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) --(this->thread[tid]->funcExeInst); } -#endif - template <class Impl> void FullO3CPU<Impl>::serialize(std::ostream &os) @@ -1662,7 +1649,6 @@ FullO3CPU<Impl>::wakeCPU() schedule(tickEvent, nextCycle()); } -#if FULL_SYSTEM template <class Impl> void FullO3CPU<Impl>::wakeup() @@ -1675,7 +1661,6 @@ FullO3CPU<Impl>::wakeup() DPRINTF(Quiesce, "Suspended Processor woken\n"); this->threadContexts[0]->activate(); } -#endif template <class Impl> ThreadID diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 121253475..165144c1b 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -54,7 +54,6 @@ #include "arch/types.hh" #include "base/statistics.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "config/use_checker.hh" #include "cpu/o3/comm.hh" @@ -424,12 +423,10 @@ class FullO3CPU : public BaseO3CPU virtual void unserialize(Checkpoint *cp, const std::string §ion); public: -#if !FULL_SYSTEM /** Executes a syscall. * @todo: Determine if this needs to be virtual. */ void syscall(int64_t callnum, ThreadID tid); -#endif /** Starts draining the CPU's pipeline of all instructions in * order to stop all memory accesses. */ @@ -454,7 +451,6 @@ class FullO3CPU : public BaseO3CPU /** Traps to handle given fault. */ void trap(Fault fault, ThreadID tid, StaticInstPtr inst); -#if FULL_SYSTEM /** HW return from error interrupt. */ Fault hwrei(ThreadID tid); @@ -474,7 +470,6 @@ class FullO3CPU : public BaseO3CPU /** Check if this address is a valid data address. */ bool validDataAddr(Addr addr) { return true; } -#endif /** Register accessors. Index refers to the physical register index. */ @@ -709,9 +704,7 @@ class FullO3CPU : public BaseO3CPU /** Wakes the CPU, rescheduling the CPU if it's not already active. */ void wakeCPU(); -#if FULL_SYSTEM virtual void wakeup(); -#endif /** Gets a free thread id. Use if thread ids change across system. */ ThreadID getFreeTid(); diff --git a/src/cpu/o3/cpu_builder.cc b/src/cpu/o3/cpu_builder.cc index 097dc7181..296ad1793 100644 --- a/src/cpu/o3/cpu_builder.cc +++ b/src/cpu/o3/cpu_builder.cc @@ -30,7 +30,6 @@ #include <string> -#include "config/full_system.hh" #include "config/use_checker.hh" #include "cpu/o3/cpu.hh" #include "cpu/o3/impl.hh" @@ -47,22 +46,23 @@ class DerivO3CPU : public FullO3CPU<O3CPUImpl> DerivO3CPU * DerivO3CPUParams::create() { -#if FULL_SYSTEM - // Full-system only supports a single thread for the moment. - ThreadID actual_num_threads = 1; -#else - if (workload.size() > numThreads) { - fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU", - workload.size(), numThreads); - } else if (workload.size() == 0) { - fatal("Must specify at least one workload!"); + ThreadID actual_num_threads; + if (FullSystem) { + // Full-system only supports a single thread for the moment. + actual_num_threads = 1; + } else { + if (workload.size() > numThreads) { + fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU", + workload.size(), numThreads); + } else if (workload.size() == 0) { + fatal("Must specify at least one workload!"); + } + + // In non-full-system mode, we infer the number of threads from + // the workload if it's not explicitly specified. + actual_num_threads = + (numThreads >= workload.size()) ? numThreads : workload.size(); } - - // In non-full-system mode, we infer the number of threads from - // the workload if it's not explicitly specified. - ThreadID actual_num_threads = - (numThreads >= workload.size()) ? numThreads : workload.size(); -#endif numThreads = actual_num_threads; diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index a523a8b45..985e92826 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -30,13 +30,13 @@ #include "arch/types.hh" #include "base/trace.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/o3/decode.hh" #include "cpu/inst_seq.hh" #include "debug/Activity.hh" #include "debug/Decode.hh" #include "params/DerivO3CPU.hh" +#include "sim/full_system.hh" using namespace std; @@ -322,19 +322,18 @@ DefaultDecode<Impl>::squash(ThreadID tid) if (decodeStatus[tid] == Blocked || decodeStatus[tid] == Unblocking) { -#if !FULL_SYSTEM - // In syscall emulation, we can have both a block and a squash due - // to a syscall in the same cycle. This would cause both signals to - // be high. This shouldn't happen in full system. - // @todo: Determine if this still happens. - if (toFetch->decodeBlock[tid]) { - toFetch->decodeBlock[tid] = 0; - } else { + if (FullSystem) { toFetch->decodeUnblock[tid] = 1; + } else { + // In syscall emulation, we can have both a block and a squash due + // to a syscall in the same cycle. This would cause both signals + // to be high. This shouldn't happen in full system. + // @todo: Determine if this still happens. + if (toFetch->decodeBlock[tid]) + toFetch->decodeBlock[tid] = 0; + else + toFetch->decodeUnblock[tid] = 1; } -#else - toFetch->decodeUnblock[tid] = 1; -#endif } // Set status to squashing. diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index e58eb99c5..1b101ede9 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -199,13 +199,11 @@ class BaseO3DynInst : public BaseDynInst<Impl> this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg)); } } -#if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); /** Traps to handle specified fault. */ void trap(Fault fault); bool simPalCheck(int palFunc); -#endif /** Emulates a syscall. */ void syscall(int64_t callnum); diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh index 500d63de8..93ae83441 100644 --- a/src/cpu/o3/dyn_inst_impl.hh +++ b/src/cpu/o3/dyn_inst_impl.hh @@ -42,6 +42,7 @@ #include "base/cp_annotate.hh" #include "cpu/o3/dyn_inst.hh" +#include "sim/full_system.hh" template <class Impl> BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, @@ -143,7 +144,6 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) return this->fault; } -#if FULL_SYSTEM template <class Impl> Fault BaseO3DynInst<Impl>::hwrei() @@ -188,24 +188,23 @@ BaseO3DynInst<Impl>::simPalCheck(int palFunc) #endif return this->cpu->simPalCheck(palFunc, this->threadNumber); } -#endif template <class Impl> void BaseO3DynInst<Impl>::syscall(int64_t callnum) { -#if FULL_SYSTEM - panic("Syscall emulation isn't available in FS mode.\n"); -#else - // HACK: check CPU's nextPC before and after syscall. If it - // changes, update this instruction's nextPC because the syscall - // must have changed the nextPC. - TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); - this->cpu->syscall(callnum, this->threadNumber); - TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); - if (!(curPC == newPC)) { - this->pcState(newPC); + if (FullSystem) { + panic("Syscall emulation isn't available in FS mode.\n"); + } else { + // HACK: check CPU's nextPC before and after syscall. If it + // changes, update this instruction's nextPC because the syscall + // must have changed the nextPC. + TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); + this->cpu->syscall(callnum, this->threadNumber); + TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); + if (!(curPC == newPC)) { + this->pcState(newPC); + } } -#endif } diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index d145fb099..1b82f8a4c 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -45,7 +45,9 @@ #include <cstring> #include "arch/isa_traits.hh" +#include "arch/tlb.hh" #include "arch/utility.hh" +#include "arch/vtophys.hh" #include "base/types.hh" #include "config/the_isa.hh" #include "config/use_checker.hh" @@ -61,12 +63,8 @@ #include "sim/byteswap.hh" #include "sim/core.hh" #include "sim/eventq.hh" - -#if FULL_SYSTEM -#include "arch/tlb.hh" -#include "arch/vtophys.hh" +#include "sim/full_system.hh" #include "sim/system.hh" -#endif // FULL_SYSTEM using namespace std; @@ -840,15 +838,15 @@ DefaultFetch<Impl>::tick() DPRINTF(Fetch, "Running stage.\n"); - #if FULL_SYSTEM - if (fromCommit->commitInfo[0].interruptPending) { - interruptPending = true; - } + if (FullSystem) { + if (fromCommit->commitInfo[0].interruptPending) { + interruptPending = true; + } - if (fromCommit->commitInfo[0].clearInterrupt) { - interruptPending = false; + if (fromCommit->commitInfo[0].clearInterrupt) { + interruptPending = false; + } } -#endif for (threadFetched = 0; threadFetched < numFetchingThreads; threadFetched++) { diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index c58361cd6..0d7e0f68f 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -47,7 +47,6 @@ #include <set> #include "base/statistics.hh" -#include "config/full_system.hh" #include "cpu/o3/comm.hh" #include "cpu/o3/lsq.hh" #include "cpu/o3/scoreboard.hh" diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 731c67ae6..db127a2da 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -46,7 +46,6 @@ #include <map> #include <queue> -#include "config/full_system.hh" #include "cpu/o3/lsq_unit.hh" #include "cpu/inst_seq.hh" #include "mem/port.hh" diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 3c1af4533..0882dcf20 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -44,7 +44,6 @@ #include "arch/mmapped_ipr.hh" #include "base/fast_alloc.hh" #include "base/hashmap.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/inst_seq.hh" #include "cpu/timebuf.hh" diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index d04f45cc0..117c955c2 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -35,17 +35,13 @@ #include <vector> #include "arch/isa_traits.hh" +#include "arch/kernel_stats.hh" #include "arch/types.hh" #include "base/trace.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/o3/comm.hh" #include "debug/IEW.hh" -#if FULL_SYSTEM -#include "arch/kernel_stats.hh" -#endif - /** * Simple physical register file class. * Right now this is specific to Alpha until we decide if/how to make things @@ -174,10 +170,8 @@ class PhysRegFile /** Floating point register file. */ PhysFloatReg *floatRegFile; -#if FULL_SYSTEM private: int intrflag; // interrupt flag -#endif private: /** CPU pointer. */ diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 98c0f231b..04935604e 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -45,7 +45,6 @@ #include "arch/isa_traits.hh" #include "arch/registers.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/o3/rename.hh" #include "debug/Activity.hh" diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh index dcde54a54..0484f519c 100644 --- a/src/cpu/o3/rob_impl.hh +++ b/src/cpu/o3/rob_impl.hh @@ -31,7 +31,6 @@ #include <list> -#include "config/full_system.hh" #include "cpu/o3/rob.hh" #include "debug/Fetch.hh" #include "debug/ROB.hh" diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 6ac745770..ff6ca0093 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -92,24 +92,23 @@ class O3ThreadContext : public ThreadContext /** Returns a pointer to the system. */ virtual System *getSystemPtr() { return cpu->system; } -#if FULL_SYSTEM /** Returns a pointer to this thread's kernel statistics. */ virtual TheISA::Kernel::Statistics *getKernelStats() { return thread->kernelStats; } + /** Returns a pointer to this thread's process. */ + virtual Process *getProcessPtr() { return thread->getProcessPtr(); } + virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); } virtual FSTranslatingPortProxy* getVirtProxy(); virtual void initMemProxies(ThreadContext *tc) { thread->initMemProxies(tc); } -#else + virtual SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); } - /** Returns a pointer to this thread's process. */ - virtual Process *getProcessPtr() { return thread->getProcessPtr(); } -#endif /** Returns this thread's status. */ virtual Status status() const { return thread->status(); } @@ -127,12 +126,11 @@ class O3ThreadContext : public ThreadContext /** Set the status to Halted. */ virtual void halt(int delay = 0); -#if FULL_SYSTEM /** Dumps the function profiling information. * @todo: Implement. */ virtual void dumpFuncProfile(); -#endif + /** Takes over execution of a thread from another CPU. */ virtual void takeOverFrom(ThreadContext *old_context); @@ -144,7 +142,6 @@ class O3ThreadContext : public ThreadContext /** Unserializes state. */ virtual void unserialize(Checkpoint *cp, const std::string §ion); -#if FULL_SYSTEM /** Reads the last tick that this thread was activated on. */ virtual Tick readLastActivate(); /** Reads the last tick that this thread was suspended on. */ @@ -154,7 +151,6 @@ class O3ThreadContext : public ThreadContext virtual void profileClear(); /** Samples the function profiling information. */ virtual void profileSample(); -#endif /** Copies the architectural registers from another TC into this TC. */ virtual void copyArchRegs(ThreadContext *tc); @@ -231,20 +227,18 @@ class O3ThreadContext : public ThreadContext * misspeculating, this is set as false. */ virtual bool misspeculating() { return false; } -#if !FULL_SYSTEM /** Executes a syscall in SE mode. */ virtual void syscall(int64_t callnum) { return cpu->syscall(callnum, thread->threadId()); } /** Reads the funcExeInst counter. */ virtual Counter readFuncExeInst() { return thread->funcExeInst; } -#else + /** Returns pointer to the quiesce event. */ virtual EndQuiesceEvent *getQuiesceEvent() { return this->thread->quiesceEvent; } -#endif }; diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 4c2fee22d..5ba454458 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -41,13 +41,13 @@ * Korey Sewell */ +#include "arch/kernel_stats.hh" #include "arch/registers.hh" #include "config/the_isa.hh" #include "cpu/o3/thread_context.hh" #include "cpu/quiesce_event.hh" #include "debug/O3CPU.hh" -#if FULL_SYSTEM template <class Impl> FSTranslatingPortProxy* O3ThreadContext<Impl>::getVirtProxy() @@ -61,18 +61,14 @@ O3ThreadContext<Impl>::dumpFuncProfile() { thread->dumpFuncProfile(); } -#endif template <class Impl> void O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) { // some things should already be set up -#if FULL_SYSTEM assert(getSystemPtr() == old_context->getSystemPtr()); -#else assert(getProcessPtr() == old_context->getProcessPtr()); -#endif // copy over functional state setStatus(old_context->status()); @@ -80,24 +76,23 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) setContextId(old_context->contextId()); setThreadId(old_context->threadId()); -#if !FULL_SYSTEM - thread->funcExeInst = old_context->readFuncExeInst(); -#else - EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); - if (other_quiesce) { - // Point the quiesce event's TC at this TC so that it wakes up - // the proper CPU. - other_quiesce->tc = this; + if (FullSystem) { + EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); + if (other_quiesce) { + // Point the quiesce event's TC at this TC so that it wakes up + // the proper CPU. + other_quiesce->tc = this; + } + if (thread->quiesceEvent) { + thread->quiesceEvent->tc = this; + } + + // Transfer kernel stats from one CPU to the other. + thread->kernelStats = old_context->getKernelStats(); + cpu->lockFlag = false; + } else { + thread->funcExeInst = old_context->readFuncExeInst(); } - if (thread->quiesceEvent) { - thread->quiesceEvent->tc = this; - } - - // Transfer kernel stats from one CPU to the other. - thread->kernelStats = old_context->getKernelStats(); -// storeCondFailures = 0; - cpu->lockFlag = false; -#endif old_context->setStatus(ThreadContext::Halted); @@ -115,10 +110,7 @@ O3ThreadContext<Impl>::activate(int delay) if (thread->status() == ThreadContext::Active) return; -#if FULL_SYSTEM thread->lastActivate = curTick(); -#endif - thread->setStatus(ThreadContext::Active); // status() == Suspended @@ -135,19 +127,9 @@ O3ThreadContext<Impl>::suspend(int delay) if (thread->status() == ThreadContext::Suspended) return; -#if FULL_SYSTEM thread->lastActivate = curTick(); thread->lastSuspend = curTick(); -#endif -/* -#if FULL_SYSTEM - // Don't change the status from active if there are pending interrupts - if (cpu->checkInterrupts()) { - assert(status() == ThreadContext::Active); - return; - } -#endif -*/ + thread->setStatus(ThreadContext::Suspended); cpu->suspendContext(thread->threadId()); } @@ -170,35 +152,28 @@ template <class Impl> void O3ThreadContext<Impl>::regStats(const std::string &name) { -#if FULL_SYSTEM - thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); - thread->kernelStats->regStats(name + ".kern"); -#endif + if (FullSystem) { + thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); + thread->kernelStats->regStats(name + ".kern"); + } } template <class Impl> void O3ThreadContext<Impl>::serialize(std::ostream &os) { -#if FULL_SYSTEM - if (thread->kernelStats) + if (FullSystem && thread->kernelStats) thread->kernelStats->serialize(os); -#endif - } template <class Impl> void O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) { -#if FULL_SYSTEM - if (thread->kernelStats) + if (FullSystem && thread->kernelStats) thread->kernelStats->unserialize(cp, section); -#endif - } -#if FULL_SYSTEM template <class Impl> Tick O3ThreadContext<Impl>::readLastActivate() @@ -226,7 +201,6 @@ O3ThreadContext<Impl>::profileSample() { thread->profileSample(); } -#endif template <class Impl> void @@ -237,9 +211,8 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) TheISA::copyRegs(tc, this); thread->inSyscall = false; -#if !FULL_SYSTEM - this->thread->funcExeInst = tc->readFuncExeInst(); -#endif + if (!FullSystem) + this->thread->funcExeInst = tc->readFuncExeInst(); } template <class Impl> diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 1171053b9..fc54ec33c 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -35,19 +35,15 @@ #include "base/output.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" +#include "sim/full_system.hh" #include "sim/sim_exit.hh" -class Event; -class Process; - -#if FULL_SYSTEM class EndQuiesceEvent; -class FunctionProfile; -class ProfileNode; -#else +class Event; class FunctionalMemory; +class FunctionProfile; class Process; -#endif +class ProfileNode; /** * Class that has various thread state, such as the status, the @@ -75,31 +71,27 @@ struct O3ThreadState : public ThreadState { */ bool trapPending; -#if FULL_SYSTEM - O3ThreadState(O3CPU *_cpu, int _thread_num) - : ThreadState(_cpu, _thread_num), + O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process) + : ThreadState(_cpu, _thread_num, _process), cpu(_cpu), inSyscall(0), trapPending(0) { - if (cpu->params()->profile) { - profile = new FunctionProfile(cpu->params()->system->kernelSymtab); - Callback *cb = - new MakeCallback<O3ThreadState, - &O3ThreadState::dumpFuncProfile>(this); - registerExitCallback(cb); - } + if (FullSystem) { + if (cpu->params()->profile) { + profile = new FunctionProfile( + cpu->params()->system->kernelSymtab); + Callback *cb = + new MakeCallback<O3ThreadState, + &O3ThreadState::dumpFuncProfile>(this); + registerExitCallback(cb); + } - // let's fill with a dummy node for now so we don't get a segfault - // on the first cycle when there's no node available. - static ProfileNode dummyNode; - profileNode = &dummyNode; - profilePC = 3; + // let's fill with a dummy node for now so we don't get a segfault + // on the first cycle when there's no node available. + static ProfileNode dummyNode; + profileNode = &dummyNode; + profilePC = 3; + } } -#else - O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process) - : ThreadState(_cpu, _thread_num, _process), - cpu(_cpu), inSyscall(0), trapPending(0) - { } -#endif /** Pointer to the ThreadContext of this thread. */ ThreadContext *tc; @@ -107,18 +99,14 @@ struct O3ThreadState : public ThreadState { /** Returns a pointer to the TC of this thread. */ ThreadContext *getTC() { return tc; } -#if !FULL_SYSTEM /** Handles the syscall. */ void syscall(int64_t callnum) { process->syscall(callnum, tc); } -#endif -#if FULL_SYSTEM void dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); profile->dump(tc, *os); } -#endif }; #endif // __CPU_O3_THREAD_STATE_HH__ diff --git a/src/cpu/ozone/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py index d4620cd8e..d79418b27 100644 --- a/src/cpu/ozone/SimpleOzoneCPU.py +++ b/src/cpu/ozone/SimpleOzoneCPU.py @@ -35,8 +35,7 @@ class SimpleOzoneCPU(BaseCPU): numThreads = Param.Unsigned("number of HW thread contexts") - if not buildEnv['FULL_SYSTEM']: - mem = Param.FunctionalMemory(NULL, "memory") + mem = Param.FunctionalMemory(NULL, "memory") width = Param.Unsigned("Width") frontEndWidth = Param.Unsigned("Front end width") diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh index 169f328ad..1df0cdf0e 100644 --- a/src/cpu/ozone/back_end_impl.hh +++ b/src/cpu/ozone/back_end_impl.hh @@ -1456,7 +1456,6 @@ BackEnd<Impl>::commitInst(int inst_num) // thread->funcExeInst--; if (inst->isNonSpeculative()) { -#if !FULL_SYSTEM // Hack to make sure syscalls aren't executed until all stores // write back their data. This direct communication shouldn't // be used for anything other than this. @@ -1464,7 +1463,6 @@ BackEnd<Impl>::commitInst(int inst_num) DPRINTF(BE, "Waiting for all stores to writeback.\n"); return false; } -#endif DPRINTF(BE, "Encountered a store or non-speculative " "instruction at the head of the ROB, PC %#x.\n", @@ -1512,7 +1510,6 @@ BackEnd<Impl>::commitInst(int inst_num) if (inst_fault != NoFault) { if (!inst->isNop()) { -#if FULL_SYSTEM DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n", inst->seqNum, inst->readPC()); @@ -1533,10 +1530,6 @@ BackEnd<Impl>::commitInst(int inst_num) // generateTrapEvent(); return false; -#else // !FULL_SYSTEM - panic("fault (%d) detected @ PC %08p", inst_fault, - inst->PC); -#endif // FULL_SYSTEM } } @@ -1574,7 +1567,6 @@ BackEnd<Impl>::commitInst(int inst_num) // Write the done sequence number here. toIEW->doneSeqNum = inst->seqNum; -#if FULL_SYSTEM int count = 0; Addr oldpc; do { @@ -1591,7 +1583,6 @@ BackEnd<Impl>::commitInst(int inst_num) // squashPending = true; return false; } -#endif return true; } diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc index 6baa95658..f4bb03dcc 100644 --- a/src/cpu/ozone/checker_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -91,11 +91,8 @@ OzoneCheckerParams::create() params->dtb = dtb; params->system = system; params->cpu_id = cpu_id; -#if FULL_SYSTEM params->profile = profile; -#else params->process = workload; -#endif OzoneChecker *cpu = new OzoneChecker(params); return cpu; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 541fea44c..ff43ad6cb 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -33,8 +33,8 @@ #include <set> +#include "arch/alpha/tlb.hh" #include "base/statistics.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/ozone/rename_table.hh" #include "cpu/ozone/thread_state.hh" @@ -48,31 +48,20 @@ #include "sim/eventq.hh" // forward declarations -#if FULL_SYSTEM -#include "arch/alpha/tlb.hh" - -namespace TheISA -{ - class TLB; -} -class PhysicalMemory; -class MemoryController; namespace TheISA { namespace Kernel { class Statistics; }; + class TLB; }; -#else - -class Process; - -#endif // FULL_SYSTEM - class Checkpoint; class EndQuiesceEvent; +class MemoryController; class MemObject; +class PhysicalMemory; +class Process; class Request; namespace Trace { @@ -116,7 +105,6 @@ class OzoneCPU : public BaseCPU TheISA::TLB * getDTBPtr() { return cpu->dtb; } -#if FULL_SYSTEM System *getSystemPtr() { return cpu->system; } PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } @@ -124,15 +112,14 @@ class OzoneCPU : public BaseCPU TheISA::Kernel::Statistics *getKernelStats() { return thread->getKernelStats(); } + Process *getProcessPtr() { return thread->getProcessPtr(); } + PortProxy* getPhysProxy() { return thread->getPhysProxy(); } FSTranslatingPortProxy* getVirtProxy() { return thread->getVirtProxy(); } -#else - SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); } - Process *getProcessPtr() { return thread->getProcessPtr(); } -#endif + SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); } Status status() const { return thread->status(); } @@ -148,9 +135,7 @@ class OzoneCPU : public BaseCPU /// Set the status to Halted. void halt(); -#if FULL_SYSTEM void dumpFuncProfile(); -#endif void takeOverFrom(ThreadContext *old_context); @@ -159,7 +144,6 @@ class OzoneCPU : public BaseCPU void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); -#if FULL_SYSTEM EndQuiesceEvent *getQuiesceEvent(); Tick readLastActivate(); @@ -167,7 +151,6 @@ class OzoneCPU : public BaseCPU void profileClear(); void profileSample(); -#endif int threadId(); @@ -227,12 +210,10 @@ class OzoneCPU : public BaseCPU bool misspeculating() { return false; } -#if !FULL_SYSTEM Counter readFuncExeInst() { return thread->funcExeInst; } void setFuncExeInst(Counter new_val) { thread->funcExeInst = new_val; } -#endif }; // Ozone specific thread context @@ -326,7 +307,6 @@ class OzoneCPU : public BaseCPU int switchCount; -#if FULL_SYSTEM Addr dbg_vtophys(Addr addr); bool interval_stats; @@ -335,7 +315,6 @@ class OzoneCPU : public BaseCPU TheISA::TLB *dtb; System *system; PhysicalMemory *physmem; -#endif virtual Port *getPort(const std::string &name, int idx); @@ -414,13 +393,10 @@ class OzoneCPU : public BaseCPU void dumpInsts() { frontEnd->dumpInsts(); } -#if FULL_SYSTEM Fault hwrei(); bool simPalCheck(int palFunc); void processInterrupts(); -#else void syscall(uint64_t &callnum); -#endif ThreadContext *tcBase() { return tc; } diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 63b7eb6ff..65f68152f 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -57,21 +57,20 @@ DerivOzoneCPUParams::create() { DerivOzoneCPU *cpu; -#if FULL_SYSTEM - // Full-system only supports a single thread for the moment. - ThreadID actual_num_threads = 1; -#else - // In non-full-system mode, we infer the number of threads from - // the workload if it's not explicitly specified. - ThreadID actual_num_threads = - numThreads.isValid() ? numThreads : workload.size(); - - if (workload.size() == 0) { - fatal("Must specify at least one workload!"); + if (FullSystem) { + // Full-system only supports a single thread for the moment. + ThreadID actual_num_threads = 1; + } else { + // In non-full-system mode, we infer the number of threads from + // the workload if it's not explicitly specified. + ThreadID actual_num_threads = + numThreads.isValid() ? numThreads : workload.size(); + + if (workload.size() == 0) { + fatal("Must specify at least one workload!"); + } } -#endif - SimpleParams *params = new SimpleParams; params->clock = clock; @@ -84,15 +83,11 @@ DerivOzoneCPUParams::create() params->system = system; params->cpu_id = cpu_id; -#if FULL_SYSTEM params->profile = profile; params->do_quiesce = do_quiesce; params->do_checkpoint_insts = do_checkpoint_insts; params->do_statistics_insts = do_statistics_insts; -#else params->workload = workload; -// params->pTable = page_table; -#endif // FULL_SYSTEM params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 273d46bdc..f532078fe 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -29,37 +29,33 @@ * Nathan Binkert */ +#include "arch/alpha/osfpal.hh" +#include "arch/faults.hh" #include "arch/isa_traits.hh" // For MachInst +#include "arch/kernel_stats.hh" +#include "arch/tlb.hh" +#include "arch/types.hh" +#include "arch/vtophys.hh" +#include "base/callback.hh" #include "base/trace.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "config/use_checker.hh" #include "cpu/ozone/cpu.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" +#include "cpu/profile.hh" #include "cpu/quiesce_event.hh" #include "cpu/simple_thread.hh" #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" -#include "sim/sim_object.hh" -#include "sim/stats.hh" - -#if FULL_SYSTEM -#include "arch/alpha/osfpal.hh" -#include "arch/faults.hh" -#include "arch/kernel_stats.hh" -#include "arch/tlb.hh" -#include "arch/types.hh" -#include "arch/vtophys.hh" -#include "base/callback.hh" -#include "cpu/profile.hh" #include "sim/faults.hh" +#include "sim/full_system.hh" +#include "sim/process.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" +#include "sim/sim_object.hh" +#include "sim/stats.hh" #include "sim/system.hh" -#else // !FULL_SYSTEM -#include "sim/process.hh" -#endif // FULL_SYSTEM #if USE_CHECKER #include "cpu/checker/thread_context.hh" @@ -89,12 +85,8 @@ OzoneCPU<Impl>::TickEvent::description() const template <class Impl> OzoneCPU<Impl>::OzoneCPU(Params *p) -#if FULL_SYSTEM - : BaseCPU(p), thread(this, 0), tickEvent(this, p->width), -#else - : BaseCPU(p), thread(this, 0, p->workload[0], 0), - tickEvent(this, p->width), -#endif + : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, + p->width), #ifndef NDEBUG instcount(0), #endif @@ -109,9 +101,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p) #if USE_CHECKER BaseCPU *temp_checker = p->checker; checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); -#if FULL_SYSTEM checker->setSystem(p->system); -#endif checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker); thread.tc = checkerTC; tc = checkerTC; @@ -133,33 +123,35 @@ OzoneCPU<Impl>::OzoneCPU(Params *p) itb = p->itb; dtb = p->dtb; -#if FULL_SYSTEM - // Setup thread state stuff. - thread.cpu = this; - thread.setTid(0); - - thread.quiesceEvent = new EndQuiesceEvent(tc); - - system = p->system; - physmem = p->system->physmem; - - if (p->profile) { - thread.profile = new FunctionProfile(p->system->kernelSymtab); - // @todo: This might be better as an ThreadContext instead of OzoneTC - Callback *cb = - new MakeCallback<OzoneTC, - &OzoneTC::dumpFuncProfile>(&ozoneTC); - registerExitCallback(cb); - } - // let's fill with a dummy node for now so we don't get a segfault - // on the first cycle when there's no node available. - static ProfileNode dummyNode; - thread.profileNode = &dummyNode; - thread.profilePC = 3; -#else - thread.cpu = this; -#endif // !FULL_SYSTEM + if (FullSystem) { + // Setup thread state stuff. + thread.cpu = this; + thread.setTid(0); + + thread.quiesceEvent = new EndQuiesceEvent(tc); + + system = p->system; + physmem = p->system->physmem; + + if (p->profile) { + thread.profile = new FunctionProfile(p->system->kernelSymtab); + // @todo: This might be better as an ThreadContext instead of + // OzoneTC + Callback *cb = + new MakeCallback<OzoneTC, + &OzoneTC::dumpFuncProfile>(&ozoneTC); + registerExitCallback(cb); + } + + // let's fill with a dummy node for now so we don't get a segfault + // on the first cycle when there's no node available. + static ProfileNode dummyNode; + thread.profileNode = &dummyNode; + thread.profilePC = 3; + } else { + thread.cpu = this; + } numInst = 0; startNumInst = 0; @@ -194,9 +186,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p) frontEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable); -#if FULL_SYSTEM thread.connectMemPorts(tc); -#endif DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n"); } @@ -305,10 +295,8 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay) notIdleFraction++; scheduleTickEvent(delay); _status = Running; -#if FULL_SYSTEM if (thread.quiesceEvent && thread.quiesceEvent->scheduled()) thread.quiesceEvent->deschedule(); -#endif thread.setStatus(ThreadContext::Active); frontEnd->wakeFromQuiesce(); } @@ -398,14 +386,14 @@ OzoneCPU<Impl>::init() // Mark this as in syscall so it won't need to squash thread.inSyscall = true; -#if FULL_SYSTEM - for (int i = 0; i < threadContexts.size(); ++i) { - ThreadContext *tc = threadContexts[i]; + if (FullSystem) { + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; - // initialize CPU, including PC - TheISA::initCPU(tc, tc->contextId()); + // initialize CPU, including PC + TheISA::initCPU(tc, tc->contextId()); + } } -#endif frontEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable); @@ -464,29 +452,24 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) thread.getTC()->copyArchRegs(temp.getTC()); } -#if FULL_SYSTEM template <class Impl> Addr OzoneCPU<Impl>::dbg_vtophys(Addr addr) { return vtophys(tc, addr); } -#endif // FULL_SYSTEM -#if FULL_SYSTEM template <class Impl> void OzoneCPU<Impl>::wakeup() { if (_status == Idle) { DPRINTF(IPI,"Suspended Processor awoke\n"); -// thread.activate(); // Hack for now. Otherwise might have to go through the tc, or // I need to figure out what's the right thing to call. activateContext(thread.threadId(), 1); } } -#endif // FULL_SYSTEM /* start simulation, program loaded, processor precise state initialized */ template <class Impl> @@ -519,7 +502,6 @@ OzoneCPU<Impl>::squashFromTC() backEnd->generateTCEvent(); } -#if !FULL_SYSTEM template <class Impl> void OzoneCPU<Impl>::syscall(uint64_t &callnum) @@ -542,7 +524,7 @@ OzoneCPU<Impl>::syscall(uint64_t &callnum) frontEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable); } -#else + template <class Impl> Fault OzoneCPU<Impl>::hwrei() @@ -600,7 +582,6 @@ OzoneCPU<Impl>::simPalCheck(int palFunc) return true; } -#endif template <class Impl> BaseCPU * @@ -639,25 +620,20 @@ OzoneCPU<Impl>::OzoneTC::halt() cpu->haltContext(thread->threadId()); } -#if FULL_SYSTEM template <class Impl> void OzoneCPU<Impl>::OzoneTC::dumpFuncProfile() { thread->dumpFuncProfile(); } -#endif template <class Impl> void OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context) { // some things should already be set up -#if FULL_SYSTEM assert(getSystemPtr() == old_context->getSystemPtr()); -#else assert(getProcessPtr() == old_context->getProcessPtr()); -#endif // copy over functional state setStatus(old_context->status()); @@ -665,9 +641,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context) setCpuId(old_context->cpuId()); setContextId(old_context->contextId()); -#if !FULL_SYSTEM setFuncExeInst(old_context->readFuncExeInst()); -#else EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); if (other_quiesce) { // Point the quiesce event's TC at this TC so that it wakes up @@ -691,10 +665,10 @@ template <class Impl> void OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name) { -#if FULL_SYSTEM - thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); - thread->kernelStats->regStats(name + ".kern"); -#endif + if (FullSystem) { + thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); + thread->kernelStats->regStats(name + ".kern"); + } } template <class Impl> @@ -711,7 +685,6 @@ void OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion) { } -#if FULL_SYSTEM template <class Impl> EndQuiesceEvent * OzoneCPU<Impl>::OzoneTC::getQuiesceEvent() @@ -746,7 +719,6 @@ OzoneCPU<Impl>::OzoneTC::profileSample() { thread->profileSample(); } -#endif template <class Impl> int @@ -781,9 +753,7 @@ OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc) thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i)); } -#if !FULL_SYSTEM thread->funcExeInst = tc->readFuncExeInst(); -#endif // Need to copy the TC values into the current rename table, // copy the misc regs. diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index c1853b1ed..b5c0bee7c 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -36,7 +36,6 @@ #include "arch/isa_traits.hh" #include "arch/types.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/ozone/cpu.hh" // MUST include this #include "cpu/ozone/ozone_impl.hh" @@ -214,13 +213,10 @@ class OzoneDynInst : public BaseDynInst<Impl> void setMiscReg(int misc_reg, const MiscReg &val); -#if FULL_SYSTEM Fault hwrei(); void trap(Fault fault); bool simPalCheck(int palFunc); -#else void syscall(uint64_t &callnum); -#endif ListIt iqIt; bool iqItValid; diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 5eb8ea8da..96d326ffc 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -28,14 +28,10 @@ * Authors: Kevin Lim */ -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/ozone/dyn_inst.hh" -#include "sim/faults.hh" - -#if FULL_SYSTEM #include "kern/kernel_stats.hh" -#endif +#include "sim/faults.hh" template <class Impl> OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu) @@ -239,8 +235,6 @@ OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val) this->thread->setMiscReg(misc_reg, val); } -#if FULL_SYSTEM - template <class Impl> Fault OzoneDynInst<Impl>::hwrei() @@ -269,11 +263,10 @@ OzoneDynInst<Impl>::simPalCheck(int palFunc) { return this->cpu->simPalCheck(palFunc); } -#else + template <class Impl> void OzoneDynInst<Impl>::syscall(uint64_t &callnum) { this->cpu->syscall(callnum); } -#endif diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index a11cf74bd..e7255d75f 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -426,13 +426,10 @@ FrontEnd<Impl>::tick() numInstsReady[0]++; ++num_inst; -#if FULL_SYSTEM if (inst->isQuiesce()) { -// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick()); status = QuiescePending; break; } -#endif if (inst->predTaken()) { // Start over with tick? @@ -980,9 +977,6 @@ FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc) cacheBlkValid = false; -#if !FULL_SYSTEM -// pTable = params->pTable; -#endif fetchFault = NoFault; serializeNext = false; barrierInst = NULL; diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index 5c2f9c28f..820e7d33b 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -73,9 +73,7 @@ class InorderBackEnd void regStats() { } -#if FULL_SYSTEM void checkInterrupts(); -#endif void tick(); void executeInsts(); diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 13c066fd2..59d1dab0d 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -79,7 +79,6 @@ InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr) thread->setFuncExeInst(0); } -#if FULL_SYSTEM template <class Impl> void InorderBackEnd<Impl>::checkInterrupts() @@ -134,7 +133,6 @@ InorderBackEnd<Impl>::checkInterrupts() setSquashInfoFromXC(); } } -#endif template <class Impl> void @@ -149,8 +147,7 @@ InorderBackEnd<Impl>::tick() // if (interrupt) then set thread PC, stall front end, record that // I'm waiting for it to drain. (for now just squash) -#if FULL_SYSTEM - if (interruptBlocked || cpu->checkInterrupts(tc)) { + if (FullSystem && (interruptBlocked || cpu->checkInterrupts(tc))) { if (!robEmpty()) { interruptBlocked = true; //AlphaDep @@ -165,7 +162,6 @@ InorderBackEnd<Impl>::tick() return; } } -#endif if (status != DcacheMissLoadStall && status != DcacheMissStoreStall) { @@ -180,15 +176,11 @@ InorderBackEnd<Impl>::tick() (*instsAdded)++; } -#if FULL_SYSTEM if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) { handleFault(); } else { executeInsts(); } -#else - executeInsts(); -#endif } } @@ -209,24 +201,24 @@ InorderBackEnd<Impl>::executeInsts() thread->setPC(commitPC); thread->setNextPC(inst->readNextPC()); -#if FULL_SYSTEM - int count = 0; - Addr oldpc; - do { - if (count == 0) - assert(!thread->inSyscall && !thread->trapPending); - oldpc = thread->readPC(); - cpu->system->pcEventQueue.service( - thread->getXCProxy()); - count++; - } while (oldpc != thread->readPC()); - if (count > 1) { - DPRINTF(IBE, "PC skip function event, stopping commit\n"); - completed_last_inst = false; - squashPending = true; - break; + if (FullSystem) { + int count = 0; + Addr oldpc; + do { + if (count == 0) + assert(!thread->inSyscall && !thread->trapPending); + oldpc = thread->readPC(); + cpu->system->pcEventQueue.service( + thread->getXCProxy()); + count++; + } while (oldpc != thread->readPC()); + if (count > 1) { + DPRINTF(IBE, "PC skip function event, stopping commit\n"); + completed_last_inst = false; + squashPending = true; + break; + } } -#endif Fault inst_fault = NoFault; @@ -296,7 +288,6 @@ InorderBackEnd<Impl>::executeInsts() } if (inst_fault != NoFault) { -#if FULL_SYSTEM DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n", inst->seqNum, inst->readPC()); @@ -313,14 +304,8 @@ InorderBackEnd<Impl>::executeInsts() squashPending = true; - // Generate trap squash event. -// generateTrapEvent(tid); completed_last_inst = false; break; -#else // !FULL_SYSTEM - panic("fault (%d) detected @ PC %08p", inst_fault, - inst->PC); -#endif // FULL_SYSTEM } for (int i = 0; i < inst->numDestRegs(); ++i) { diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh index 1d8328610..c812a10a2 100644 --- a/src/cpu/ozone/lsq_unit.hh +++ b/src/cpu/ozone/lsq_unit.hh @@ -38,7 +38,6 @@ #include "arch/faults.hh" #include "arch/types.hh" #include "base/hashmap.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/inst_seq.hh" #include "mem/mem_interface.hh" diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index 880d0d183..c06a58754 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -520,7 +520,6 @@ LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm) fromCommit = comm->getWire(-1); } -#if FULL_SYSTEM template <class Impl> void LWBackEnd<Impl>::checkInterrupts() @@ -557,7 +556,6 @@ LWBackEnd<Impl>::checkInterrupts() } } } -#endif template <class Impl> void @@ -604,9 +602,7 @@ LWBackEnd<Impl>::tick() wbCycle = 0; -#if FULL_SYSTEM checkInterrupts(); -#endif if (trapSquash) { assert(!tcSquash); @@ -1049,16 +1045,8 @@ LWBackEnd<Impl>::commitInst(int inst_num) (inst->isStoreConditional() && inst->getFault() == NoFault) || inst->isMemBarrier() || inst->isWriteBarrier()) { -#if !FULL_SYSTEM - // Hack to make sure syscalls aren't executed until all stores - // write back their data. This direct communication shouldn't - // be used for anything other than this. - if (inst_num > 0 || LSQ.hasStoresToWB()) -#else if ((inst->isMemBarrier() || inst->isWriteBarrier() || - inst->isQuiesce()) && - LSQ.hasStoresToWB()) -#endif + inst->isQuiesce()) && LSQ.hasStoresToWB()) { DPRINTF(BE, "Waiting for all stores to writeback.\n"); return false; @@ -1184,11 +1172,7 @@ LWBackEnd<Impl>::commitInst(int inst_num) ++freed_regs; } -#if FULL_SYSTEM - if (thread->profile) { -// bool usermode = -// (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; -// thread->profilePC = usermode ? 1 : inst->readPC(); + if (FullSystem && thread->profile) { thread->profilePC = inst->readPC(); ProfileNode *node = thread->profile->consume(thread->getTC(), inst->staticInst); @@ -1196,7 +1180,6 @@ LWBackEnd<Impl>::commitInst(int inst_num) if (node) thread->profileNode = node; } -#endif if (inst->traceData) { inst->traceData->setFetchSeq(inst->seqNum); @@ -1225,23 +1208,23 @@ LWBackEnd<Impl>::commitInst(int inst_num) toIEW->doneSeqNum = inst->seqNum; lastCommitCycle = curTick(); -#if FULL_SYSTEM - int count = 0; - Addr oldpc; - do { - if (count == 0) - assert(!thread->inSyscall && !thread->trapPending); - oldpc = thread->readPC(); - cpu->system->pcEventQueue.service( - thread->getTC()); - count++; - } while (oldpc != thread->readPC()); - if (count > 1) { - DPRINTF(BE, "PC skip function event, stopping commit\n"); - tcSquash = true; - return false; + if (FullSystem) { + int count = 0; + Addr oldpc; + do { + if (count == 0) + assert(!thread->inSyscall && !thread->trapPending); + oldpc = thread->readPC(); + cpu->system->pcEventQueue.service( + thread->getTC()); + count++; + } while (oldpc != thread->readPC()); + if (count > 1) { + DPRINTF(BE, "PC skip function event, stopping commit\n"); + tcSquash = true; + return false; + } } -#endif return true; } diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index 1add13894..dd573e5e0 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -40,7 +40,6 @@ #include "arch/types.hh" #include "base/fast_alloc.hh" #include "base/hashmap.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/inst_seq.hh" #include "mem/packet.hh" diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc index f4446ede3..512dc3b9e 100644 --- a/src/cpu/ozone/simple_cpu_builder.cc +++ b/src/cpu/ozone/simple_cpu_builder.cc @@ -60,21 +60,20 @@ SimpleOzoneCPUParams::create() { SimpleOzoneCPU *cpu; -#if FULL_SYSTEM - // Full-system only supports a single thread for the moment. - ThreadID actual_num_threads = 1; -#else - // In non-full-system mode, we infer the number of threads from - // the workload if it's not explicitly specified. - ThreadID actual_num_threads = - numThreads.isValid() ? numThreads : workload.size(); - - if (workload.size() == 0) { - fatal("Must specify at least one workload!"); + if (FullSystem) { + // Full-system only supports a single thread for the moment. + ThreadID actual_num_threads = 1; + } else { + // In non-full-system mode, we infer the number of threads from + // the workload if it's not explicitly specified. + ThreadID actual_num_threads = + numThreads.isValid() ? numThreads : workload.size(); + + if (workload.size() == 0) { + fatal("Must specify at least one workload!"); + } } -#endif - SimpleParams *params = new SimpleParams; params->clock = clock; @@ -87,10 +86,7 @@ SimpleOzoneCPUParams::create() params->system = system; params->cpu_id = cpu_id; -#if !FULL_SYSTEM params->workload = workload; -// params->pTable = page_table; -#endif // FULL_SYSTEM params->mem = mem; params->checker = checker; diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh index b241dea73..228b78128 100644 --- a/src/cpu/ozone/simple_params.hh +++ b/src/cpu/ozone/simple_params.hh @@ -56,9 +56,7 @@ class SimpleParams : public BaseCPU::Params public: TheISA::TLB *itb; TheISA::TLB *dtb; -#if !FULL_SYSTEM std::vector<Process *> workload; -#endif // FULL_SYSTEM //Page Table PageTable *pTable; diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index 638b9d86c..98ecd850c 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -45,14 +45,11 @@ class Event; //class Process; -#if FULL_SYSTEM class EndQuiesceEvent; +class FunctionalMemory; class FunctionProfile; -class ProfileNode; -#else class Process; -class FunctionalMemory; -#endif +class ProfileNode; // Maybe this ozone thread state should only really have committed state? // I need to think about why I'm using this and what it's useful for. Clearly @@ -66,7 +63,6 @@ struct OzoneThreadState : public ThreadState { typedef typename Impl::CPUType CPUType; typedef TheISA::MiscReg MiscReg; -#if FULL_SYSTEM OzoneThreadState(CPUType *_cpu, int _thread_num) : ThreadState(_cpu, -1, _thread_num), intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0) @@ -86,14 +82,13 @@ struct OzoneThreadState : public ThreadState { profilePC = 3; miscRegFile.clear(); } -#else + OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process) : ThreadState(_cpu, -1, _thread_num, _process), cpu(_cpu), inSyscall(0), trapPending(0) { miscRegFile.clear(); } -#endif RenameTable<Impl> renameTable; @@ -147,13 +142,11 @@ struct OzoneThreadState : public ThreadState { void setNextPC(uint64_t val) { nextPC = val; } -#if FULL_SYSTEM void dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); profile->dump(tc, *os); } -#endif }; #endif // __CPU_OZONE_THREAD_STATE_HH__ diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc index 385a83b27..9cf63f7d3 100644 --- a/src/cpu/pc_event.cc +++ b/src/cpu/pc_event.cc @@ -36,7 +36,6 @@ #include "base/debug.hh" #include "base/trace.hh" -#include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/pc_event.hh" #include "cpu/thread_context.hh" @@ -140,7 +139,6 @@ BreakPCEvent::process(ThreadContext *tc) delete this; } -#if FULL_SYSTEM void sched_break_pc_sys(System *sys, Addr addr) { @@ -156,4 +154,3 @@ sched_break_pc(Addr addr) } } -#endif diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 425c8b1f1..2c12b244b 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -42,6 +42,7 @@ #include "params/AtomicSimpleCPU.hh" #include "sim/faults.hh" #include "sim/system.hh" +#include "sim/full_system.hh" using namespace std; using namespace TheISA; @@ -83,18 +84,18 @@ void AtomicSimpleCPU::init() { BaseCPU::init(); -#if FULL_SYSTEM - ThreadID size = threadContexts.size(); - for (ThreadID i = 0; i < size; ++i) { - ThreadContext *tc = threadContexts[i]; - - // initialize CPU, including PC - TheISA::initCPU(tc, tc->contextId()); + if (FullSystem) { + ThreadID size = threadContexts.size(); + for (ThreadID i = 0; i < size; ++i) { + ThreadContext *tc = threadContexts[i]; + // initialize CPU, including PC + TheISA::initCPU(tc, tc->contextId()); + } } // Initialise the ThreadContext's memory proxies tcBase()->initMemProxies(tcBase()); -#endif + if (hasPhysMemPort) { AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges(); physMemAddr = *pmAddrList.begin(); @@ -560,9 +561,7 @@ AtomicSimpleCPU * AtomicSimpleCPUParams::create() { numThreads = 1; -#if !FULL_SYSTEM - if (workload.size() != 1) + if (!FullSystem && workload.size() != 1) panic("only one workload allowed"); -#endif return new AtomicSimpleCPU(this); } diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 70e2c39e6..610cc6b89 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -41,7 +41,11 @@ */ #include "arch/faults.hh" +#include "arch/kernel_stats.hh" +#include "arch/stacktrace.hh" +#include "arch/tlb.hh" #include "arch/utility.hh" +#include "arch/vtophys.hh" #include "base/loader/symtab.hh" #include "base/cp_annotate.hh" #include "base/cprintf.hh" @@ -63,37 +67,29 @@ #include "debug/Decode.hh" #include "debug/Fetch.hh" #include "debug/Quiesce.hh" +#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/request.hh" #include "params/BaseSimpleCPU.hh" #include "sim/byteswap.hh" #include "sim/debug.hh" +#include "sim/full_system.hh" #include "sim/sim_events.hh" #include "sim/sim_object.hh" #include "sim/stats.hh" #include "sim/system.hh" -#if FULL_SYSTEM -#include "arch/kernel_stats.hh" -#include "arch/stacktrace.hh" -#include "arch/tlb.hh" -#include "arch/vtophys.hh" -#else // !FULL_SYSTEM -#include "mem/mem_object.hh" -#endif // FULL_SYSTEM - using namespace std; using namespace TheISA; BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) { -#if FULL_SYSTEM - thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); -#else - thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], - p->itb, p->dtb); -#endif // !FULL_SYSTEM + if (FullSystem) + thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); + else + thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], + p->itb, p->dtb); thread->setStatus(ThreadContext::Halted); @@ -290,15 +286,12 @@ change_thread_state(ThreadID tid, int activate, int priority) { } -#if FULL_SYSTEM Addr BaseSimpleCPU::dbg_vtophys(Addr addr) { return vtophys(tc, addr); } -#endif // FULL_SYSTEM -#if FULL_SYSTEM void BaseSimpleCPU::wakeup() { @@ -308,12 +301,10 @@ BaseSimpleCPU::wakeup() DPRINTF(Quiesce,"Suspended Processor awoke\n"); thread->activate(); } -#endif // FULL_SYSTEM void BaseSimpleCPU::checkForInterrupts() { -#if FULL_SYSTEM if (checkInterrupts(tc)) { Fault interrupt = interrupts->getInterrupt(tc); @@ -324,7 +315,6 @@ BaseSimpleCPU::checkForInterrupts() predecoder.reset(); } } -#endif } @@ -422,15 +412,13 @@ BaseSimpleCPU::postExecute() TheISA::PCState pc = tc->pcState(); Addr instAddr = pc.instAddr(); -#if FULL_SYSTEM - if (thread->profile) { + if (FullSystem && thread->profile) { bool usermode = TheISA::inUserMode(tc); thread->profilePC = usermode ? 1 : instAddr; ProfileNode *node = thread->profile->consume(tc, curStaticInst); if (node) thread->profileNode = node; } -#endif if (curStaticInst->isMemRef()) { numMemRefs++; @@ -478,7 +466,8 @@ BaseSimpleCPU::postExecute() } /* End power model statistics */ - traceFunctions(instAddr); + if (FullSystem) + traceFunctions(instAddr); if (traceData) { traceData->dump(); diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index ad281aa2b..6272560a1 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -35,7 +35,6 @@ #include "arch/predecoder.hh" #include "base/statistics.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/base.hh" #include "cpu/decode.hh" @@ -46,30 +45,22 @@ #include "mem/port.hh" #include "mem/request.hh" #include "sim/eventq.hh" +#include "sim/full_system.hh" #include "sim/system.hh" // forward declarations -#if FULL_SYSTEM -class Processor; -namespace TheISA -{ - class ITB; - class DTB; -} +class Checkpoint; class MemObject; - -#else - class Process; - -#endif // FULL_SYSTEM +class Processor; +class ThreadContext; namespace TheISA { + class DTB; + class ITB; class Predecoder; } -class ThreadContext; -class Checkpoint; namespace Trace { class InstRecord; @@ -141,11 +132,9 @@ class BaseSimpleCPU : public BaseCPU public: -#if FULL_SYSTEM Addr dbg_vtophys(Addr addr); bool interval_stats; -#endif // current instruction TheISA::MachInst inst; @@ -399,19 +388,16 @@ class BaseSimpleCPU : public BaseCPU //Fault CacheOp(uint8_t Op, Addr EA); -#if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } -#endif void syscall(int64_t callnum) { -#if FULL_SYSTEM - panic("Syscall emulation isn't available in FS mode.\n"); -#else - thread->syscall(callnum); -#endif + if (FullSystem) + panic("Syscall emulation isn't available in FS mode.\n"); + else + thread->syscall(callnum); } bool misspeculating() { return thread->misspeculating(); } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index f8d13efd9..fd02e8300 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -54,6 +54,7 @@ #include "mem/packet_access.hh" #include "params/TimingSimpleCPU.hh" #include "sim/faults.hh" +#include "sim/full_system.hh" #include "sim/system.hh" using namespace std; @@ -74,17 +75,16 @@ void TimingSimpleCPU::init() { BaseCPU::init(); -#if FULL_SYSTEM - for (int i = 0; i < threadContexts.size(); ++i) { - ThreadContext *tc = threadContexts[i]; - - // initialize CPU, including PC - TheISA::initCPU(tc, _cpuId); + if (FullSystem) { + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; + // initialize CPU, including PC + TheISA::initCPU(tc, _cpuId); + } } // Initialise the ThreadContext's memory proxies tcBase()->initMemProxies(tcBase()); -#endif } void @@ -966,9 +966,7 @@ TimingSimpleCPU * TimingSimpleCPUParams::create() { numThreads = 1; -#if !FULL_SYSTEM - if (workload.size() != 1) + if (!FullSystem && workload.size() != 1) panic("only one workload allowed"); -#endif return new TimingSimpleCPU(this); } diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 2541bdee1..a12ab8e8a 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -34,39 +34,44 @@ #include <string> #include "arch/isa_traits.hh" -#include "arch/utility.hh" -#include "config/the_isa.hh" -#include "cpu/base.hh" -#include "cpu/simple_thread.hh" -#include "cpu/thread_context.hh" -#include "params/BaseCPU.hh" - -#if FULL_SYSTEM #include "arch/kernel_stats.hh" #include "arch/stacktrace.hh" +#include "arch/utility.hh" #include "base/callback.hh" #include "base/cprintf.hh" #include "base/output.hh" #include "base/trace.hh" +#include "config/the_isa.hh" +#include "cpu/base.hh" #include "cpu/profile.hh" #include "cpu/quiesce_event.hh" +#include "cpu/simple_thread.hh" +#include "cpu/thread_context.hh" +#include "params/BaseCPU.hh" #include "mem/fs_translating_port_proxy.hh" +#include "mem/se_translating_port_proxy.hh" +#include "sim/full_system.hh" +#include "sim/process.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" -#else -#include "mem/se_translating_port_proxy.hh" #include "sim/process.hh" #include "sim/system.hh" -#endif using namespace std; // constructor -#if FULL_SYSTEM +SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, + TheISA::TLB *_itb, TheISA::TLB *_dtb) + : ThreadState(_cpu, _thread_num, _process), + cpu(_cpu), itb(_itb), dtb(_dtb) +{ + clearArchRegs(); + tc = new ProxyThreadContext<SimpleThread>(this); +} SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, TheISA::TLB *_itb, TheISA::TLB *_dtb, bool use_kernel_stats) - : ThreadState(_cpu, _thread_num), + : ThreadState(_cpu, _thread_num, NULL), cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) { @@ -93,24 +98,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, if (use_kernel_stats) kernelStats = new TheISA::Kernel::Statistics(system); } -#else -SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, - TheISA::TLB *_itb, TheISA::TLB *_dtb) - : ThreadState(_cpu, _thread_num, _process), - cpu(_cpu), itb(_itb), dtb(_dtb) -{ - clearArchRegs(); - tc = new ProxyThreadContext<SimpleThread>(this); -} - -#endif SimpleThread::SimpleThread() -#if FULL_SYSTEM - : ThreadState(NULL, -1) -#else : ThreadState(NULL, -1, NULL) -#endif { tc = new ProxyThreadContext<SimpleThread>(this); } @@ -124,29 +114,27 @@ void SimpleThread::takeOverFrom(ThreadContext *oldContext) { // some things should already be set up -#if FULL_SYSTEM - assert(system == oldContext->getSystemPtr()); -#else + if (FullSystem) + assert(system == oldContext->getSystemPtr()); assert(process == oldContext->getProcessPtr()); -#endif copyState(oldContext); -#if FULL_SYSTEM - EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); - if (quiesce) { - // Point the quiesce event's TC at this TC so that it wakes up - // the proper CPU. - quiesce->tc = tc; - } - if (quiesceEvent) { - quiesceEvent->tc = tc; - } - - TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); - if (stats) { - kernelStats = stats; + if (FullSystem) { + EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); + if (quiesce) { + // Point the quiesce event's TC at this TC so that it wakes up + // the proper CPU. + quiesce->tc = tc; + } + if (quiesceEvent) { + quiesceEvent->tc = tc; + } + + TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); + if (stats) { + kernelStats = stats; + } } -#endif storeCondFailures = 0; @@ -158,16 +146,16 @@ SimpleThread::copyTC(ThreadContext *context) { copyState(context); -#if FULL_SYSTEM - EndQuiesceEvent *quiesce = context->getQuiesceEvent(); - if (quiesce) { - quiesceEvent = quiesce; - } - TheISA::Kernel::Statistics *stats = context->getKernelStats(); - if (stats) { - kernelStats = stats; + if (FullSystem) { + EndQuiesceEvent *quiesce = context->getQuiesceEvent(); + if (quiesce) { + quiesceEvent = quiesce; + } + TheISA::Kernel::Statistics *stats = context->getKernelStats(); + if (stats) { + kernelStats = stats; + } } -#endif } void @@ -176,9 +164,8 @@ SimpleThread::copyState(ThreadContext *oldContext) // copy over functional state _status = oldContext->status(); copyArchRegs(oldContext); -#if !FULL_SYSTEM - funcExeInst = oldContext->readFuncExeInst(); -#endif + if (FullSystem) + funcExeInst = oldContext->readFuncExeInst(); _threadId = oldContext->threadId(); _contextId = oldContext->contextId(); @@ -215,14 +202,12 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) isa.unserialize(cpu, cp, section); } -#if FULL_SYSTEM void SimpleThread::dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); profile->dump(tc, *os); } -#endif void SimpleThread::activate(int delay) @@ -251,15 +236,6 @@ SimpleThread::suspend() lastActivate = curTick(); lastSuspend = curTick(); -/* -#if FULL_SYSTEM - // Don't change the status from active if there are pending interrupts - if (cpu->checkInterrupts()) { - assert(status() == ThreadContext::Active); - return; - } -#endif -*/ _status = ThreadContext::Suspended; cpu->suspendContext(_threadId); } @@ -279,10 +255,8 @@ SimpleThread::halt() void SimpleThread::regStats(const string &name) { -#if FULL_SYSTEM - if (kernelStats) + if (FullSystem && kernelStats) kernelStats->regStats(name + ".kern"); -#endif } void diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index ebc23276a..f2132dc36 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -38,28 +38,27 @@ #include "arch/tlb.hh" #include "arch/types.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "cpu/decode.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" #include "debug/FloatRegs.hh" #include "debug/IntRegs.hh" +#include "mem/page_table.hh" #include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/eventq.hh" +#include "sim/process.hh" #include "sim/serialize.hh" +#include "sim/system.hh" class BaseCPU; -#if FULL_SYSTEM - -#include "sim/system.hh" class FunctionProfile; class ProfileNode; -class FunctionalPort; class PhysicalPort; +class TranslatingPort; namespace TheISA { namespace Kernel { @@ -67,14 +66,6 @@ namespace TheISA { }; }; -#else // !FULL_SYSTEM - -#include "mem/page_table.hh" -#include "sim/process.hh" -class TranslatingPort; - -#endif // FULL_SYSTEM - /** * The SimpleThread object provides a combination of the ThreadState * object and the ThreadContext interface. It implements the @@ -133,14 +124,13 @@ class SimpleThread : public ThreadState Decoder decoder; // constructor: initialize SimpleThread from given process structure -#if FULL_SYSTEM + // FS SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, TheISA::TLB *_itb, TheISA::TLB *_dtb, bool use_kernel_stats = true); -#else + // SE SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb); -#endif SimpleThread(); @@ -184,15 +174,12 @@ class SimpleThread : public ThreadState dtb->demapPage(vaddr, asn); } -#if FULL_SYSTEM void dumpFuncProfile(); Fault hwrei(); bool simPalCheck(int palFunc); -#endif - /******************************************* * ThreadContext interface functions. ******************************************/ @@ -207,7 +194,6 @@ class SimpleThread : public ThreadState System *getSystemPtr() { return system; } -#if FULL_SYSTEM PortProxy* getPhysProxy() { return physProxy; } /** Return a virtual port. This port cannot be cached locally in an object. @@ -215,7 +201,6 @@ class SimpleThread : public ThreadState * mean stale data. */ FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } -#endif Status status() const { return _status; } @@ -384,12 +369,10 @@ class SimpleThread : public ThreadState void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } -#if !FULL_SYSTEM void syscall(int64_t callnum) { process->syscall(callnum, tc); } -#endif }; diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index 334bdf4d4..c403667bf 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -56,7 +56,6 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) panic("Float reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); } -#if FULL_SYSTEM for (int i = 0; i < TheISA::NumMiscRegs; ++i) { TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); @@ -64,7 +63,6 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); } -#endif if (!(one->pcState() == two->pcState())) panic("PC state doesn't match."); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index d80d26e3d..261ace7cf 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -37,7 +37,6 @@ #include "arch/registers.hh" #include "arch/types.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" // @todo: Figure out a more architecture independent way to obtain the ITB and @@ -125,7 +124,6 @@ class ThreadContext virtual System *getSystemPtr() = 0; -#if FULL_SYSTEM virtual TheISA::Kernel::Statistics *getKernelStats() = 0; virtual PortProxy* getPhysProxy() = 0; @@ -139,11 +137,10 @@ class ThreadContext * tc ThreadContext for the virtual-to-physical translation */ virtual void initMemProxies(ThreadContext *tc) = 0; -#else + virtual SETranslatingPortProxy *getMemProxy() = 0; virtual Process *getProcessPtr() = 0; -#endif virtual Status status() const = 0; @@ -159,9 +156,7 @@ class ThreadContext /// Set the status to Halted. virtual void halt(int delay = 0) = 0; -#if FULL_SYSTEM virtual void dumpFuncProfile() = 0; -#endif virtual void takeOverFrom(ThreadContext *old_context) = 0; @@ -170,7 +165,6 @@ class ThreadContext virtual void serialize(std::ostream &os) = 0; virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; -#if FULL_SYSTEM virtual EndQuiesceEvent *getQuiesceEvent() = 0; // Not necessarily the best location for these... @@ -180,7 +174,6 @@ class ThreadContext virtual void profileClear() = 0; virtual void profileSample() = 0; -#endif virtual void copyArchRegs(ThreadContext *tc) = 0; @@ -242,7 +235,6 @@ class ThreadContext // Only really makes sense for old CPU model. Still could be useful though. virtual bool misspeculating() = 0; -#if !FULL_SYSTEM // Same with st cond failures. virtual Counter readFuncExeInst() = 0; @@ -252,7 +244,6 @@ class ThreadContext // 1 if the CPU has no more active threads (meaning it's OK to exit); // Used in syscall-emulation mode when a thread calls the exit syscall. virtual int exit() { return 1; }; -#endif /** function to compare two thread contexts (for debugging) */ static void compare(ThreadContext *one, ThreadContext *two); @@ -300,7 +291,6 @@ class ProxyThreadContext : public ThreadContext System *getSystemPtr() { return actualTC->getSystemPtr(); } -#if FULL_SYSTEM TheISA::Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } @@ -309,11 +299,10 @@ class ProxyThreadContext : public ThreadContext FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); } void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } -#else + SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } Process *getProcessPtr() { return actualTC->getProcessPtr(); } -#endif Status status() const { return actualTC->status(); } @@ -329,9 +318,7 @@ class ProxyThreadContext : public ThreadContext /// Set the status to Halted. void halt(int delay = 0) { actualTC->halt(); } -#if FULL_SYSTEM void dumpFuncProfile() { actualTC->dumpFuncProfile(); } -#endif void takeOverFrom(ThreadContext *oldContext) { actualTC->takeOverFrom(oldContext); } @@ -342,7 +329,6 @@ class ProxyThreadContext : public ThreadContext void unserialize(Checkpoint *cp, const std::string §ion) { actualTC->unserialize(cp, section); } -#if FULL_SYSTEM EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } Tick readLastActivate() { return actualTC->readLastActivate(); } @@ -350,7 +336,6 @@ class ProxyThreadContext : public ThreadContext void profileClear() { return actualTC->profileClear(); } void profileSample() { return actualTC->profileSample(); } -#endif // @todo: Do I need this? void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } @@ -418,12 +403,10 @@ class ProxyThreadContext : public ThreadContext // @todo: Fix this! bool misspeculating() { return actualTC->misspeculating(); } -#if !FULL_SYSTEM void syscall(int64_t callnum) { actualTC->syscall(callnum); } Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } -#endif }; #endif diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index 6c9bb99ea..574be7b6d 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -28,52 +28,37 @@ * Authors: Kevin Lim */ +#include "arch/kernel_stats.hh" #include "base/output.hh" #include "cpu/base.hh" #include "cpu/profile.hh" +#include "cpu/quiesce_event.hh" #include "cpu/thread_state.hh" +#include "mem/fs_translating_port_proxy.hh" +#include "mem/port.hh" #include "mem/port_proxy.hh" #include "mem/se_translating_port_proxy.hh" +#include "sim/full_system.hh" #include "sim/serialize.hh" #include "sim/system.hh" -#if FULL_SYSTEM -#include "arch/kernel_stats.hh" -#include "cpu/quiesce_event.hh" -#include "mem/fs_translating_port_proxy.hh" -#endif - -#if FULL_SYSTEM -ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid) -#else ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) -#endif : numInst(0), numLoad(0), _status(ThreadContext::Halted), baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0), -#if FULL_SYSTEM profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), - kernelStats(NULL), physProxy(NULL), virtProxy(NULL), -#else - proxy(NULL), process(_process), -#endif - funcExeInst(0), storeCondFailures(0) + kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL), + proxy(NULL), funcExeInst(0), storeCondFailures(0) { } ThreadState::~ThreadState() { -#if FULL_SYSTEM - if (physProxy != NULL) { + if (physProxy != NULL) delete physProxy; - } - if (virtProxy != NULL) { + if (virtProxy != NULL) delete virtProxy; - } -#else - if (proxy != NULL) { + if (proxy != NULL) delete proxy; - } -#endif } void @@ -83,14 +68,14 @@ ThreadState::serialize(std::ostream &os) // thread_num and cpu_id are deterministic from the config SERIALIZE_SCALAR(funcExeInst); -#if FULL_SYSTEM - Tick quiesceEndTick = 0; - if (quiesceEvent->scheduled()) - quiesceEndTick = quiesceEvent->when(); - SERIALIZE_SCALAR(quiesceEndTick); - if (kernelStats) - kernelStats->serialize(os); -#endif + if (FullSystem) { + Tick quiesceEndTick = 0; + if (quiesceEvent->scheduled()) + quiesceEndTick = quiesceEvent->when(); + SERIALIZE_SCALAR(quiesceEndTick); + if (kernelStats) + kernelStats->serialize(os); + } } void @@ -101,17 +86,16 @@ ThreadState::unserialize(Checkpoint *cp, const std::string §ion) // thread_num and cpu_id are deterministic from the config UNSERIALIZE_SCALAR(funcExeInst); -#if FULL_SYSTEM - Tick quiesceEndTick; - UNSERIALIZE_SCALAR(quiesceEndTick); - if (quiesceEndTick) - baseCpu->schedule(quiesceEvent, quiesceEndTick); - if (kernelStats) - kernelStats->unserialize(cp, section); -#endif + if (FullSystem) { + Tick quiesceEndTick; + UNSERIALIZE_SCALAR(quiesceEndTick); + if (quiesceEndTick) + baseCpu->schedule(quiesceEvent, quiesceEndTick); + if (kernelStats) + kernelStats->unserialize(cp, section); + } } -#if FULL_SYSTEM void ThreadState::initMemProxies(ThreadContext *tc) { @@ -139,7 +123,6 @@ ThreadState::profileSample() profile->sample(profileNode, profilePC); } -#else SETranslatingPortProxy * ThreadState::getMemProxy() { @@ -153,4 +136,3 @@ ThreadState::getMemProxy() return proxy; } -#endif diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index a007567c1..30bb64ed7 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -36,13 +36,9 @@ #include "cpu/base.hh" #include "cpu/profile.hh" #include "cpu/thread_context.hh" - -#if !FULL_SYSTEM #include "mem/mem_object.hh" #include "sim/process.hh" -#endif -#if FULL_SYSTEM class EndQuiesceEvent; class FunctionProfile; class ProfileNode; @@ -51,7 +47,6 @@ namespace TheISA { class Statistics; }; }; -#endif class Checkpoint; class PortProxy; @@ -67,11 +62,7 @@ class FSTranslatingPort; struct ThreadState { typedef ThreadContext::Status Status; -#if FULL_SYSTEM - ThreadState(BaseCPU *cpu, ThreadID _tid); -#else ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process); -#endif ~ThreadState(); @@ -93,7 +84,6 @@ struct ThreadState { Tick readLastSuspend() { return lastSuspend; } -#if FULL_SYSTEM /** * Initialise the physical and virtual port proxies and tie them to * the data port of the CPU. @@ -115,11 +105,10 @@ struct ThreadState { PortProxy* getPhysProxy() { return physProxy; } FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } -#else + Process *getProcessPtr() { return process; } SETranslatingPortProxy* getMemProxy(); -#endif /** Reads the number of instructions functionally executed and * committed. @@ -173,7 +162,6 @@ struct ThreadState { /** Last time suspend was called on this thread. */ Tick lastSuspend; -#if FULL_SYSTEM public: FunctionProfile *profile; ProfileNode *profileNode; @@ -181,7 +169,10 @@ struct ThreadState { EndQuiesceEvent *quiesceEvent; TheISA::Kernel::Statistics *kernelStats; + protected: + Process *process; + /** A port proxy outgoing only for functional accesses to physical * addresses.*/ PortProxy *physProxy; @@ -189,12 +180,8 @@ struct ThreadState { /** A translating port proxy, outgoing only, for functional * accesse to virtual addresses. */ FSTranslatingPortProxy* virtProxy; -#else SETranslatingPortProxy* proxy; - Process *process; -#endif - public: /* * number of executed instructions, for matching with syscall trace |