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-rw-r--r--src/cpu/o3/decode_impl.hh2
-rw-r--r--src/cpu/simple/timing.cc4
-rw-r--r--src/cpu/testers/directedtest/DirectedGenerator.cc2
-rw-r--r--src/cpu/testers/directedtest/DirectedGenerator.hh10
-rw-r--r--src/cpu/testers/directedtest/InvalidateGenerator.cc8
-rw-r--r--src/cpu/testers/directedtest/InvalidateGenerator.hh10
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.cc4
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.cc4
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.hh10
-rw-r--r--src/cpu/testers/networktest/networktest.cc8
-rw-r--r--src/cpu/timebuf.hh2
11 files changed, 32 insertions, 32 deletions
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 93d04a8f7..4ff82da8e 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -1,4 +1,4 @@
-/*
+/*
* Copyright (c) 2012, 2014 ARM Limited
* All rights reserved
*
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 441d5f896..97a280b17 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -817,7 +817,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
delete pkt;
PacketPtr big_pkt = send_state->bigPkt;
delete send_state;
-
+
SplitMainSenderState * main_send_state =
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
assert(main_send_state);
@@ -932,7 +932,7 @@ TimingSimpleCPU::DcachePort::recvReqRetry()
dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
assert(send_state);
PacketPtr big_pkt = send_state->bigPkt;
-
+
SplitMainSenderState * main_send_state =
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
assert(main_send_state);
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc b/src/cpu/testers/directedtest/DirectedGenerator.cc
index d69261cf0..5aee2a91c 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc
@@ -38,7 +38,7 @@ DirectedGenerator::DirectedGenerator(const Params *p)
m_directed_tester = NULL;
}
-void
+void
DirectedGenerator::setDirectedTester(RubyDirectedTester* directed_tester)
{
assert(m_directed_tester == NULL);
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh
index 422a0ddb6..2d033723d 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -34,19 +34,19 @@
#include "params/DirectedGenerator.hh"
#include "sim/sim_object.hh"
-class DirectedGenerator : public SimObject
+class DirectedGenerator : public SimObject
{
public:
typedef DirectedGeneratorParams Params;
DirectedGenerator(const Params *p);
-
+
virtual ~DirectedGenerator() {}
-
+
virtual bool initiate() = 0;
virtual void performCallback(uint32_t proc, Addr address) = 0;
-
+
void setDirectedTester(RubyDirectedTester* directed_tester);
-
+
protected:
int m_num_cpus;
MasterID masterId;
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index 61c3f5972..6f4877309 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -98,10 +98,10 @@ InvalidateGenerator::initiate()
}
}
-void
+void
InvalidateGenerator::performCallback(uint32_t proc, Addr address)
{
- assert(m_address == address);
+ assert(m_address == address);
if (m_status == InvalidateGeneratorStatus_Load_Pending) {
assert(m_active_read_node == proc);
@@ -128,8 +128,8 @@ InvalidateGenerator::performCallback(uint32_t proc, Addr address)
//
m_directed_tester->incrementCycleCompletions();
m_status = InvalidateGeneratorStatus_Load_Waiting;
- }
-
+ }
+
}
InvalidateGenerator *
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh
index 50db180e3..0e842bd3f 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.hh
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh
@@ -27,7 +27,7 @@
*/
//
-// This Directed Generator generates GETX requests for all nodes in the
+// This Directed Generator generates GETX requests for all nodes in the
// system. The GETX requests are generated one at a time in round-robin fashion
// 0...1...2...etc.
//
@@ -40,17 +40,17 @@
#include "mem/protocol/InvalidateGeneratorStatus.hh"
#include "params/InvalidateGenerator.hh"
-class InvalidateGenerator : public DirectedGenerator
+class InvalidateGenerator : public DirectedGenerator
{
public:
typedef InvalidateGeneratorParams Params;
InvalidateGenerator(const Params *p);
-
+
~InvalidateGenerator();
-
+
bool initiate();
void performCallback(uint32_t proc, Addr address);
-
+
private:
InvalidateGeneratorStatus m_status;
Addr m_address;
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc
index 70da23f03..b85031720 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -93,7 +93,7 @@ bool
RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt)
{
tester->hitCallback(id, pkt->getAddr());
-
+
//
// Now that the tester has completed, delete the packet, then return
//
@@ -118,7 +118,7 @@ RubyDirectedTester::hitCallback(NodeID proc, Addr addr)
proc,
addr);
- generator->performCallback(proc, addr);
+ generator->performCallback(proc, addr);
schedule(directedStartEvent, curTick());
}
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 2356fb47a..62d03fbf6 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -87,11 +87,11 @@ SeriesRequestGenerator::initiate()
}
}
-void
+void
SeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
{
assert(m_active_node == proc);
- assert(m_address == address);
+ assert(m_address == address);
assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
m_status = SeriesRequestGeneratorStatus_Thinking;
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
index 944a179cb..8c64a3dd0 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
@@ -27,7 +27,7 @@
*/
//
-// This Deterministic Generator generates GETX requests for all nodes in the
+// This Deterministic Generator generates GETX requests for all nodes in the
// system. The GETX requests are generated one at a time in round-robin fashion
// 0...1...2...etc.
//
@@ -40,17 +40,17 @@
#include "mem/protocol/SeriesRequestGeneratorStatus.hh"
#include "params/SeriesRequestGenerator.hh"
-class SeriesRequestGenerator : public DirectedGenerator
+class SeriesRequestGenerator : public DirectedGenerator
{
public:
typedef SeriesRequestGeneratorParams Params;
SeriesRequestGenerator(const Params *p);
-
+
~SeriesRequestGenerator();
-
+
bool initiate();
void performCallback(uint32_t proc, Addr address);
-
+
private:
SeriesRequestGeneratorStatus m_status;
Addr m_address;
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index e3103f6b6..79a563f28 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -207,14 +207,14 @@ NetworkTest::generatePkt()
// Modeling different coherence msg types over different msg classes.
//
- // networktest assumes the Network_test coherence protocol
+ // networktest assumes the Network_test coherence protocol
// which models three message classes/virtual networks.
// These are: request, forward, response.
// requests and forwards are "control" packets (typically 8 bytes),
// while responses are "data" packets (typically 72 bytes).
//
// Life of a packet from the tester into the network:
- // (1) This function generatePkt() generates packets of one of the
+ // (1) This function generatePkt() generates packets of one of the
// following 3 types (randomly) : ReadReq, INST_FETCH, WriteReq
// (2) mem/ruby/system/RubyPort.cc converts these to RubyRequestType_LD,
// RubyRequestType_IFETCH, RubyRequestType_ST respectively
@@ -222,13 +222,13 @@ NetworkTest::generatePkt()
// in the coherence protocol.
// (4) Network_test-cache.sm tags RubyRequestType:LD,
// RubyRequestType:IFETCH and RubyRequestType:ST as
- // Request, Forward, and Response events respectively;
+ // Request, Forward, and Response events respectively;
// and injects them into virtual networks 0, 1 and 2 respectively.
// It immediately calls back the sequencer.
// (5) The packet traverses the network (simple/garnet) and reaches its
// destination (Directory), and network stats are updated.
// (6) Network_test-dir.sm simply drops the packet.
- //
+ //
MemCmd::Command requestType;
Request *req = nullptr;
diff --git a/src/cpu/timebuf.hh b/src/cpu/timebuf.hh
index e93fe0e79..2cd965c04 100644
--- a/src/cpu/timebuf.hh
+++ b/src/cpu/timebuf.hh
@@ -138,7 +138,7 @@ class TimeBuffer
public:
TimeBuffer(int p, int f)
- : past(p), future(f), size(past + future + 1),
+ : past(p), future(f), size(past + future + 1),
data(new char[size * sizeof(T)]), index(size), base(0)
{
assert(past >= 0 && future >= 0);