summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/SConscript4
-rw-r--r--src/cpu/activity.cc1
-rw-r--r--src/cpu/base.cc1
-rw-r--r--src/cpu/base_dyn_inst_impl.hh2
-rw-r--r--src/cpu/exetrace.cc32
-rw-r--r--src/cpu/exetrace.hh6
-rw-r--r--src/cpu/inorder/cpu.cc4
-rw-r--r--src/cpu/inorder/first_stage.cc1
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc1
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.hh1
-rw-r--r--src/cpu/inorder/inorder_trace.cc3
-rw-r--r--src/cpu/inorder/pipeline_stage.cc5
-rw-r--r--src/cpu/inorder/reg_dep_map.cc1
-rw-r--r--src/cpu/inorder/resource.cc4
-rw-r--r--src/cpu/inorder/resource_pool.cc1
-rw-r--r--src/cpu/inorder/resource_sked.cc1
-rw-r--r--src/cpu/inorder/resources/agen_unit.cc1
-rw-r--r--src/cpu/inorder/resources/bpred_unit.cc3
-rw-r--r--src/cpu/inorder/resources/branch_predictor.cc2
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc8
-rw-r--r--src/cpu/inorder/resources/decode_unit.cc3
-rw-r--r--src/cpu/inorder/resources/execution_unit.cc2
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.cc2
-rw-r--r--src/cpu/inorder/resources/fetch_unit.cc5
-rw-r--r--src/cpu/inorder/resources/graduation_unit.cc1
-rw-r--r--src/cpu/inorder/resources/inst_buffer.cc2
-rw-r--r--src/cpu/inorder/resources/mult_div_unit.cc2
-rw-r--r--src/cpu/inorder/resources/use_def.cc2
-rw-r--r--src/cpu/inorder/thread_context.cc1
-rw-r--r--src/cpu/inteltrace.hh6
-rw-r--r--src/cpu/intr_control.cc1
-rw-r--r--src/cpu/nativetrace.cc1
-rw-r--r--src/cpu/o3/bpred_unit_impl.hh2
-rw-r--r--src/cpu/o3/commit_impl.hh4
-rw-r--r--src/cpu/o3/cpu.cc4
-rw-r--r--src/cpu/o3/decode_impl.hh2
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/o3/free_list.cc1
-rw-r--r--src/cpu/o3/free_list.hh2
-rw-r--r--src/cpu/o3/iew.hh1
-rw-r--r--src/cpu/o3/iew_impl.hh3
-rw-r--r--src/cpu/o3/inst_queue_impl.hh1
-rw-r--r--src/cpu/o3/lsq_impl.hh3
-rw-r--r--src/cpu/o3/lsq_unit.hh1
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rw-r--r--src/cpu/o3/mem_dep_unit.hh1
-rw-r--r--src/cpu/o3/mem_dep_unit_impl.hh1
-rw-r--r--src/cpu/o3/regfile.hh1
-rw-r--r--src/cpu/o3/rename_impl.hh2
-rw-r--r--src/cpu/o3/rename_map.cc1
-rw-r--r--src/cpu/o3/rob_impl.hh2
-rw-r--r--src/cpu/o3/scoreboard.cc1
-rw-r--r--src/cpu/o3/scoreboard.hh1
-rw-r--r--src/cpu/o3/store_set.cc1
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh1
-rw-r--r--src/cpu/pc_event.cc1
-rw-r--r--src/cpu/pred/2bit_local.cc1
-rw-r--r--src/cpu/pred/btb.cc1
-rw-r--r--src/cpu/quiesce_event.cc1
-rw-r--r--src/cpu/simple/atomic.cc2
-rw-r--r--src/cpu/simple/base.cc3
-rw-r--r--src/cpu/simple/timing.cc3
-rw-r--r--src/cpu/simple_thread.hh2
-rw-r--r--src/cpu/testers/directedtest/InvalidateGenerator.cc1
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.cc1
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.cc1
-rw-r--r--src/cpu/testers/memtest/memtest.cc1
-rw-r--r--src/cpu/testers/networktest/networktest.cc1
-rw-r--r--src/cpu/testers/rubytest/Check.cc1
-rw-r--r--src/cpu/testers/rubytest/CheckTable.cc1
-rw-r--r--src/cpu/testers/rubytest/RubyTester.cc1
-rw-r--r--src/cpu/thread_context.cc1
72 files changed, 149 insertions, 25 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 99308c2fb..fb7c86845 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -173,6 +173,10 @@ TraceFlag('IntrControl')
TraceFlag('PCEvent')
TraceFlag('Quiesce')
+CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
+ 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
+ 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
+ 'ExecTicks', 'ExecMicro', 'ExecMacro' ])
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc
index 84f88d594..13613cffc 100644
--- a/src/cpu/activity.cc
+++ b/src/cpu/activity.cc
@@ -32,6 +32,7 @@
#include "cpu/activity.hh"
#include "cpu/timebuf.hh"
+#include "debug/Activity.hh"
using namespace std;
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 1d249b274..1e25a5982 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -45,6 +45,7 @@
#include "cpu/cpuevent.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "params/BaseCPU.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index 688d5c66b..226291e1d 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -50,6 +50,8 @@
#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
+#include "debug/DynInst.hh"
+#include "debug/IQ.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index ea90ba7c2..a6450ffe3 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -41,6 +41,7 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecAll.hh"
#include "enums/OpClass.hh"
using namespace std;
@@ -59,22 +60,21 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
{
ostream &outs = Trace::output();
- if (IsOn(ExecTicks))
+ if (Debug::ExecTicks)
dumpTicks(outs);
outs << thread->getCpuPtr()->name() << " ";
- if (IsOn(ExecSpeculative))
+ if (Debug::ExecSpeculative)
outs << (misspeculating ? "-" : "+") << " ";
- if (IsOn(ExecThread))
+ if (Debug::ExecThread)
outs << "T" << thread->threadId() << " : ";
std::string sym_str;
Addr sym_addr;
Addr cur_pc = pc.instAddr();
- if (debugSymbolTable
- && IsOn(ExecSymbol)
+ if (debugSymbolTable && Debug::ExecSymbol
#if FULL_SYSTEM
&& !inUserMode(thread)
#endif
@@ -104,25 +104,25 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
if (ran) {
outs << " : ";
- if (IsOn(ExecOpClass)) {
+ if (Debug::ExecOpClass) {
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
}
- if (IsOn(ExecResult) && predicate == false) {
+ if (Debug::ExecResult && predicate == false) {
outs << "Predicated False";
}
- if (IsOn(ExecResult) && data_status != DataInvalid) {
+ if (Debug::ExecResult && data_status != DataInvalid) {
ccprintf(outs, " D=%#018x", data.as_int);
}
- if (IsOn(ExecEffAddr) && addr_valid)
+ if (Debug::ExecEffAddr && addr_valid)
outs << " A=0x" << hex << addr;
- if (IsOn(ExecFetchSeq) && fetch_seq_valid)
+ if (Debug::ExecFetchSeq && fetch_seq_valid)
outs << " FetchSeq=" << dec << fetch_seq;
- if (IsOn(ExecCPSeq) && cp_seq_valid)
+ if (Debug::ExecCPSeq && cp_seq_valid)
outs << " CPSeq=" << dec << cp_seq;
}
@@ -143,14 +143,14 @@ Trace::ExeTracerRecord::dump()
* finishes. Macroops then behave like regular instructions and don't
* complete/print when they fault.
*/
- if (IsOn(ExecMacro) && staticInst->isMicroop() &&
- ((IsOn(ExecMicro) &&
- macroStaticInst && staticInst->isFirstMicroop()) ||
- (!IsOn(ExecMicro) &&
+ if (Debug::ExecMacro && staticInst->isMicroop() &&
+ ((Debug::ExecMicro &&
+ macroStaticInst && staticInst->isFirstMicroop()) ||
+ (!Debug::ExecMicro &&
macroStaticInst && staticInst->isLastMicroop()))) {
traceInst(macroStaticInst, false);
}
- if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
+ if (Debug::ExecMicro || !staticInst->isMicroop()) {
traceInst(staticInst, true);
}
}
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 5dc65b48b..6d9f2a337 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -36,6 +36,8 @@
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecEnable.hh"
+#include "debug/ExecSpeculative.hh"
#include "params/ExeTracer.hh"
#include "sim/insttracer.hh"
@@ -72,13 +74,13 @@ class ExeTracer : public InstTracer
const StaticInstPtr staticInst, TheISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
- if (!IsOn(ExecEnable))
+ if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
return NULL;
- if (!IsOn(ExecSpeculative) && tc->misspeculating())
+ if (!Debug::ExecSpeculative && tc->misspeculating())
return NULL;
return new ExeTracerRecord(when, tc,
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index f7fff05d3..c27020671 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -47,6 +47,10 @@
#include "cpu/exetrace.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
+#include "debug/Activity.hh"
+#include "debug/InOrderCPU.hh"
+#include "debug/RefCount.hh"
+#include "debug/SkedCache.hh"
#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
#include "sim/process.hh"
diff --git a/src/cpu/inorder/first_stage.cc b/src/cpu/inorder/first_stage.cc
index bf57681a7..20fd9169f 100644
--- a/src/cpu/inorder/first_stage.cc
+++ b/src/cpu/inorder/first_stage.cc
@@ -34,6 +34,7 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/first_stage.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/InOrderStage.hh"
#include "params/InOrderTrace.hh"
using namespace std;
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 90134f533..30a69bbb5 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -41,6 +41,7 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/exetrace.hh"
+#include "debug/InOrderDynInst.hh"
#include "mem/request.hh"
using namespace std;
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 1fbc476e8..033726df9 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -57,6 +57,7 @@
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/InOrderDynInst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
diff --git a/src/cpu/inorder/inorder_trace.cc b/src/cpu/inorder/inorder_trace.cc
index 8d40451bd..8edb5b1cc 100644
--- a/src/cpu/inorder/inorder_trace.cc
+++ b/src/cpu/inorder/inorder_trace.cc
@@ -37,6 +37,7 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/ExecEnable.hh"
#include "params/InOrderTrace.hh"
using namespace std;
@@ -64,7 +65,7 @@ InOrderTraceRecord *
InOrderTrace::getInstRecord(unsigned num_stages, bool stage_tracing,
ThreadContext *tc)
{
- if (!IsOn(ExecEnable))
+ if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index b9e21e20f..fe97fb8f4 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -34,6 +34,11 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_stage.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Activity.hh"
+#include "debug/InOrderStage.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/Resource.hh"
+#include "debug/ThreadModel.hh"
using namespace std;
using namespace ThePipeline;
diff --git a/src/cpu/inorder/reg_dep_map.cc b/src/cpu/inorder/reg_dep_map.cc
index 8eb7a3111..cf66f42c2 100644
--- a/src/cpu/inorder/reg_dep_map.cc
+++ b/src/cpu/inorder/reg_dep_map.cc
@@ -35,6 +35,7 @@
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/reg_dep_map.hh"
+#include "debug/RegDepMap.hh"
using namespace std;
using namespace TheISA;
diff --git a/src/cpu/inorder/resource.cc b/src/cpu/inorder/resource.cc
index b72dbd14f..bdcfbde7d 100644
--- a/src/cpu/inorder/resource.cc
+++ b/src/cpu/inorder/resource.cc
@@ -35,6 +35,10 @@
#include "base/str.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource.hh"
+#include "debug/RefCount.hh"
+#include "debug/ResReqCount.hh"
+#include "debug/Resource.hh"
+
using namespace std;
Resource::Resource(string res_name, int res_id, int res_width,
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc
index a9eb742f4..536a3b53c 100644
--- a/src/cpu/inorder/resource_pool.cc
+++ b/src/cpu/inorder/resource_pool.cc
@@ -34,6 +34,7 @@
#include "cpu/inorder/resources/resource_list.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;
diff --git a/src/cpu/inorder/resource_sked.cc b/src/cpu/inorder/resource_sked.cc
index 443500870..96b4f84b6 100644
--- a/src/cpu/inorder/resource_sked.cc
+++ b/src/cpu/inorder/resource_sked.cc
@@ -35,6 +35,7 @@
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_sked.hh"
+#include "debug/SkedCache.hh"
using namespace std;
using namespace ThePipeline;
diff --git a/src/cpu/inorder/resources/agen_unit.cc b/src/cpu/inorder/resources/agen_unit.cc
index 3e26c4da3..d87ca364d 100644
--- a/src/cpu/inorder/resources/agen_unit.cc
+++ b/src/cpu/inorder/resources/agen_unit.cc
@@ -30,6 +30,7 @@
*/
#include "cpu/inorder/resources/agen_unit.hh"
+#include "debug/InOrderAGEN.hh"
AGENUnit::AGENUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu,
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc
index 9e15a4fee..127843e96 100644
--- a/src/cpu/inorder/resources/bpred_unit.cc
+++ b/src/cpu/inorder/resources/bpred_unit.cc
@@ -33,9 +33,10 @@
#include "arch/utility.hh"
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/bpred_unit.hh"
+#include "debug/InOrderBPred.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;
diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc
index 4b8205070..829ae4346 100644
--- a/src/cpu/inorder/resources/branch_predictor.cc
+++ b/src/cpu/inorder/resources/branch_predictor.cc
@@ -31,6 +31,8 @@
#include "config/the_isa.hh"
#include "cpu/inorder/resources/branch_predictor.hh"
+#include "debug/InOrderBPred.hh"
+#include "debug/InOrderStage.hh"
using namespace std;
using namespace TheISA;
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index ce4c538da..620ba06c1 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -41,6 +41,14 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Activity.hh"
+#include "debug/AddrDep.hh"
+#include "debug/InOrderCachePort.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/InOrderTLB.hh"
+#include "debug/LLSC.hh"
+#include "debug/RefCount.hh"
+#include "debug/ThreadModel.hh"
#include "mem/request.hh"
using namespace std;
diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index 71d33ab90..559becaaf 100644
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -31,6 +31,9 @@
#include "config/the_isa.hh"
#include "cpu/inorder/resources/decode_unit.hh"
+#include "debug/InOrderDecode.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/Resource.hh"
using namespace TheISA;
using namespace ThePipeline;
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index 2ec340749..7ed9aed9a 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -35,6 +35,8 @@
#include "cpu/inorder/resources/execution_unit.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/InOrderExecute.hh"
+#include "debug/InOrderStall.hh"
using namespace std;
using namespace ThePipeline;
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 8d9187c7a..df8c6de63 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -32,6 +32,8 @@
#include "config/the_isa.hh"
#include "cpu/inorder/resources/fetch_seq_unit.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/InOrderFetchSeq.hh"
+#include "debug/InOrderStall.hh"
using namespace std;
using namespace TheISA;
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index 899fa8c08..692f78c7b 100644
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -42,6 +42,11 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "debug/Activity.hh"
+#include "debug/InOrderCachePort.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/RefCount.hh"
+#include "debug/ThreadModel.hh"
#include "mem/request.hh"
using namespace std;
diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc
index edc2fb3ff..a7530345e 100644
--- a/src/cpu/inorder/resources/graduation_unit.cc
+++ b/src/cpu/inorder/resources/graduation_unit.cc
@@ -30,6 +30,7 @@
*/
#include "cpu/inorder/resources/graduation_unit.hh"
+#include "debug/InOrderGraduation.hh"
using namespace ThePipeline;
diff --git a/src/cpu/inorder/resources/inst_buffer.cc b/src/cpu/inorder/resources/inst_buffer.cc
index e0405879b..d64eb79f1 100644
--- a/src/cpu/inorder/resources/inst_buffer.cc
+++ b/src/cpu/inorder/resources/inst_buffer.cc
@@ -37,6 +37,8 @@
#include "cpu/inorder/resources/inst_buffer.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
+#include "debug/InOrderInstBuffer.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace TheISA;
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index 8fbfc231e..49df901e3 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -36,6 +36,8 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh"
#include "cpu/op_class.hh"
+#include "debug/InOrderMDU.hh"
+#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index 8a00ab704..beb8d4dde 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -37,6 +37,8 @@
#include "cpu/inorder/resources/use_def.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
+#include "debug/InOrderStall.hh"
+#include "debug/InOrderUseDef.hh"
using namespace std;
using namespace TheISA;
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index 636bcee22..a217630a9 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -33,6 +33,7 @@
#include "config/the_isa.hh"
#include "cpu/inorder/thread_context.hh"
#include "cpu/exetrace.hh"
+#include "debug/InOrderCPU.hh"
using namespace TheISA;
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index 5083318ad..dbb6300ac 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -35,6 +35,8 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "debug/ExecEnable.hh"
+#include "debug/ExecSpeculative.hh"
#include "params/IntelTrace.hh"
#include "sim/insttracer.hh"
@@ -68,13 +70,13 @@ class IntelTrace : public InstTracer
const StaticInstPtr staticInst, TheISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
- if (!IsOn(ExecEnable))
+ if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
return NULL;
- if (!IsOn(ExecSpeculative) && tc->misspeculating())
+ if (!Debug::ExecSpeculative && tc->misspeculating())
return NULL;
return new IntelTraceRecord(when, tc,
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index 085dbe9ac..8f3808889 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -36,6 +36,7 @@
#include "cpu/base.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
+#include "debug/IntrControl.hh"
#include "sim/sim_object.hh"
using namespace std;
diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc
index 9660c0e13..1f5132288 100644
--- a/src/cpu/nativetrace.cc
+++ b/src/cpu/nativetrace.cc
@@ -31,6 +31,7 @@
#include "base/socket.hh"
#include "cpu/nativetrace.hh"
#include "cpu/static_inst.hh"
+#include "debug/GDBMisc.hh"
#include "params/NativeTrace.hh"
using namespace std;
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index 44e6f4230..e0292e232 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -34,9 +34,9 @@
#include "arch/types.hh"
#include "arch/utility.hh"
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/o3/bpred_unit.hh"
+#include "debug/Fetch.hh"
#include "params/DerivO3CPU.hh"
template<class Impl>
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 2512ab1f6..aa72c0750 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -54,6 +54,10 @@
#include "cpu/o3/thread_state.hh"
#include "cpu/exetrace.hh"
#include "cpu/timebuf.hh"
+#include "debug/Activity.hh"
+#include "debug/Commit.hh"
+#include "debug/CommitRate.hh"
+#include "debug/ExecFaulting.hh"
#include "params/DerivO3CPU.hh"
#include "sim/faults.hh"
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 565c68f7a..b19e4f460 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -40,6 +40,9 @@
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
+#include "debug/Activity.hh"
+#include "debug/O3CPU.hh"
+#include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh"
#include "sim/core.hh"
#include "sim/stat_control.hh"
@@ -57,6 +60,7 @@
#if THE_ISA == ALPHA_ISA
#include "arch/alpha/osfpal.hh"
+#include "debug/Activity.hh"
#endif
class BaseCPUParams;
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index cee597716..010dbfa5a 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -34,6 +34,8 @@
#include "config/the_isa.hh"
#include "cpu/o3/decode.hh"
#include "cpu/inst_seq.hh"
+#include "debug/Activity.hh"
+#include "debug/Decode.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 806cf7916..0f7d908d1 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -52,6 +52,8 @@
#include "cpu/checker/cpu.hh"
#include "cpu/o3/fetch.hh"
#include "cpu/exetrace.hh"
+#include "debug/Activity.hh"
+#include "debug/Fetch.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/DerivO3CPU.hh"
diff --git a/src/cpu/o3/free_list.cc b/src/cpu/o3/free_list.cc
index 88020a0a2..4224d0e41 100644
--- a/src/cpu/o3/free_list.cc
+++ b/src/cpu/o3/free_list.cc
@@ -30,6 +30,7 @@
#include "base/trace.hh"
#include "cpu/o3/free_list.hh"
+#include "debug/FreeList.hh"
SimpleFreeList::SimpleFreeList(ThreadID activeThreads,
unsigned _numLogicalIntRegs,
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index 96289f641..fec076097 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -37,9 +37,9 @@
#include "arch/registers.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
+#include "debug/FreeList.hh"
/**
* FreeList class that simply holds the list of free integer and floating
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 75f6df7ab..8ebbfb2e6 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -52,6 +52,7 @@
#include "cpu/o3/lsq.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/timebuf.hh"
+#include "debug/IEW.hh"
class DerivO3CPUParams;
class FUPool;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index e76a6bc3d..2569dbb34 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -51,6 +51,9 @@
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/iew.hh"
#include "cpu/timebuf.hh"
+#include "debug/Activity.hh"
+#include "debug/Decode.hh"
+#include "debug/IEW.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 1a211af7a..bac9e2ec6 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -46,6 +46,7 @@
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
+#include "debug/IQ.hh"
#include "enums/OpClass.hh"
#include "params/DerivO3CPU.hh"
#include "sim/core.hh"
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index ddfc63754..8dd240557 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -33,6 +33,9 @@
#include <string>
#include "cpu/o3/lsq.hh"
+#include "debug/Fetch.hh"
+#include "debug/LSQ.hh"
+#include "debug/Writeback.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 2d9a6ce56..be9c91a23 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -45,6 +45,7 @@
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
+#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 6a366d056..aa86c3d14 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -47,6 +47,9 @@
#include "config/use_checker.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/o3/lsq_unit.hh"
+#include "debug/Activity.hh"
+#include "debug/IEW.hh"
+#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index a9560f446..5d6f0a159 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -38,6 +38,7 @@
#include "base/refcnt.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
+#include "debug/MemDepUnit.hh"
struct SNHash {
size_t operator() (const InstSeqNum &seq_num) const {
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index fdea84ed5..6f3c922a7 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -32,6 +32,7 @@
#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/mem_dep_unit.hh"
+#include "debug/MemDepUnit.hh"
#include "params/DerivO3CPU.hh"
template <class MemDepPred, class Impl>
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index e252fa362..d04f45cc0 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -40,6 +40,7 @@
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
+#include "debug/IEW.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 1f34b7255..7d20cac30 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -48,6 +48,8 @@
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/o3/rename.hh"
+#include "debug/Activity.hh"
+#include "debug/Rename.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index e6649ce3e..cc5044c20 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -31,6 +31,7 @@
#include <vector>
#include "cpu/o3/rename_map.hh"
+#include "debug/Rename.hh"
using namespace std;
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index d9d1daded..dcde54a54 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -33,6 +33,8 @@
#include "config/full_system.hh"
#include "cpu/o3/rob.hh"
+#include "debug/Fetch.hh"
+#include "debug/ROB.hh"
using namespace std;
diff --git a/src/cpu/o3/scoreboard.cc b/src/cpu/o3/scoreboard.cc
index 7fb47f3c7..83a88f213 100644
--- a/src/cpu/o3/scoreboard.cc
+++ b/src/cpu/o3/scoreboard.cc
@@ -31,6 +31,7 @@
#include "config/the_isa.hh"
#include "cpu/o3/scoreboard.hh"
+#include "debug/Scoreboard.hh"
Scoreboard::Scoreboard(unsigned activeThreads,
unsigned _numLogicalIntRegs,
diff --git a/src/cpu/o3/scoreboard.hh b/src/cpu/o3/scoreboard.hh
index 4789e2181..8a49d7a3a 100644
--- a/src/cpu/o3/scoreboard.hh
+++ b/src/cpu/o3/scoreboard.hh
@@ -37,7 +37,6 @@
#include <vector>
#include "base/trace.hh"
-#include "base/traceflags.hh"
#include "cpu/o3/comm.hh"
/**
diff --git a/src/cpu/o3/store_set.cc b/src/cpu/o3/store_set.cc
index df4ee00ad..fc87c417e 100644
--- a/src/cpu/o3/store_set.cc
+++ b/src/cpu/o3/store_set.cc
@@ -32,6 +32,7 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/o3/store_set.hh"
+#include "debug/StoreSet.hh"
StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
: SSITSize(_SSIT_size), LFSTSize(_LFST_size)
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index b179ad50e..c3b7d2248 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -45,6 +45,7 @@
#include "config/the_isa.hh"
#include "cpu/o3/thread_context.hh"
#include "cpu/quiesce_event.hh"
+#include "debug/O3CPU.hh"
#if FULL_SYSTEM
template <class Impl>
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index 0ac5102bb..f9955d014 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -40,6 +40,7 @@
#include "cpu/base.hh"
#include "cpu/pc_event.hh"
#include "cpu/thread_context.hh"
+#include "debug/PCEvent.hh"
#include "sim/core.hh"
#include "sim/system.hh"
diff --git a/src/cpu/pred/2bit_local.cc b/src/cpu/pred/2bit_local.cc
index a70d65296..dc8cf50b7 100644
--- a/src/cpu/pred/2bit_local.cc
+++ b/src/cpu/pred/2bit_local.cc
@@ -32,6 +32,7 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/pred/2bit_local.hh"
+#include "debug/Fetch.hh"
LocalBP::LocalBP(unsigned _localPredictorSize,
unsigned _localCtrBits,
diff --git a/src/cpu/pred/btb.cc b/src/cpu/pred/btb.cc
index e87cc6dc2..393e52ccf 100644
--- a/src/cpu/pred/btb.cc
+++ b/src/cpu/pred/btb.cc
@@ -31,6 +31,7 @@
#include "base/intmath.hh"
#include "base/trace.hh"
#include "cpu/pred/btb.hh"
+#include "debug/Fetch.hh"
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
diff --git a/src/cpu/quiesce_event.cc b/src/cpu/quiesce_event.cc
index 79068985b..d5c3fe240 100644
--- a/src/cpu/quiesce_event.cc
+++ b/src/cpu/quiesce_event.cc
@@ -31,6 +31,7 @@
#include "cpu/base.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/thread_context.hh"
+#include "debug/Quiesce.hh"
EndQuiesceEvent::EndQuiesceEvent(ThreadContext *_tc)
: tc(_tc)
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index c5730e137..f3d79dd2b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -35,6 +35,8 @@
#include "config/the_isa.hh"
#include "cpu/simple/atomic.hh"
#include "cpu/exetrace.hh"
+#include "debug/ExecFaulting.hh"
+#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/AtomicSimpleCPU.hh"
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 464520309..699e78764 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -60,6 +60,9 @@
#include "cpu/smt.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "debug/Decode.hh"
+#include "debug/Fetch.hh"
+#include "debug/Quiesce.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/BaseSimpleCPU.hh"
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 52d4b06d2..c992cb0b5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -47,6 +47,9 @@
#include "config/the_isa.hh"
#include "cpu/simple/timing.hh"
#include "cpu/exetrace.hh"
+#include "debug/Config.hh"
+#include "debug/ExecFaulting.hh"
+#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/TimingSimpleCPU.hh"
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 5420519e4..dcf0663e2 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -42,6 +42,8 @@
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+#include "debug/FloatRegs.hh"
+#include "debug/IntRegs.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index 3b5aa55e5..902c6cc15 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -30,6 +30,7 @@
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/InvalidateGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
+#include "debug/DirectedTest.hh"
InvalidateGenerator::InvalidateGenerator(const Params *p)
: DirectedGenerator(p)
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc
index cc7c84dd3..b85cf781c 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -29,6 +29,7 @@
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
+#include "debug/DirectedTest.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
#include "sim/sim_exit.hh"
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 5b6395f93..43e140178 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -30,6 +30,7 @@
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
+#include "debug/DirectedTest.hh"
SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
: DirectedGenerator(p)
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 758a25ea2..d75bcb845 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -39,6 +39,7 @@
#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/testers/memtest/memtest.hh"
+#include "debug/MemTest.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 1c1555743..dcc47675b 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -37,6 +37,7 @@
#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/testers/networktest/networktest.hh"
+#include "debug/NetworkTest.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index c0007cd98..164fb56e1 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -28,6 +28,7 @@
*/
#include "cpu/testers/rubytest/Check.hh"
+#include "debug/RubyTest.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"
diff --git a/src/cpu/testers/rubytest/CheckTable.cc b/src/cpu/testers/rubytest/CheckTable.cc
index c2aa68a53..f3335b48c 100644
--- a/src/cpu/testers/rubytest/CheckTable.cc
+++ b/src/cpu/testers/rubytest/CheckTable.cc
@@ -30,6 +30,7 @@
#include "base/intmath.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "cpu/testers/rubytest/CheckTable.hh"
+#include "debug/RubyTest.hh"
CheckTable::CheckTable(int _num_cpu_sequencers, RubyTester* _tester)
: m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester)
diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc
index 024cb741e..5040d9fae 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -30,6 +30,7 @@
#include "base/misc.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
+#include "debug/RubyTest.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index c4960ea30..334bdf4d4 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -32,6 +32,7 @@
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
+#include "debug/Context.hh"
void
ThreadContext::compare(ThreadContext *one, ThreadContext *two)