diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/FuncUnit.py | 6 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 7 | ||||
| -rw-r--r-- | src/cpu/op_class.cc | 2 |
3 files changed, 8 insertions, 7 deletions
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index 541bdbd83..ad2d1b87b 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -29,15 +29,15 @@ from m5.SimObject import SimObject from m5.params import * -class OpType(Enum): - vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', +class OpClass(Enum): + vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] class OpDesc(SimObject): type = 'OpDesc' issueLat = Param.Int(1, "cycles until another can be issued") - opClass = Param.OpType("type of operation") + opClass = Param.OpClass("type of operation") opLat = Param.Int(1, "cycles until result is available") class FUDesc(SimObject): diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 0d7403023..ff4617fcc 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -29,6 +29,9 @@ * Korey Sewell */ +#include <algorithm> +#include <cstring> + #include "config/use_checker.hh" #include "arch/isa_traits.hh" @@ -48,8 +51,6 @@ #include "sim/system.hh" #endif // FULL_SYSTEM -#include <algorithm> - template<class Impl> void DefaultFetch<Impl>::IcachePort::setPeer(Port *port) @@ -374,7 +375,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) return; } - memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); + memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); cacheDataValid[tid] = true; if (!drainPending) { diff --git a/src/cpu/op_class.cc b/src/cpu/op_class.cc index f7ef49c0f..02cb4a08a 100644 --- a/src/cpu/op_class.cc +++ b/src/cpu/op_class.cc @@ -34,7 +34,7 @@ const char * opClassStrings[Num_OpClasses] = { - "(null)", + "No_OpClass", "IntAlu", "IntMult", "IntDiv", |