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-rw-r--r--src/cpu/base.hh8
-rw-r--r--src/cpu/checker/cpu.hh83
-rw-r--r--src/cpu/minor/cpu.hh28
-rw-r--r--src/cpu/minor/func_unit.cc2
-rw-r--r--src/cpu/minor/pipeline.hh2
-rw-r--r--src/cpu/o3/cpu.hh34
-rw-r--r--src/cpu/pred/bpred_unit.hh2
-rw-r--r--src/cpu/simple/atomic.hh23
-rw-r--r--src/cpu/simple/base.hh14
-rw-r--r--src/cpu/simple/timing.hh21
-rw-r--r--src/cpu/testers/traffic_gen/traffic_gen.hh10
11 files changed, 116 insertions, 111 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 554c4d754..87f27acca 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -189,7 +189,7 @@ class BaseCPU : public MemObject
* @return a reference to the port with the given name
*/
BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
/** Get cpu task id */
uint32_t taskId() const { return _taskId; }
@@ -303,9 +303,9 @@ class BaseCPU : public MemObject
BaseCPU(Params *params, bool is_checker = false);
virtual ~BaseCPU();
- virtual void init();
- virtual void startup();
- virtual void regStats();
+ void init() override;
+ void startup() override;
+ void regStats() override;
void regProbePoints() override;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 14c0ad0b2..c77f964c0 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -98,7 +98,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
/** id attached to all issued requests */
MasterID masterId;
public:
- virtual void init();
+ void init() override;
typedef CheckerCPUParams Params;
CheckerCPU(Params *p);
@@ -110,7 +110,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
void setDcachePort(MasterPort *dcache_port);
- MasterPort &getDataPort()
+ MasterPort &getDataPort() override
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -118,7 +118,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
return *dcachePort;
}
- MasterPort &getInstPort()
+ MasterPort &getInstPort() override
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -175,12 +175,12 @@ class CheckerCPU : public BaseCPU, public ExecContext
TheISA::TLB* getITBPtr() { return itb; }
TheISA::TLB* getDTBPtr() { return dtb; }
- virtual Counter totalInsts() const
+ virtual Counter totalInsts() const override
{
return 0;
}
- virtual Counter totalOps() const
+ virtual Counter totalOps() const override
{
return 0;
}
@@ -194,8 +194,10 @@ class CheckerCPU : public BaseCPU, public ExecContext
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
- void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
- Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
+ void setEA(Addr EA) override
+ { panic("CheckerCPU::setEA() not implemented\n"); }
+ Addr getEA() const override
+ { panic("CheckerCPU::getEA() not implemented\n"); }
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
@@ -208,24 +210,25 @@ class CheckerCPU : public BaseCPU, public ExecContext
// storage (which is pretty hard to imagine they would have reason
// to do).
- IntReg readIntRegOperand(const StaticInst *si, int idx)
+ IntReg readIntRegOperand(const StaticInst *si, int idx) override
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si,
+ int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatRegBits(reg_idx);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx)
+ CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
return thread->readCCReg(reg_idx);
@@ -239,13 +242,15 @@ class CheckerCPU : public BaseCPU, public ExecContext
result.push(instRes);
}
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+ void setIntRegOperand(const StaticInst *si, int idx,
+ IntReg val) override
{
thread->setIntReg(si->destRegIdx(idx), val);
setResult<uint64_t>(val);
}
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx,
+ FloatReg val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatReg(reg_idx, val);
@@ -253,28 +258,28 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val)
+ FloatRegBits val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatRegBits(reg_idx, val);
setResult<uint64_t>(val);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
thread->setCCReg(reg_idx, val);
setResult<uint64_t>(val);
}
- bool readPredicate() { return thread->readPredicate(); }
- void setPredicate(bool val)
+ bool readPredicate() override { return thread->readPredicate(); }
+ void setPredicate(bool val) override
{
thread->setPredicate(val);
}
- TheISA::PCState pcState() const { return thread->pcState(); }
- void pcState(const TheISA::PCState &val)
+ TheISA::PCState pcState() const override { return thread->pcState(); }
+ void pcState(const TheISA::PCState &val) override
{
DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
val, thread->pcState());
@@ -290,7 +295,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
return thread->readMiscRegNoEffect(misc_reg);
}
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscReg(int misc_reg) override
{
return thread->readMiscReg(misc_reg);
}
@@ -302,21 +307,21 @@ class CheckerCPU : public BaseCPU, public ExecContext
return thread->setMiscRegNoEffect(misc_reg, val);
}
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val) override
{
DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
miscRegIdxs.push(misc_reg);
return thread->setMiscReg(misc_reg, val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->readMiscReg(reg_idx);
}
- void setMiscRegOperand(
- const StaticInst *si, int idx, const MiscReg &val)
+ void setMiscRegOperand(const StaticInst *si, int idx,
+ const MiscReg &val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
return this->setMiscReg(reg_idx, val);
@@ -343,18 +348,20 @@ class CheckerCPU : public BaseCPU, public ExecContext
newPCState = val;
}
- void demapPage(Addr vaddr, uint64_t asn)
+ void demapPage(Addr vaddr, uint64_t asn) override
{
this->itb->demapPage(vaddr, asn);
this->dtb->demapPage(vaddr, asn);
}
// monitor/mwait funtions
- virtual void armMonitor(Addr address) { BaseCPU::armMonitor(0, address); }
- bool mwait(PacketPtr pkt) { return BaseCPU::mwait(0, pkt); }
- void mwaitAtomic(ThreadContext *tc)
+ void armMonitor(Addr address) override
+ { BaseCPU::armMonitor(0, address); }
+ bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
+ void mwaitAtomic(ThreadContext *tc) override
{ return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
- AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(0); }
+ AddressMonitor *getAddrMonitor() override
+ { return BaseCPU::getCpuAddrMonitor(0); }
void demapInstPage(Addr vaddr, uint64_t asn)
{
@@ -366,24 +373,26 @@ class CheckerCPU : public BaseCPU, public ExecContext
this->dtb->demapPage(vaddr, asn);
}
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size,
+ unsigned flags) override;
Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Addr addr, unsigned flags, uint64_t *res) override;
- unsigned int readStCondFailures() const {
+ unsigned int readStCondFailures() const override {
return thread->readStCondFailures();
}
- void setStCondFailures(unsigned int sc_failures)
+ void setStCondFailures(unsigned int sc_failures) override
{}
/////////////////////////////////////////////////////
- Fault hwrei() { return thread->hwrei(); }
- bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
+ Fault hwrei() override { return thread->hwrei(); }
+ bool simPalCheck(int palFunc) override
+ { return thread->simPalCheck(palFunc); }
void wakeup(ThreadID tid) override { }
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
- void syscall(int64_t callnum) { }
+ void syscall(int64_t callnum) override { }
void handleError()
{
@@ -396,7 +405,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
void dumpAndExit();
- ThreadContext *tcBase() { return tc; }
+ ThreadContext *tcBase() override { return tc; }
SimpleThread *threadBase() { return thread; }
Result unverifiedResult;
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 5bfc3b29f..82dac6aa9 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -114,10 +114,10 @@ class MinorCPU : public BaseCPU
protected:
/** Return a reference to the data port. */
- MasterPort &getDataPort();
+ MasterPort &getDataPort() override;
/** Return a reference to the instruction port. */
- MasterPort &getInstPort();
+ MasterPort &getInstPort() override;
public:
MinorCPU(MinorCPUParams *params);
@@ -126,8 +126,8 @@ class MinorCPU : public BaseCPU
public:
/** Starting, waking and initialisation */
- void init();
- void startup();
+ void init() override;
+ void startup() override;
void wakeup(ThreadID tid) override;
Addr dbg_vtophys(Addr addr);
@@ -136,18 +136,18 @@ class MinorCPU : public BaseCPU
Minor::MinorStats stats;
/** Stats interface from SimObject (by way of BaseCPU) */
- void regStats();
+ void regStats() override;
/** Simple inst count interface from BaseCPU */
- Counter totalInsts() const;
- Counter totalOps() const;
+ Counter totalInsts() const override;
+ Counter totalOps() const override;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
/** Serialize pipeline data */
- void serialize(CheckpointOut &cp) const;
- void unserialize(CheckpointIn &cp);
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Drain interface */
DrainState drain() override;
@@ -155,15 +155,15 @@ class MinorCPU : public BaseCPU
/** Signal from Pipeline that MinorCPU should signal that a drain
* is complete and set its drainState */
void signalDrainDone();
- void memWriteback();
+ void memWriteback() override;
/** Switching interface from BaseCPU */
- void switchOut();
- void takeOverFrom(BaseCPU *old_cpu);
+ void switchOut() override;
+ void takeOverFrom(BaseCPU *old_cpu) override;
/** Thread activation interface from BaseCPU. */
- void activateContext(ThreadID thread_id);
- void suspendContext(ThreadID thread_id);
+ void activateContext(ThreadID thread_id) override;
+ void suspendContext(ThreadID thread_id) override;
/** Interface for stages to signal that they have become active after
* a callback or eventq event where the pipeline itself may have
diff --git a/src/cpu/minor/func_unit.cc b/src/cpu/minor/func_unit.cc
index 65dd1eefc..aeee5cc44 100644
--- a/src/cpu/minor/func_unit.cc
+++ b/src/cpu/minor/func_unit.cc
@@ -223,7 +223,7 @@ FUPipeline::findTiming(const StaticInstPtr &inst)
"Found extra timing match (pattern %d '%s')"
" %s %16x (type %s)\n",
i, timing.description, inst->disassemble(0), mach_inst,
- typeid(*inst).name());
+ typeid(inst).name());
return &timing;
}
diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh
index 213def58e..2e1aa9921 100644
--- a/src/cpu/minor/pipeline.hh
+++ b/src/cpu/minor/pipeline.hh
@@ -124,7 +124,7 @@ class Pipeline : public Ticked
/** A custom evaluate allows report in the right place (between
* stages and pipeline advance) */
- void evaluate();
+ void evaluate() override;
void countCycles(Cycles delta) override
{
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index bed61234a..09177d404 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -265,13 +265,13 @@ class FullO3CPU : public BaseO3CPU
~FullO3CPU();
/** Registers statistics. */
- void regStats();
+ void regStats() override;
ProbePointArg<PacketPtr> *ppInstAccessComplete;
ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
/** Register probe points. */
- void regProbePoints();
+ void regProbePoints() override;
void demapPage(Addr vaddr, uint64_t asn)
{
@@ -295,9 +295,9 @@ class FullO3CPU : public BaseO3CPU
void tick();
/** Initialize the CPU */
- void init();
+ void init() override;
- void startup();
+ void startup() override;
/** Returns the Number of Active Threads in the CPU */
int numActiveThreads()
@@ -316,21 +316,21 @@ class FullO3CPU : public BaseO3CPU
void removeThread(ThreadID tid);
/** Count the Total Instructions Committed in the CPU. */
- virtual Counter totalInsts() const;
+ Counter totalInsts() const override;
/** Count the Total Ops (including micro ops) committed in the CPU. */
- virtual Counter totalOps() const;
+ Counter totalOps() const override;
/** Add Thread to Active Threads List. */
- void activateContext(ThreadID tid);
+ void activateContext(ThreadID tid) override;
/** Remove Thread from Active Threads List */
- void suspendContext(ThreadID tid);
+ void suspendContext(ThreadID tid) override;
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
- void haltContext(ThreadID tid);
+ void haltContext(ThreadID tid) override;
/** Update The Order In Which We Process Threads. */
void updateThreadPriority();
@@ -364,12 +364,12 @@ class FullO3CPU : public BaseO3CPU
void commitDrained(ThreadID tid);
/** Switches out this CPU. */
- virtual void switchOut();
+ void switchOut() override;
/** Takes over from another CPU. */
- virtual void takeOverFrom(BaseCPU *oldCPU);
+ void takeOverFrom(BaseCPU *oldCPU) override;
- void verifyMemoryMode() const;
+ void verifyMemoryMode() const override;
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq()
@@ -392,12 +392,6 @@ class FullO3CPU : public BaseO3CPU
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Check if this address is a valid instruction address. */
- bool validInstAddr(Addr addr) { return true; }
-
- /** Check if this address is a valid data address. */
- bool validDataAddr(Addr addr) { return true; }
-
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
@@ -699,10 +693,10 @@ class FullO3CPU : public BaseO3CPU
}
/** Used by the fetch unit to get a hold of the instruction port. */
- virtual MasterPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
/** Get the dcache port (used to find block size for translations). */
- virtual MasterPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar timesIdled;
diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh
index 1f26f1aac..bef8cb949 100644
--- a/src/cpu/pred/bpred_unit.hh
+++ b/src/cpu/pred/bpred_unit.hh
@@ -75,7 +75,7 @@ class BPredUnit : public SimObject
/**
* Registers statistics.
*/
- void regStats();
+ void regStats() override;
void regProbePoints() override;
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 372df7cbd..1a2f19949 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -55,7 +55,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
AtomicSimpleCPU(AtomicSimpleCPUParams *params);
virtual ~AtomicSimpleCPU();
- virtual void init();
+ void init() override;
private:
@@ -181,10 +181,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
protected:
/** Return a reference to the data port. */
- virtual MasterPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Return a reference to the instruction port. */
- virtual MasterPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
/** Perform snoop for other cpu-local thread contexts. */
void threadSnoop(PacketPtr pkt, ThreadID sender);
@@ -194,20 +194,21 @@ class AtomicSimpleCPU : public BaseSimpleCPU
DrainState drain() override;
void drainResume() override;
- void switchOut();
- void takeOverFrom(BaseCPU *oldCPU);
+ void switchOut() override;
+ void takeOverFrom(BaseCPU *oldCPU) override;
- void verifyMemoryMode() const;
+ void verifyMemoryMode() const override;
- virtual void activateContext(ThreadID thread_num);
- virtual void suspendContext(ThreadID thread_num);
+ void activateContext(ThreadID thread_num) override;
+ void suspendContext(ThreadID thread_num) override;
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size,
+ unsigned flags) override;
Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Addr addr, unsigned flags, uint64_t *res) override;
- virtual void regProbePoints();
+ void regProbePoints() override;
/**
* Print state of address in memory system via PrintReq (for
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 72ac9bb4b..0ec9e502b 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -94,7 +94,7 @@ class BaseSimpleCPU : public BaseCPU
BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
void wakeup(ThreadID tid) override;
- virtual void init();
+ void init() override;
public:
Trace::InstRecord *traceData;
CheckerCPU *checker;
@@ -134,13 +134,13 @@ class BaseSimpleCPU : public BaseCPU
void postExecute();
void advancePC(const Fault &fault);
- virtual void haltContext(ThreadID thread_num);
+ void haltContext(ThreadID thread_num) override;
// statistics
- virtual void regStats();
- virtual void resetStats();
+ void regStats() override;
+ void resetStats() override;
- virtual void startup();
+ void startup() override;
virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
unsigned flags) = 0;
@@ -149,8 +149,8 @@ class BaseSimpleCPU : public BaseCPU
unsigned flags, uint64_t* res) = 0;
void countInst();
- virtual Counter totalInsts() const;
- virtual Counter totalOps() const;
+ Counter totalInsts() const override;
+ Counter totalOps() const override;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index a6c7df988..36e01e9be 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -55,7 +55,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
TimingSimpleCPU(TimingSimpleCPUParams * params);
virtual ~TimingSimpleCPU();
- virtual void init();
+ void init() override;
private:
@@ -265,28 +265,29 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
/** Return a reference to the data port. */
- virtual MasterPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Return a reference to the instruction port. */
- virtual MasterPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
public:
DrainState drain() override;
void drainResume() override;
- void switchOut();
- void takeOverFrom(BaseCPU *oldCPU);
+ void switchOut() override;
+ void takeOverFrom(BaseCPU *oldCPU) override;
- void verifyMemoryMode() const;
+ void verifyMemoryMode() const override;
- virtual void activateContext(ThreadID thread_num);
- virtual void suspendContext(ThreadID thread_num);
+ void activateContext(ThreadID thread_num) override;
+ void suspendContext(ThreadID thread_num) override;
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size,
+ unsigned flags) override;
Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Addr addr, unsigned flags, uint64_t *res) override;
void fetch();
void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh
index e5295bcf5..d57b613f3 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.hh
+++ b/src/cpu/testers/traffic_gen/traffic_gen.hh
@@ -192,12 +192,12 @@ class TrafficGen : public MemObject
~TrafficGen() {}
- virtual BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ BaseMasterPort& getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
- void init();
+ void init() override;
- void initState();
+ void initState() override;
DrainState drain() override;
@@ -205,7 +205,7 @@ class TrafficGen : public MemObject
void unserialize(CheckpointIn &cp) override;
/** Register statistics */
- void regStats();
+ void regStats() override;
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 21:23:34 +0000