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-rw-r--r--src/cpu/o3/dyn_inst.hh7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 5477f46d6..76bd8b291 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -54,13 +54,6 @@
class Packet;
-/**
- * Mostly implementation & ISA specific AlphaDynInst. As with most
- * other classes in the new CPU model, it is templated on the Impl to
- * allow for passing in of all types, such as the CPU type and the ISA
- * type. The AlphaDynInst serves as the primary interface to the CPU
- * for instructions that are executing.
- */
template <class Impl>
class BaseO3DynInst : public BaseDynInst<Impl>
{