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-rw-r--r--src/cpu/base.cc15
-rw-r--r--src/cpu/base.hh5
-rw-r--r--src/cpu/base_dyn_inst.hh2
-rw-r--r--src/cpu/checker/cpu.hh2
-rw-r--r--src/cpu/checker/cpu_impl.hh13
-rw-r--r--src/cpu/o3/alpha/cpu_builder.cc5
-rw-r--r--src/cpu/o3/checker_builder.cc5
-rw-r--r--src/cpu/o3/commit_impl.hh2
-rw-r--r--src/cpu/o3/cpu.cc44
-rw-r--r--src/cpu/o3/iew_impl.hh16
-rw-r--r--src/cpu/o3/lsq_impl.hh10
-rw-r--r--src/cpu/o3/lsq_unit.hh13
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh10
-rw-r--r--src/cpu/o3/thread_state.hh2
-rw-r--r--src/cpu/ozone/checker_builder.cc5
-rw-r--r--src/cpu/ozone/cpu.hh5
-rw-r--r--src/cpu/ozone/cpu_builder.cc5
-rw-r--r--src/cpu/ozone/cpu_impl.hh20
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh4
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh2
-rw-r--r--src/cpu/ozone/lw_lsq_impl.hh8
-rw-r--r--src/cpu/ozone/thread_state.hh4
-rw-r--r--src/cpu/thread_state.hh14
24 files changed, 73 insertions, 141 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index f00dad7d6..513dd7c55 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -60,6 +60,15 @@ vector<BaseCPU *> BaseCPU::cpuList;
// been initialized
int maxThreadsPerCPU = 1;
+CPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival,
+ BaseCPU *_cpu)
+ : Event(q, Event::Stat_Event_Pri), interval(ival),
+ lastNumInst(0), cpu(_cpu)
+{
+ if (interval)
+ schedule(curTick + interval);
+}
+
void
CPUProgressEvent::process()
{
@@ -156,12 +165,6 @@ BaseCPU::BaseCPU(Params *p)
p->max_loads_all_threads, *counter);
}
- if (p->stats_reset_inst != 0) {
- Stats::SetupEvent(Stats::Reset, p->stats_reset_inst, 0, comInstEventQueue[0]);
- cprintf("Stats reset event scheduled for %lli insts\n",
- p->stats_reset_inst);
- }
-
#if FULL_SYSTEM
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 2a3fd9b56..e02527371 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -54,9 +54,7 @@ class CPUProgressEvent : public Event
BaseCPU *cpu;
public:
- CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu)
- : Event(q, Event::Stat_Event_Pri), interval(ival), lastNumInst(0), cpu(_cpu)
- { schedule(curTick + interval); }
+ CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
void process();
@@ -138,7 +136,6 @@ class BaseCPU : public MemObject
Counter max_insts_all_threads;
Counter max_loads_any_thread;
Counter max_loads_all_threads;
- Counter stats_reset_inst;
Tick clock;
bool functionTrace;
Tick functionTraceStart;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 926bfcbb2..c68810954 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -409,7 +409,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
if (width == 32)
- instResult.fp = val;
+ instResult.dbl = (double)val;
else if (width == 64)
instResult.dbl = val;
else
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 737b4b5d4..00b01171f 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -258,7 +258,7 @@ class CheckerCPU : public BaseCPU
thread->setFloatReg(reg_idx, val, width);
switch(width) {
case 32:
- result.fp = val;
+ result.dbl = (double)val;
break;
case 64:
result.dbl = val;
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 3bb81c4b9..8aec79754 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -403,19 +403,20 @@ Checker<DynInstPtr>::validateState()
warn("%lli: Instruction PC %#x results didn't match up, copying all "
"registers from main CPU", curTick, unverifiedInst->readPC());
// Heavy-weight copying of all registers
- cpuXC->copyArchRegs(unverifiedInst->xcBase());
+ thread->copyArchRegs(unverifiedInst->tcBase());
// Also advance the PC. Hopefully no PC-based events happened.
#if THE_ISA != MIPS_ISA
// go to the next instruction
- cpuXC->setPC(cpuXC->readNextPC());
- cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+ thread->setPC(thread->readNextPC());
+ thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
#else
// go to the next instruction
- cpuXC->setPC(cpuXC->readNextPC());
- cpuXC->setNextPC(cpuXC->readNextNPC());
- cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
+ thread->setPC(thread->readNextPC());
+ thread->setNextPC(thread->readNextNPC());
+ thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
#endif
updateThisCycle = false;
+ }
}
template <class DynInstPtr>
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index fbf1f342c..ff123a6f7 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -69,7 +69,6 @@ Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
-Param<Counter> stats_reset_inst;
Param<Tick> progress_interval;
Param<unsigned> cachePorts;
@@ -188,9 +187,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
"Terminate when all threads have reached this load"
"count",
0),
- INIT_PARAM_DFLT(stats_reset_inst,
- "blah",
- 0),
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
@@ -326,7 +322,6 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->max_insts_all_threads = max_insts_all_threads;
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
- params->stats_reset_inst = stats_reset_inst;
params->progress_interval = progress_interval;
//
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index ad83ec57a..02c817499 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -64,7 +64,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
- Param<Counter> stats_reset_inst;
Param<Tick> progress_interval;
#if FULL_SYSTEM
@@ -97,8 +96,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
- INIT_PARAM(stats_reset_inst,
- "blah"),
INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
#if FULL_SYSTEM
@@ -133,7 +130,6 @@ CREATE_SIM_OBJECT(O3Checker)
params->max_insts_all_threads = 0;
params->max_loads_any_thread = 0;
params->max_loads_all_threads = 0;
- params->stats_reset_inst = 0;
params->exitOnError = exitOnError;
params->updateOnError = updateOnError;
params->warnOnlyOnLoadError = warnOnlyOnLoadError;
@@ -148,7 +144,6 @@ CREATE_SIM_OBJECT(O3Checker)
temp = max_insts_all_threads;
temp = max_loads_any_thread;
temp = max_loads_all_threads;
- temp = stats_reset_inst;
Tick temp2 = progress_interval;
params->progress_interval = 0;
temp2++;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 6ae01ae67..c80e4d8c1 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1095,7 +1095,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0;
// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
thread[tid]->profilePC = head_inst->readPC();
- ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getXCProxy(),
+ ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
head_inst->staticInst);
if (node)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 4279df6f7..7386dfadd 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -795,7 +795,6 @@ unsigned int
FullO3CPU<Impl>::drain(Event *drain_event)
{
DPRINTF(O3CPU, "Switching out\n");
- BaseCPU::switchOut(_sampler);
drainCount = 0;
fetch.drain();
decode.drain();
@@ -852,6 +851,8 @@ FullO3CPU<Impl>::signalDrained()
changeState(SimObject::Drained);
+ BaseCPU::switchOut();
+
if (drainEvent) {
drainEvent->process();
drainEvent = NULL;
@@ -878,6 +879,8 @@ FullO3CPU<Impl>::switchOut()
if (checker)
checker->switchOut();
#endif
+ if (tickEvent.scheduled())
+ tickEvent.squash();
}
template <class Impl>
@@ -935,45 +938,6 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
template <class Impl>
-void
-FullO3CPU<Impl>::serialize(std::ostream &os)
-{
- BaseCPU::serialize(os);
- nameOut(os, csprintf("%s.tickEvent", name()));
- tickEvent.serialize(os);
-
- // Use SimpleThread's ability to checkpoint to make it easier to
- // write out the registers. Also make this static so it doesn't
- // get instantiated multiple times (causes a panic in statistics).
- static CPUExecContext temp;
-
- for (int i = 0; i < thread.size(); i++) {
- nameOut(os, csprintf("%s.xc.%i", name(), i));
- temp.copyXC(thread[i]->getXCProxy());
- temp.serialize(os);
- }
-}
-
-template <class Impl>
-void
-FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
-{
- BaseCPU::unserialize(cp, section);
- tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
-
- // Use SimpleThread's ability to checkpoint to make it easier to
- // read in the registers. Also make this static so it doesn't
- // get instantiated multiple times (causes a panic in statistics).
- static CPUExecContext temp;
-
- for (int i = 0; i < thread.size(); i++) {
- temp.copyXC(thread[i]->getXCProxy());
- temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
- thread[i]->getXCProxy()->copyArchRegs(temp.getProxy());
- }
-}
-
-template <class Impl>
uint64_t
FullO3CPU<Impl>::readIntReg(int reg_idx)
{
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index c82f6dd21..b2baae296 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -906,22 +906,6 @@ DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
template <class Impl>
void
-DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
-{
- while (!insts[tid].empty()) {
- if (insts[tid].front()->isLoad() ||
- insts[tid].front()->isStore() ) {
- toRename->iewInfo[tid].dispatchedToLSQ++;
- }
-
- toRename->iewInfo[tid].dispatched++;
-
- insts[tid].pop();
- }
-}
-
-template <class Impl>
-void
DefaultIEW<Impl>::wakeCPU()
{
cpu->wakeCPU();
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index a1ac5adb8..2bbab71f0 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -167,16 +167,6 @@ LSQ<Impl>::regStats()
template<class Impl>
void
-LSQ<Impl>::regStats()
-{
- //Initialize LSQs
- for (int tid=0; tid < numThreads; tid++) {
- thread[tid].regStats();
- }
-}
-
-template<class Impl>
-void
LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
activeThreads = at_ptr;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 8537e9dd7..90d1a3d53 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -410,6 +410,19 @@ class LSQUnit {
/** Total number of loads forwaded from LSQ stores. */
Stats::Scalar<> lsqForwLoads;
+ /** Total number of loads ignored due to invalid addresses. */
+ Stats::Scalar<> invAddrLoads;
+
+ /** Total number of squashed loads. */
+ Stats::Scalar<> lsqSquashedLoads;
+
+ /** Total number of responses from the memory system that are
+ * ignored due to the instruction already being squashed. */
+ Stats::Scalar<> lsqIgnoredResponses;
+
+ /** Tota number of memory ordering violations. */
+ Stats::Scalar<> lsqMemOrderViolation;
+
/** Total number of squashed stores. */
Stats::Scalar<> lsqSquashedStores;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 2922b81bd..98bea74fb 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -416,7 +416,7 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
- if (!(inst->req->flags & UNCACHEABLE) || inst->isAtCommit()) {
+ if (!(inst->req->getFlags() & UNCACHEABLE) || inst->isAtCommit()) {
inst->setExecuted();
}
iewStage->instToCommit(inst);
@@ -832,6 +832,7 @@ LSQUnit<Impl>::completeStore(int store_idx)
// A bit conservative because a store completion may not free up entries,
// but hopefully avoids two store completions in one cycle from making
// the CPU tick twice.
+ cpu->wakeCPU();
cpu->activityThisCycle();
if (store_idx == storeHead) {
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index a4546e669..25e1db21c 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -54,7 +54,7 @@ template <class Impl>
void
O3ThreadContext<Impl>::dumpFuncProfile()
{
- // Currently not supported
+ thread->dumpFuncProfile();
}
#endif
@@ -239,12 +239,16 @@ O3ThreadContext<Impl>::readLastSuspend()
template <class Impl>
void
O3ThreadContext<Impl>::profileClear()
-{}
+{
+ thread->profileClear();
+}
template <class Impl>
void
O3ThreadContext<Impl>::profileSample()
-{}
+{
+ thread->profileSample();
+}
#endif
template <class Impl>
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 0247deb52..5fe7bb94d 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -117,7 +117,7 @@ struct O3ThreadState : public ThreadState {
void dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
- profile->dump(xcProxy, *os);
+ profile->dump(tc, *os);
}
#endif
};
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index 99ba3e308..b4c4686b7 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -65,7 +65,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
- Param<Counter> stats_reset_inst;
Param<Tick> progress_interval;
#if FULL_SYSTEM
@@ -98,8 +97,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
- INIT_PARAM(stats_reset_inst,
- "blah"),
INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
#if FULL_SYSTEM
@@ -134,7 +131,6 @@ CREATE_SIM_OBJECT(OzoneChecker)
params->max_insts_all_threads = 0;
params->max_loads_any_thread = 0;
params->max_loads_all_threads = 0;
- params->stats_reset_inst = 0;
params->exitOnError = exitOnError;
params->updateOnError = updateOnError;
params->warnOnlyOnLoadError = warnOnlyOnLoadError;
@@ -149,7 +145,6 @@ CREATE_SIM_OBJECT(OzoneChecker)
temp = max_insts_all_threads;
temp = max_loads_any_thread;
temp = max_loads_all_threads;
- temp = stats_reset_inst;
Tick temp2 = progress_interval;
temp2++;
params->progress_interval = 0;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index ece68282f..8c5be9424 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -33,6 +33,7 @@
#include <set>
+#include "arch/regfile.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
@@ -257,8 +258,8 @@ class OzoneCPU : public BaseCPU
void setFuncExeInst(Counter new_val)
{ thread->funcExeInst = new_val; }
#endif
- void changeRegFileContext(TheISA::RegFile::ContextParam param,
- TheISA::RegFile::ContextVal val)
+ void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val)
{ panic("Not supported on Alpha!"); }
};
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index e3e4ec433..730158258 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -77,7 +77,6 @@ Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
-Param<Counter> stats_reset_inst;
Param<Tick> progress_interval;
//SimObjectParam<BaseCache *> icache;
@@ -210,9 +209,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
"Terminate when all threads have reached this load"
"count",
0),
- INIT_PARAM_DFLT(stats_reset_inst,
- "blah",
- 0),
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
// INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
@@ -360,7 +356,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->max_insts_all_threads = max_insts_all_threads;
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
- params->stats_reset_inst = stats_reset_inst;
params->progress_interval = progress_interval;
//
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 5c8b5001d..bf547bf94 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -35,6 +35,7 @@
#include "arch/isa_traits.hh" // For MachInst
#include "base/trace.hh"
#include "cpu/base.hh"
+#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/cpu.hh"
@@ -52,6 +53,7 @@
#include "base/callback.hh"
#include "cpu/profile.hh"
#include "kern/kernel_stats.hh"
+#include "mem/physical.hh"
#include "sim/faults.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
@@ -102,7 +104,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
_status = Idle;
if (p->checker) {
-
+#if USE_CHECKER
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
checker->setMemory(mem);
@@ -240,7 +242,7 @@ template <class Impl>
void
OzoneCPU<Impl>::switchOut()
{
- BaseCPU::switchOut(_sampler);
+ BaseCPU::switchOut();
switchCount = 0;
// Front end needs state from back end, so switch out the back end first.
backEnd->switchOut();
@@ -468,10 +470,10 @@ OzoneCPU<Impl>::serialize(std::ostream &os)
// Use SimpleThread's ability to checkpoint to make it easier to
// write out the registers. Also make this static so it doesn't
// get instantiated multiple times (causes a panic in statistics).
- static CPUExecContext temp;
+ static SimpleThread temp;
nameOut(os, csprintf("%s.xc.0", name()));
- temp.copyXC(thread.getXCProxy());
+ temp.copyTC(thread.getTC());
temp.serialize(os);
}
@@ -487,11 +489,11 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
// Use SimpleThread's ability to checkpoint to make it easier to
// read in the registers. Also make this static so it doesn't
// get instantiated multiple times (causes a panic in statistics).
- static CPUExecContext temp;
+ static SimpleThread temp;
- temp.copyXC(thread.getXCProxy());
+ temp.copyTC(thread.getTC());
temp.unserialize(cp, csprintf("%s.xc.0", section));
- thread.getXCProxy()->copyArchRegs(temp.getProxy());
+ thread.getTC()->copyArchRegs(temp.getTC());
}
template <class Impl>
@@ -746,11 +748,13 @@ OzoneCPU<Impl>::processInterrupts()
if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) {
thread.setMiscReg(IPR_ISR, summary);
thread.setMiscReg(IPR_INTID, ipl);
+#if USE_CHECKER
// @todo: Make this more transparent
if (checker) {
checker->threadBase()->setMiscReg(IPR_ISR, summary);
checker->threadBase()->setMiscReg(IPR_INTID, ipl);
}
+#endif
Fault fault = new InterruptFault;
fault->invoke(thread.getTC());
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
@@ -872,7 +876,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
copyArchRegs(old_context);
setCpuId(old_context->readCpuId());
- thread->inst = old_context->getInst();
+ thread->setInst(old_context->getInst());
#if !FULL_SYSTEM
setFuncExeInst(old_context->readFuncExeInst());
#else
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index ba0d70417..db1460eba 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -215,14 +215,14 @@ OzoneDynInst<Impl>::clearMemDependents()
}
template <class Impl>
-MiscReg
+TheISA::MiscReg
OzoneDynInst<Impl>::readMiscReg(int misc_reg)
{
return this->thread->readMiscReg(misc_reg);
}
template <class Impl>
-MiscReg
+TheISA::MiscReg
OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
{
return this->thread->readMiscRegWithEffect(misc_reg, fault);
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index f87a2bc57..c39b9e08b 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -1197,7 +1197,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
// (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
// thread->profilePC = usermode ? 1 : inst->readPC();
thread->profilePC = inst->readPC();
- ProfileNode *node = thread->profile->consume(thread->getXCProxy(),
+ ProfileNode *node = thread->profile->consume(thread->getTC(),
inst->staticInst);
if (node)
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 31ffa9d67..4c96ad149 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -121,7 +121,7 @@ OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
}
if (inst->isStore()) {
- completeStore(state->idx);
+ completeStore(inst);
}
}
@@ -178,6 +178,10 @@ OzoneLWLSQ<Impl>::regStats()
lsqMemOrderViolation
.name(name() + ".memOrderViolation")
.desc("Number of memory ordering violations");
+}
+
+template<class Impl>
+void
OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
{
cpu = cpu_ptr;
@@ -390,7 +394,7 @@ OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
// Actually probably want the oldest faulting load
if (load_fault != NoFault) {
DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
- if (!(inst->req->flags & UNCACHEABLE && !inst->isAtCommit())) {
+ if (!(inst->req->getFlags() & UNCACHEABLE && !inst->isAtCommit())) {
inst->setExecuted();
}
// Maybe just set it as can commit here, although that might cause
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index adaa8e71b..c86f3552e 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -68,7 +68,7 @@ struct OzoneThreadState : public ThreadState {
#if FULL_SYSTEM
OzoneThreadState(CPUType *_cpu, int _thread_num)
: ThreadState(-1, _thread_num),
- cpu(_cpu), intrflag(0), inSyscall(0), trapPending(0)
+ intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
{
if (cpu->params->profile) {
profile = new FunctionProfile(cpu->params->system->kernelSymtab);
@@ -151,7 +151,7 @@ struct OzoneThreadState : public ThreadState {
void dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
- profile->dump(xcProxy, *os);
+ profile->dump(tc, *os);
}
#endif
};
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 5479f8478..14e033b7f 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -195,20 +195,6 @@ struct ThreadState {
#endif
-#if FULL_SYSTEM
- void profileClear()
- {
- if (profile)
- profile->clear();
- }
-
- void profileSample()
- {
- if (profile)
- profile->sample(profileNode, profilePC);
- }
-#endif
-
/** Current instruction the thread is committing. Only set and
* used for DTB faults currently.
*/
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 00:08:50 +0000