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-rw-r--r--src/cpu/base_dyn_inst.hh3
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc48
-rw-r--r--src/cpu/o3/commit_impl.hh15
-rw-r--r--src/cpu/o3/dyn_inst.hh83
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh14
-rw-r--r--src/cpu/simple/base.hh17
6 files changed, 85 insertions, 95 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 638ee33c1..bd2d9fa95 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -859,7 +859,8 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
if (fault != NoFault) {
// Return a fixed value to keep simulation deterministic even
// along misspeculated paths.
- bzero(data, size);
+ if (data)
+ bzero(data, size);
}
if (traceData) {
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index d848226c4..70fd59418 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -419,18 +419,12 @@ InOrderDynInst::readMiscReg(int misc_reg)
return this->cpu->readMiscReg(misc_reg, threadNumber);
}
+
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
MiscReg
-InOrderDynInst::readMiscRegNoEffect(int misc_reg)
-{
- return this->cpu->readMiscRegNoEffect(misc_reg, threadNumber);
-}
-
-/** Reads a miscellaneous register. */
-MiscReg
-InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
+InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
{
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
" read as %#x.\n", threadNumber, seqNum, idx,
@@ -438,22 +432,13 @@ InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
return instSrc[idx].integer;
}
-/** Reads a misc. register, including any side-effects the read
+
+/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
-MiscReg
-InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
-{
- // For In-Order, the side-effect of reading a register happens
- // when explicitly executing a "ReadSrc" command. This simply returns
- // a value.
- return readMiscRegOperandNoEffect(si, idx);
-}
-
-/** Sets a misc. register. */
void
-InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx,
- const MiscReg &val)
+InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
+ const MiscReg &val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
@@ -463,19 +448,6 @@ InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx,
"being set to %#x.\n", threadNumber, seqNum, idx, val);
}
-/** Sets a misc. register, including any side-effects the write
- * might have as defined by the architecture.
- */
-void
-InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val)
-{
- // For In-Order, the side-effect of setting a register happens
- // when explicitly writing back the register value. This
- // simply maintains the operand value.
- setMiscRegOperandNoEffect(si, idx, val);
-}
-
MiscReg
InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
{
@@ -534,14 +506,6 @@ InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
threadNumber, seqNum, idx, val, instResult[idx].tick);
}
-/** Sets a misc. register. */
-/* Alter this when wanting to *speculate* on Miscellaneous registers */
-void
-InOrderDynInst::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
-{
- this->cpu->setMiscRegNoEffect(misc_reg, val, threadNumber);
-}
-
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 8d3edfb19..1a44c64ee 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -900,6 +912,9 @@ DefaultCommit<Impl>::commitInsts()
cpu->instDone(tid);
}
+ // Updates misc. registers.
+ head_inst->updateMiscRegs();
+
TheISA::advancePC(pc[tid], head_inst->staticInst);
int count = 0;
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 6bd1f9fad..b62068111 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -99,13 +111,18 @@ class BaseO3DynInst : public BaseDynInst<Impl>
/** Initializes variables. */
void initVars();
- public:
- /** Reads a miscellaneous register. */
- MiscReg readMiscRegNoEffect(int misc_reg)
- {
- return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
- }
+ protected:
+ /** Indexes of the destination misc. registers. They are needed to defer
+ * the write accesses to the misc. registers until the commit stage, when
+ * the instruction is out of its speculative state.
+ */
+ int _destMiscRegIdx[MaxInstDestRegs];
+ /** Values to be written to the destination misc. registers. */
+ MiscReg _destMiscRegVal[MaxInstDestRegs];
+ /** Number of destination misc. registers. */
+ int _numDestMiscRegs;
+ public:
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
@@ -114,28 +131,17 @@ class BaseO3DynInst : public BaseDynInst<Impl>
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
- /** Sets a misc. register. */
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
- {
- this->instResult.integer = val;
- return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
- }
-
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
void setMiscReg(int misc_reg, const MiscReg &val)
{
- return this->cpu->setMiscReg(misc_reg, val,
- this->threadNumber);
- }
-
- /** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
- {
- return this->cpu->readMiscRegNoEffect(
- si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- this->threadNumber);
+ /** Writes to misc. registers are recorded and deferred until the
+ * commit stage, when updateMiscRegs() is called.
+ */
+ _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
+ _destMiscRegVal[_numDestMiscRegs] = val;
+ _numDestMiscRegs++;
}
/** Reads a misc. register, including any side-effects the read
@@ -148,24 +154,31 @@ class BaseO3DynInst : public BaseDynInst<Impl>
this->threadNumber);
}
- /** Sets a misc. register. */
- void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
- {
- this->instResult.integer = val;
- return this->cpu->setMiscRegNoEffect(
- si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- val, this->threadNumber);
- }
-
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
void setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
- return this->cpu->setMiscReg(
- si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- val, this->threadNumber);
+ int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ setMiscReg(misc_reg, val);
+ }
+
+ /** Called at the commit stage to update the misc. registers. */
+ void updateMiscRegs()
+ {
+ // @todo: Pretty convoluted way to avoid squashing from happening when
+ // using the TC during an instruction's execution (specifically for
+ // instructions that have side-effects that use the TC). Fix this.
+ // See cpu/o3/dyn_inst_impl.hh.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
+ for (int i = 0; i < _numDestMiscRegs; i++)
+ this->cpu->setMiscReg(
+ _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
+
+ this->thread->inSyscall = in_syscall;
}
#if FULL_SYSTEM
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 268746655..89d6528a1 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -71,6 +83,8 @@ BaseO3DynInst<Impl>::initVars()
this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
this->_readySrcRegIdx[i] = 0;
}
+
+ _numDestMiscRegs = 0;
}
template <class Impl>
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index f7dcd4a86..bd967b185 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -297,34 +297,17 @@ class BaseSimpleCPU : public BaseCPU
return thread->readMiscReg(misc_reg);
}
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
- {
- return thread->setMiscRegNoEffect(misc_reg, val);
- }
-
void setMiscReg(int misc_reg, const MiscReg &val)
{
return thread->setMiscReg(misc_reg, val);
}
- MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
- {
- int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->readMiscRegNoEffect(reg_idx);
- }
-
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscReg(reg_idx);
}
- void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
- {
- int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->setMiscRegNoEffect(reg_idx, val);
- }
-
void setMiscRegOperand(
const StaticInst *si, int idx, const MiscReg &val)
{
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