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-rw-r--r--src/cpu/simple/timing.cc30
-rw-r--r--src/cpu/simple/timing.hh6
2 files changed, 17 insertions, 19 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 877364eff..ad04c8d3b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -88,7 +88,7 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
{
_status = Idle;
ifetch_pkt = dcache_pkt = NULL;
- quiesceEvent = NULL;
+ drainEvent = NULL;
state = SimObject::Timing;
}
@@ -112,18 +112,16 @@ TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
}
bool
-TimingSimpleCPU::quiesce(Event *quiesce_event)
+TimingSimpleCPU::drain(Event *drain_event)
{
- // TimingSimpleCPU is ready to quiesce if it's not waiting for
+ // TimingSimpleCPU is ready to drain if it's not waiting for
// an access to complete.
if (status() == Idle || status() == Running || status() == SwitchedOut) {
- DPRINTF(Config, "Ready to quiesce\n");
- changeState(SimObject::QuiescedTiming);
+ changeState(SimObject::DrainedTiming);
return false;
} else {
- DPRINTF(Config, "Waiting to quiesce\n");
- changeState(SimObject::Quiescing);
- quiesceEvent = quiesce_event;
+ changeState(SimObject::Draining);
+ drainEvent = drain_event;
return true;
}
}
@@ -423,8 +421,8 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
delete pkt->req;
delete pkt;
- if (getState() == SimObject::Quiescing) {
- completeQuiesce();
+ if (getState() == SimObject::Draining) {
+ completeDrain();
return;
}
@@ -480,8 +478,8 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
assert(_status == DcacheWaitResponse);
_status = Running;
- if (getState() == SimObject::Quiescing) {
- completeQuiesce();
+ if (getState() == SimObject::Draining) {
+ completeDrain();
delete pkt->req;
delete pkt;
@@ -500,11 +498,11 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
void
-TimingSimpleCPU::completeQuiesce()
+TimingSimpleCPU::completeDrain()
{
- DPRINTF(Config, "Done quiescing\n");
- changeState(SimObject::QuiescedTiming);
- quiesceEvent->process();
+ DPRINTF(Config, "Done draining\n");
+ changeState(SimObject::DrainedTiming);
+ drainEvent->process();
}
bool
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index d91144e4a..c360e553e 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -64,7 +64,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
Status status() const { return _status; }
- Event *quiesceEvent;
+ Event *drainEvent;
private:
@@ -133,7 +133,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
- virtual bool quiesce(Event *quiesce_event);
+ virtual bool drain(Event *drain_event);
virtual void resume();
virtual void setMemoryMode(State new_mode);
@@ -154,7 +154,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void completeDataAccess(Packet *);
void advanceInst(Fault fault);
private:
- void completeQuiesce();
+ void completeDrain();
};
#endif // __CPU_SIMPLE_TIMING_HH__