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-rw-r--r--src/cpu/NativeTrace.py1
-rw-r--r--src/cpu/SConscript6
-rw-r--r--src/cpu/nativetrace.cc169
-rw-r--r--src/cpu/nativetrace.hh155
4 files changed, 40 insertions, 291 deletions
diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py
index f410b5473..7fd240543 100644
--- a/src/cpu/NativeTrace.py
+++ b/src/cpu/NativeTrace.py
@@ -31,5 +31,6 @@ from m5.params import *
from InstTracer import InstTracer
class NativeTrace(InstTracer):
+ abstract = True
type = 'NativeTrace'
cxx_class = 'Trace::NativeTrace'
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 44f8817ff..ea79b622c 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -112,6 +112,7 @@ SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
+SimObject('NativeTrace.py')
Source('activity.cc')
Source('base.cc')
@@ -119,6 +120,7 @@ Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
+Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
@@ -136,10 +138,6 @@ if env['FULL_SYSTEM']:
SimObject('LegionTrace.py')
Source('legiontrace.cc')
-if env['TARGET_ISA'] == 'x86':
- SimObject('NativeTrace.py')
- Source('nativetrace.cc')
-
if env['USE_CHECKER']:
Source('checker/cpu.cc')
TraceFlag('Checker')
diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc
index fca8674f9..47c58434f 100644
--- a/src/cpu/nativetrace.cc
+++ b/src/cpu/nativetrace.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006-2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,28 +25,15 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Steve Reinhardt
- * Lisa Hsu
- * Nathan Binkert
- * Steve Raasch
+ * Authors: Gabe Black
*/
-#include <errno.h>
-
-#include "arch/registers.hh"
-#include "arch/utility.hh"
-#include "base/loader/symtab.hh"
#include "base/socket.hh"
#include "cpu/nativetrace.hh"
#include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
#include "params/NativeTrace.hh"
-//XXX This is temporary
-#include "arch/isa_specific.hh"
-
using namespace std;
-using namespace TheISA;
namespace Trace {
@@ -64,41 +51,6 @@ NativeTrace::NativeTrace(const Params *p)
}
ccprintf(cerr, "Listening for native process on port %d\n", port);
fd = native_listener.accept();
- checkRcx = true;
- checkR11 = true;
-}
-
-bool
-NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
-{
- if(!checkRcx)
- checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
- if(checkRcx)
- return checkReg(name, mVal, nVal);
- return true;
-}
-
-bool
-NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
-{
- if(!checkR11)
- checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
- if(checkR11)
- return checkReg(name, mVal, nVal);
- return true;
-}
-
-bool
-NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
-{
- if (mXmmBuf[num * 2] != nXmmBuf[num * 2] ||
- mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
- DPRINTFN("Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
- num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
- mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
- return false;
- }
- return true;
}
void
@@ -106,119 +58,8 @@ Trace::NativeTraceRecord::dump()
{
//Don't print what happens for each micro-op, just print out
//once at the last op, and for regular instructions.
- if(!staticInst->isMicroop() || staticInst->isLastMicroop())
- parent->check(thread, staticInst->isSyscall());
+ if (!staticInst->isMicroop() || staticInst->isLastMicroop())
+ parent->check(this);
}
-void
-Trace::NativeTrace::check(ThreadContext * tc, bool isSyscall)
-{
-// ostream &outs = Trace::output();
- nState.update(fd);
- mState.update(tc);
-
- if(isSyscall)
- {
- checkRcx = false;
- checkR11 = false;
- oldRcxVal = mState.rcx;
- oldRealRcxVal = nState.rcx;
- oldR11Val = mState.r11;
- oldRealR11Val = nState.r11;
- }
-
- checkReg("rax", mState.rax, nState.rax);
- checkRcxReg("rcx", mState.rcx, nState.rcx);
- checkReg("rdx", mState.rdx, nState.rdx);
- checkReg("rbx", mState.rbx, nState.rbx);
- checkReg("rsp", mState.rsp, nState.rsp);
- checkReg("rbp", mState.rbp, nState.rbp);
- checkReg("rsi", mState.rsi, nState.rsi);
- checkReg("rdi", mState.rdi, nState.rdi);
- checkReg("r8", mState.r8, nState.r8);
- checkReg("r9", mState.r9, nState.r9);
- checkReg("r10", mState.r10, nState.r10);
- checkR11Reg("r11", mState.r11, nState.r11);
- checkReg("r12", mState.r12, nState.r12);
- checkReg("r13", mState.r13, nState.r13);
- checkReg("r14", mState.r14, nState.r14);
- checkReg("r15", mState.r15, nState.r15);
- checkReg("rip", mState.rip, nState.rip);
- checkXMM(0, mState.xmm, nState.xmm);
- checkXMM(1, mState.xmm, nState.xmm);
- checkXMM(2, mState.xmm, nState.xmm);
- checkXMM(3, mState.xmm, nState.xmm);
- checkXMM(4, mState.xmm, nState.xmm);
- checkXMM(5, mState.xmm, nState.xmm);
- checkXMM(6, mState.xmm, nState.xmm);
- checkXMM(7, mState.xmm, nState.xmm);
- checkXMM(8, mState.xmm, nState.xmm);
- checkXMM(9, mState.xmm, nState.xmm);
- checkXMM(10, mState.xmm, nState.xmm);
- checkXMM(11, mState.xmm, nState.xmm);
- checkXMM(12, mState.xmm, nState.xmm);
- checkXMM(13, mState.xmm, nState.xmm);
- checkXMM(14, mState.xmm, nState.xmm);
- checkXMM(15, mState.xmm, nState.xmm);
-#if THE_ISA == SPARC_ISA
- /*for(int f = 0; f <= 62; f+=2)
- {
- uint64_t regVal;
- int res = read(fd, &regVal, sizeof(regVal));
- if(res < 0)
- panic("First read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- uint64_t realRegVal = thread->readFloatRegBits(f, 64);
- if(regVal != realRegVal)
- {
- DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
- }
- }*/
- uint64_t regVal;
- int res = read(fd, &regVal, sizeof(regVal));
- if(res < 0)
- panic("First read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- uint64_t realRegVal = thread->readNextPC();
- if(regVal != realRegVal)
- {
- DPRINTF(ExecRegDelta,
- "Register pc should be %#x but is %#x.\n",
- regVal, realRegVal);
- }
- res = read(fd, &regVal, sizeof(regVal));
- if(res < 0)
- panic("First read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- realRegVal = thread->readNextNPC();
- if(regVal != realRegVal)
- {
- DPRINTF(ExecRegDelta,
- "Register npc should be %#x but is %#x.\n",
- regVal, realRegVal);
- }
- res = read(fd, &regVal, sizeof(regVal));
- if(res < 0)
- panic("First read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
- if((regVal & 0xF) != (realRegVal & 0xF))
- {
- DPRINTF(ExecRegDelta,
- "Register ccr should be %#x but is %#x.\n",
- regVal, realRegVal);
- }
-#endif
-}
-
-/* namespace Trace */ }
-
-////////////////////////////////////////////////////////////////////////
-//
-// ExeTracer Simulation Object
-//
-Trace::NativeTrace *
-NativeTraceParams::create()
-{
- return new Trace::NativeTrace(this);
-};
+} /* namespace Trace */
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index f137e66ee..34869f263 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006-2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,15 +25,16 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Steve Reinhardt
- * Nathan Binkert
+ * Authors: Gabe Black
*/
#ifndef __CPU_NATIVETRACE_HH__
#define __CPU_NATIVETRACE_HH__
-#include "arch/x86/floatregs.hh"
-#include "arch/x86/intregs.hh"
+#include <errno.h>
+#include <unistd.h>
+
+#include "base/socket.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
@@ -71,102 +72,22 @@ class NativeTrace : public InstTracer
ListenSocket native_listener;
- bool checkRcx;
- bool checkR11;
- uint64_t oldRcxVal, oldR11Val;
- uint64_t oldRealRcxVal, oldRealR11Val;
-
- struct ThreadState {
- uint64_t rax;
- uint64_t rcx;
- uint64_t rdx;
- uint64_t rbx;
- uint64_t rsp;
- uint64_t rbp;
- uint64_t rsi;
- uint64_t rdi;
- uint64_t r8;
- uint64_t r9;
- uint64_t r10;
- uint64_t r11;
- uint64_t r12;
- uint64_t r13;
- uint64_t r14;
- uint64_t r15;
- uint64_t rip;
- //This should be expanded to 16 if x87 registers are considered
- uint64_t mmx[8];
- uint64_t xmm[32];
-
- void update(int fd)
- {
- int bytesLeft = sizeof(ThreadState);
- int bytesRead = 0;
- do
- {
- int res = read(fd, ((char *)this) + bytesRead, bytesLeft);
- if(res < 0)
- panic("Read call failed! %s\n", strerror(errno));
- bytesLeft -= res;
- bytesRead += res;
- } while(bytesLeft);
- rax = TheISA::gtoh(rax);
- rcx = TheISA::gtoh(rcx);
- rdx = TheISA::gtoh(rdx);
- rbx = TheISA::gtoh(rbx);
- rsp = TheISA::gtoh(rsp);
- rbp = TheISA::gtoh(rbp);
- rsi = TheISA::gtoh(rsi);
- rdi = TheISA::gtoh(rdi);
- r8 = TheISA::gtoh(r8);
- r9 = TheISA::gtoh(r9);
- r10 = TheISA::gtoh(r10);
- r11 = TheISA::gtoh(r11);
- r12 = TheISA::gtoh(r12);
- r13 = TheISA::gtoh(r13);
- r14 = TheISA::gtoh(r14);
- r15 = TheISA::gtoh(r15);
- rip = TheISA::gtoh(rip);
- //This should be expanded if x87 registers are considered
- for (int i = 0; i < 8; i++)
- mmx[i] = TheISA::gtoh(mmx[i]);
- for (int i = 0; i < 32; i++)
- xmm[i] = TheISA::gtoh(xmm[i]);
- }
-
- void update(ThreadContext * tc)
- {
- rax = tc->readIntReg(X86ISA::INTREG_RAX);
- rcx = tc->readIntReg(X86ISA::INTREG_RCX);
- rdx = tc->readIntReg(X86ISA::INTREG_RDX);
- rbx = tc->readIntReg(X86ISA::INTREG_RBX);
- rsp = tc->readIntReg(X86ISA::INTREG_RSP);
- rbp = tc->readIntReg(X86ISA::INTREG_RBP);
- rsi = tc->readIntReg(X86ISA::INTREG_RSI);
- rdi = tc->readIntReg(X86ISA::INTREG_RDI);
- r8 = tc->readIntReg(X86ISA::INTREG_R8);
- r9 = tc->readIntReg(X86ISA::INTREG_R9);
- r10 = tc->readIntReg(X86ISA::INTREG_R10);
- r11 = tc->readIntReg(X86ISA::INTREG_R11);
- r12 = tc->readIntReg(X86ISA::INTREG_R12);
- r13 = tc->readIntReg(X86ISA::INTREG_R13);
- r14 = tc->readIntReg(X86ISA::INTREG_R14);
- r15 = tc->readIntReg(X86ISA::INTREG_R15);
- rip = tc->readNextPC();
- //This should be expanded if x87 registers are considered
- for (int i = 0; i < 8; i++)
- mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
- for (int i = 0; i < 32; i++)
- xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
- }
-
- };
+ public:
- ThreadState nState;
- ThreadState mState;
+ NativeTrace(const Params *p);
+ virtual ~NativeTrace() {}
+ NativeTraceRecord *
+ getInstRecord(Tick when, ThreadContext *tc,
+ const StaticInstPtr staticInst, Addr pc,
+ const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0)
+ {
+ if (tc->misspeculating())
+ return NULL;
- public:
+ return new NativeTraceRecord(this, when, tc,
+ staticInst, pc, tc->misspeculating(), macroStaticInst, upc);
+ }
template<class T>
bool
@@ -181,35 +102,23 @@ class NativeTrace : public InstTracer
return true;
}
- bool
- checkRcxReg(const char * regName, uint64_t &, uint64_t &);
-
- bool
- checkR11Reg(const char * regName, uint64_t &, uint64_t &);
-
- bool
- checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
-
- NativeTrace(const Params *p);
-
- NativeTraceRecord *
- getInstRecord(Tick when, ThreadContext *tc,
- const StaticInstPtr staticInst, Addr pc,
- const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0)
+ void
+ read(void *ptr, size_t size)
{
- if (tc->misspeculating())
- return NULL;
-
- return new NativeTraceRecord(this, when, tc,
- staticInst, pc, tc->misspeculating(), macroStaticInst, upc);
+ size_t soFar = 0;
+ while (soFar < size) {
+ size_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar);
+ if (res < 0)
+ panic("Read call failed! %s\n", strerror(errno));
+ else
+ soFar += res;
+ }
}
- void
- check(ThreadContext *, bool syscall);
-
- friend class NativeTraceRecord;
+ virtual void
+ check(NativeTraceRecord *record) = 0;
};
-/* namespace Trace */ }
+} /* namespace Trace */
#endif // __CPU_NATIVETRACE_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 20:42:07 +0000