diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 33 | ||||
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 2 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.py | 2 | ||||
| -rw-r--r-- | src/cpu/testers/memtest/MemTest.py | 5 | ||||
| -rw-r--r-- | src/cpu/testers/networktest/NetworkTest.py | 2 | ||||
| -rw-r--r-- | src/cpu/testers/rubytest/RubyTester.py | 2 |
6 files changed, 32 insertions, 14 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index fda0a3bc8..0bb2090ad 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2005-2008 The Regents of The University of Michigan # Copyright (c) 2011 Regents of the University of California # All rights reserved. @@ -27,6 +39,7 @@ # # Authors: Nathan Binkert # Rick Strong +# Andreas Hansson import sys @@ -138,24 +151,28 @@ class BaseCPU(MemObject): tracer = Param.InstTracer(default_tracer, "Instruction tracer") - icache_port = Port("Instruction Port") - dcache_port = Port("Data Port") + icache_port = MasterPort("Instruction Port") + dcache_port = MasterPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] - _uncached_ports = [] + _uncached_slave_ports = [] + _uncached_master_ports = [] if buildEnv['TARGET_ISA'] == 'x86': - _uncached_ports = ["interrupts.pio", "interrupts.int_port"] + _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] + _uncached_master_ports += ["interrupts.int_master"] def connectCachedPorts(self, bus): for p in self._cached_ports: - exec('self.%s = bus.port' % p) + exec('self.%s = bus.slave' % p) def connectUncachedPorts(self, bus): - for p in self._uncached_ports: - exec('self.%s = bus.port' % p) + for p in self._uncached_slave_ports: + exec('self.%s = bus.master' % p) + for p in self._uncached_master_ports: + exec('self.%s = bus.slave' % p) def connectAllPorts(self, cached_bus, uncached_bus = None): self.connectCachedPorts(cached_bus) @@ -190,5 +207,5 @@ class BaseCPU(MemObject): self.toL2Bus = Bus() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c - self.l2cache.cpu_side = self.toL2Bus.port + self.toL2Bus.master = self.l2cache.cpu_side self._cached_ports = ['l2cache.mem_side'] diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 93cd02ba7..1199f35e1 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -34,4 +34,4 @@ class AtomicSimpleCPU(BaseSimpleCPU): width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") - physmem_port = Port("Physical Memory Port") + physmem_port = MasterPort("Physical Memory Port") diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index ccadc5b36..bf3eace08 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -48,6 +48,6 @@ class InvalidateGenerator(DirectedGenerator): class RubyDirectedTester(MemObject): type = 'RubyDirectedTester' - cpuPort = VectorPort("the cpu ports") + cpuPort = VectorMasterPort("the cpu ports") requests_to_complete = Param.Int("checks to complete") generator = Param.DirectedGenerator("the request generator") diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 6a3568379..1b4d6767c 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -48,8 +48,9 @@ class MemTest(MemObject): "progress report interval (in accesses)") trace_addr = Param.Addr(0, "address to trace") - test = Port("Port to the memory system to test") - functional = Port("Port to the functional memory used for verification") + test = MasterPort("Port to the memory system to test") + functional = MasterPort("Port to the functional memory " \ + "used for verification") suppress_func_warnings = Param.Bool(False, "suppress warnings when functional accesses fail.\n") sys = Param.System(Parent.any, "System Parameter") diff --git a/src/cpu/testers/networktest/NetworkTest.py b/src/cpu/testers/networktest/NetworkTest.py index b2eda9aa2..7d6ed576b 100644 --- a/src/cpu/testers/networktest/NetworkTest.py +++ b/src/cpu/testers/networktest/NetworkTest.py @@ -41,5 +41,5 @@ class NetworkTest(MemObject): traffic_type = Param.Counter(0, "Traffic type: uniform random, tornado, bit complement") inj_rate = Param.Float(0.1, "Packet injection rate") precision = Param.Int(3, "Number of digits of precision after decimal point") - test = Port("Port to the memory system to test") + test = MasterPort("Port to the memory system to test") system = Param.System(Parent.any, "System we belong to") diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index fc0a60e11..6518862e9 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -32,7 +32,7 @@ from m5.proxy import * class RubyTester(MemObject): type = 'RubyTester' - cpuPort = VectorPort("the cpu ports") + cpuPort = VectorMasterPort("the cpu ports") checks_to_complete = Param.Int(100, "checks to complete") deadlock_threshold = Param.Int(50000, "how often to check for deadlock") wakeup_frequency = Param.Int(10, "number of cycles between wakeups") |