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-rw-r--r--src/cpu/inorder/cpu.cc4
-rw-r--r--src/cpu/inorder/cpu.hh2
-rw-r--r--src/cpu/inorder/pipeline_traits.hh2
-rw-r--r--src/cpu/memtest/memtest.cc2
-rw-r--r--src/cpu/ozone/cpu_impl.hh4
-rw-r--r--src/cpu/pred/2bit_local.cc4
-rw-r--r--src/cpu/pred/btb.cc4
-rw-r--r--src/cpu/pred/ras.cc4
-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/base.cc6
-rw-r--r--src/cpu/simple/timing.cc4
11 files changed, 22 insertions, 20 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 24483bf25..3d7d713e8 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -184,7 +184,7 @@ InOrderCPU::InOrderCPU(Params *params)
// Resize for Multithreading CPUs
thread.resize(numThreads);
- int active_threads = params->workload.size();
+ ThreadID active_threads = params->workload.size();
if (active_threads > MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads'"
@@ -204,7 +204,7 @@ InOrderCPU::InOrderCPU(Params *params)
}
for (ThreadID tid = 0; tid < numThreads; ++tid) {
- if (tid < params->workload.size()) {
+ if (tid < (ThreadID)params->workload.size()) {
DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
tid, this->thread[tid]);
this->thread[tid] =
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index faf37382f..794d81def 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -623,7 +623,7 @@ class InOrderCPU : public BaseCPU
{
Counter total(0);
- for (ThreadID tid = 0; tid < thread.size(); tid++)
+ for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
total += thread[tid]->numInst;
return total;
diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh
index 5012553b0..3c28894e7 100644
--- a/src/cpu/inorder/pipeline_traits.hh
+++ b/src/cpu/inorder/pipeline_traits.hh
@@ -49,7 +49,7 @@ class InOrderDynInst;
namespace ThePipeline {
// Pipeline Constants
const unsigned NumStages = 5;
- const unsigned MaxThreads = 8;
+ const ThreadID MaxThreads = 8;
const unsigned StageWidth = 1;
const unsigned BackEndStartStage = 2;
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 3c57f85b7..fccb8435f 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -217,7 +217,7 @@ MemTest::completeRequest(PacketPtr pkt)
numReads++;
numReadsStat++;
- if (numReads == nextProgressMessage) {
+ if (numReads == (uint64_t)nextProgressMessage) {
ccprintf(cerr, "%s: completed %d read accesses @%d\n",
name(), numReads, curTick);
nextProgressMessage += progressInterval;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index ba1205010..25fa64071 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -488,7 +488,7 @@ OzoneCPU<Impl>::copySrcTranslate(Addr src)
return NoFault;
#if 0
static bool no_warn = true;
- int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ unsigned blk_size = dcacheInterface ? dcacheInterface->getBlockSize() : 64;
// Only support block sizes of 64 atm.
assert(blk_size == 64);
int offset = src & (blk_size - 1);
@@ -527,7 +527,7 @@ OzoneCPU<Impl>::copy(Addr dest)
return NoFault;
#if 0
static bool no_warn = true;
- int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ unsigned blk_size = dcacheInterface ? dcacheInterface->getBlockSize() : 64;
// Only support block sizes of 64 atm.
assert(blk_size == 64);
uint8_t data[blk_size];
diff --git a/src/cpu/pred/2bit_local.cc b/src/cpu/pred/2bit_local.cc
index 65925fe79..a70d65296 100644
--- a/src/cpu/pred/2bit_local.cc
+++ b/src/cpu/pred/2bit_local.cc
@@ -58,7 +58,7 @@ LocalBP::LocalBP(unsigned _localPredictorSize,
// Setup the array of counters for the local predictor.
localCtrs.resize(localPredictorSets);
- for (int i = 0; i < localPredictorSets; ++i)
+ for (unsigned i = 0; i < localPredictorSets; ++i)
localCtrs[i].setBits(_localCtrBits);
DPRINTF(Fetch, "Branch predictor: local predictor size: %i\n",
@@ -73,7 +73,7 @@ LocalBP::LocalBP(unsigned _localPredictorSize,
void
LocalBP::reset()
{
- for (int i = 0; i < localPredictorSets; ++i) {
+ for (unsigned i = 0; i < localPredictorSets; ++i) {
localCtrs[i].reset();
}
}
diff --git a/src/cpu/pred/btb.cc b/src/cpu/pred/btb.cc
index 81676aceb..c6a5e23f9 100644
--- a/src/cpu/pred/btb.cc
+++ b/src/cpu/pred/btb.cc
@@ -47,7 +47,7 @@ DefaultBTB::DefaultBTB(unsigned _numEntries,
btb.resize(numEntries);
- for (int i = 0; i < numEntries; ++i) {
+ for (unsigned i = 0; i < numEntries; ++i) {
btb[i].valid = false;
}
@@ -61,7 +61,7 @@ DefaultBTB::DefaultBTB(unsigned _numEntries,
void
DefaultBTB::reset()
{
- for (int i = 0; i < numEntries; ++i) {
+ for (unsigned i = 0; i < numEntries; ++i) {
btb[i].valid = false;
}
}
diff --git a/src/cpu/pred/ras.cc b/src/cpu/pred/ras.cc
index 5af188749..6373e5de3 100644
--- a/src/cpu/pred/ras.cc
+++ b/src/cpu/pred/ras.cc
@@ -39,7 +39,7 @@ ReturnAddrStack::init(unsigned _numEntries)
addrStack.resize(numEntries);
- for (int i = 0; i < numEntries; ++i)
+ for (unsigned i = 0; i < numEntries; ++i)
addrStack[i] = 0;
}
@@ -48,7 +48,7 @@ ReturnAddrStack::reset()
{
usedEntries = 0;
tos = 0;
- for (int i = 0; i < numEntries; ++i)
+ for (unsigned i = 0; i < numEntries; ++i)
addrStack[i] = 0;
}
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 2ec56c0f2..bab4b8b51 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -61,7 +61,7 @@ AtomicSimpleCPU::TickEvent::description() const
}
Port *
-AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
+AtomicSimpleCPU::getPort(const string &if_name, int idx)
{
if (if_name == "dcache_port")
return &dcachePort;
@@ -302,7 +302,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
}
//The block size of our peer.
- int blockSize = dcachePort.peerBlockSize();
+ unsigned blockSize = dcachePort.peerBlockSize();
//The size of the data we're trying to read.
int dataSize = sizeof(T);
@@ -444,7 +444,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
}
//The block size of our peer.
- int blockSize = dcachePort.peerBlockSize();
+ unsigned blockSize = dcachePort.peerBlockSize();
//The size of the data we're trying to read.
int dataSize = sizeof(T);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 61d034f31..279fb98b7 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -209,7 +209,8 @@ BaseSimpleCPU::copySrcTranslate(Addr src)
{
#if 0
static bool no_warn = true;
- int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ unsigned blk_size =
+ (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
// Only support block sizes of 64 atm.
assert(blk_size == 64);
int offset = src & (blk_size - 1);
@@ -247,7 +248,8 @@ BaseSimpleCPU::copy(Addr dest)
{
#if 0
static bool no_warn = true;
- int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ unsigned blk_size =
+ (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
// Only support block sizes of 64 atm.
assert(blk_size == 64);
uint8_t data[blk_size];
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 6666f6f9d..672fd9414 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -439,7 +439,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
const int asid = 0;
const ThreadID tid = 0;
const Addr pc = thread->readPC();
- int block_size = dcachePort.peerBlockSize();
+ unsigned block_size = dcachePort.peerBlockSize();
int data_size = sizeof(T);
RequestPtr req = new Request(asid, addr, data_size,
@@ -557,7 +557,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
const int asid = 0;
const ThreadID tid = 0;
const Addr pc = thread->readPC();
- int block_size = dcachePort.peerBlockSize();
+ unsigned block_size = dcachePort.peerBlockSize();
int data_size = sizeof(T);
RequestPtr req = new Request(asid, addr, data_size,
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 08:07:05 +0000