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-rw-r--r--src/cpu/inorder/cpu.cc9
-rw-r--r--src/cpu/inorder/cpu.hh2
-rw-r--r--src/cpu/o3/cpu.hh4
-rw-r--r--src/cpu/simple/atomic.cc3
-rw-r--r--src/cpu/simple/timing.hh5
5 files changed, 13 insertions, 10 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 580389564..f67691d0a 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -82,8 +82,9 @@ using namespace std;
using namespace TheISA;
using namespace ThePipeline;
-InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
- CpuPort(_cacheUnit->name() + "-cache-port", _cacheUnit->cpu),
+InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
+ const std::string& name) :
+ CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu),
cacheUnit(_cacheUnit)
{ }
@@ -230,8 +231,8 @@ InOrderCPU::InOrderCPU(Params *params)
stageWidth(params->stageWidth),
resPool(new ResourcePool(this, params)),
timeBuffer(2 , 2),
- dataPort(resPool->getDataUnit()),
- instPort(resPool->getInstUnit()),
+ dataPort(resPool->getDataUnit(), ".dcache_port"),
+ instPort(resPool->getInstUnit(), ".icache_port"),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
system(params->system),
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 615d0eb90..3103201dd 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -165,7 +165,7 @@ class InOrderCPU : public BaseCPU
public:
/** Default constructor. */
- CachePort(CacheUnit *_cacheUnit);
+ CachePort(CacheUnit *_cacheUnit, const std::string& name);
protected:
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 41128110b..b1fd12a2e 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -141,7 +141,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
- : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
+ : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
{ }
protected:
@@ -168,7 +168,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
- : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
+ : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
{ }
protected:
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0886b276f..fc6724939 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -105,7 +105,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
simulate_data_stalls(p->simulate_data_stalls),
simulate_inst_stalls(p->simulate_inst_stalls),
- icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
+ icachePort(name() + ".icache_port", this),
+ dcachePort(name() + ".dcache_port", this),
fastmem(p->fastmem)
{
_status = Idle;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 95edea0b6..b6b78c5db 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -178,7 +178,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
IcachePort(TimingSimpleCPU *_cpu)
- : TimingCPUPort(_cpu->name() + "-iport", _cpu),
+ : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
tickEvent(_cpu)
{ }
@@ -206,7 +206,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
DcachePort(TimingSimpleCPU *_cpu)
- : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
+ : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
+ tickEvent(_cpu)
{ }
protected: