diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/testers/memtest/memtest.cc | 5 | ||||
| -rw-r--r-- | src/cpu/testers/memtest/memtest.hh | 2 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 2d0131a92..dffaa71ed 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -125,6 +125,7 @@ MemTest::MemTest(const Params *p) tickEvent(this), cachePort("test", this), funcPort("functional", this), + funcProxy(funcPort), retryPkt(NULL), // mainMem(main_mem), // checkMem(check_mem), @@ -237,7 +238,7 @@ MemTest::completeRequest(PacketPtr pkt) exitSimLoop("maximum number of loads reached"); } else { assert(pkt->isWrite()); - funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize()); + funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize()); numWrites++; numWritesStat++; } @@ -349,7 +350,7 @@ MemTest::tick() outstandingAddrs.insert(paddr); // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin - funcPort.readBlob(req->getPaddr(), result, req->getSize()); + funcProxy.readBlob(req->getPaddr(), result, req->getSize()); DPRINTF(MemTest, "id %d initiating %sread at addr %x (blk %x) expecting %x\n", diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 208b34caf..c56a37574 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -38,6 +38,7 @@ #include "base/statistics.hh" #include "mem/mem_object.hh" #include "mem/port.hh" +#include "mem/port_proxy.hh" #include "params/MemTest.hh" #include "sim/eventq.hh" #include "sim/sim_exit.hh" @@ -108,6 +109,7 @@ class MemTest : public MemObject CpuPort cachePort; CpuPort funcPort; + PortProxy funcProxy; class MemTestSenderState : public Packet::SenderState, public FastAlloc { |