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-rw-r--r--src/cpu/BaseCPU.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 4fc2ebf1b..5e1a0a961 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -221,8 +221,9 @@ class BaseCPU(MemObject):
elif buildEnv['TARGET_ISA'] == 'alpha':
self.interrupts = AlphaInterrupts()
elif buildEnv['TARGET_ISA'] == 'x86':
- _localApic = X86LocalApic(pio_addr=0x2000000000000000)
- self.interrupts = _localApic
+ self.interrupts = X86LocalApic(clock = Parent.clock * 16,
+ pio_addr=0x2000000000000000)
+ _localApic = self.interrupts
elif buildEnv['TARGET_ISA'] == 'mips':
self.interrupts = MipsInterrupts()
elif buildEnv['TARGET_ISA'] == 'arm':