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-rw-r--r--src/cpu/SConscript8
-rw-r--r--src/cpu/activity.cc6
-rw-r--r--src/cpu/base.cc4
-rw-r--r--src/cpu/base.hh1
-rw-r--r--src/cpu/exetrace.hh3
-rw-r--r--src/cpu/o3/alpha/cpu_impl.hh3
-rw-r--r--src/cpu/o3/commit_impl.hh3
-rw-r--r--src/cpu/o3/sparc/cpu_impl.hh1
-rw-r--r--src/cpu/ozone/cpu_impl.hh7
-rw-r--r--src/cpu/ozone/inorder_back_end_impl.hh4
-rw-r--r--src/cpu/simple/base.cc3
-rw-r--r--src/cpu/simple/base.hh3
12 files changed, 16 insertions, 30 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 5771a7904..4d4b7574c 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -54,18 +54,18 @@ execfile(models_db.srcnode().abspath)
exec_sig_template = '''
virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
-{ panic("initiateAcc not defined!"); };
+{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
virtual Fault completeAcc(Packet *pkt, %s *xc,
Trace::InstRecord *traceData) const
-{ panic("completeAcc not defined!"); };
+{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
'''
mem_ini_sig_template = '''
-virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); };
+virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
'''
mem_comp_sig_template = '''
-virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; };
+virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
'''
# Generate a temporary CPU list, including the CheckerCPU if
diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc
index 9a0f6d98d..15e0556ad 100644
--- a/src/cpu/activity.cc
+++ b/src/cpu/activity.cc
@@ -28,6 +28,8 @@
* Authors: Kevin Lim
*/
+#include <cstring>
+
#include "base/timebuf.hh"
#include "cpu/activity.hh"
@@ -37,7 +39,7 @@ ActivityRecorder::ActivityRecorder(int num_stages, int longest_latency,
activityCount(activity), numStages(num_stages)
{
stageActive = new bool[numStages];
- memset(stageActive, 0, numStages);
+ std::memset(stageActive, 0, numStages);
}
void
@@ -114,7 +116,7 @@ void
ActivityRecorder::reset()
{
activityCount = 0;
- memset(stageActive, 0, numStages);
+ std::memset(stageActive, 0, numStages);
for (int i = 0; i < longestLatency + 1; ++i)
activityBuffer.advance();
}
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index b03bc19a5..deb4e02c4 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -96,7 +96,7 @@ CPUProgressEvent::description()
#if FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
- : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true),
+ : MemObject(p->name), clock(p->clock), instCnt(0),
params(p), number_of_threads(p->numberOfThreads), system(p->system),
phase(p->phase)
#else
@@ -334,7 +334,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
#if FULL_SYSTEM
interrupts = oldCPU->interrupts;
- checkInterrupts = oldCPU->checkInterrupts;
for (int i = 0; i < threadContexts.size(); ++i)
threadContexts[i]->profileClear();
@@ -371,7 +370,6 @@ BaseCPU::post_interrupt(int int_type)
void
BaseCPU::post_interrupt(int int_num, int index)
{
- checkInterrupts = true;
interrupts.post(int_num, index);
}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 89c7d9dda..3ae9c60b6 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -106,7 +106,6 @@ class BaseCPU : public MemObject
virtual void post_interrupt(int int_num, int index);
virtual void clear_interrupt(int int_num, int index);
virtual void clear_interrupts();
- bool checkInterrupts;
bool check_interrupts(ThreadContext * tc) const
{ return interrupts.check_interrupts(tc); }
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 6562e5265..a825f6a82 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -32,6 +32,7 @@
#ifndef __EXETRACE_HH__
#define __EXETRACE_HH__
+#include <cstring>
#include <fstream>
#include <vector>
@@ -169,7 +170,7 @@ InstRecord::setRegs(const IntRegFile &regs)
if (!iregs)
iregs = new iRegFile;
- memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
+ std::memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
regs_valid = true;
}
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 98fd0699a..980e70fdd 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -217,8 +217,6 @@ AlphaO3CPU<Impl>::hwrei(unsigned tid)
this->thread[tid]->kernelStats->hwrei();
- this->checkInterrupts = true;
-
// FIXME: XXX check for interrupts? XXX
return NoFault;
}
@@ -270,7 +268,6 @@ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
this->interrupts.updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
- this->checkInterrupts = false;
this->trap(interrupt, 0);
}
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 96f094926..483c2f71b 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -671,8 +671,7 @@ DefaultCommit<Impl>::commit()
} else {
DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
}
- } else if (cpu->checkInterrupts &&
- cpu->check_interrupts(cpu->tcBase(0)) &&
+ } else if (cpu->check_interrupts(cpu->tcBase(0)) &&
commitStatus[0] != TrapPending &&
!trapSquash[0] &&
!tcSquash[0]) {
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index 536a620bf..66bf7d1c0 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -245,7 +245,6 @@ SparcO3CPU<Impl>::processInterrupts(Fault interrupt)
this->interrupts.updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
- this->checkInterrupts = false;
this->trap(interrupt, 0);
}
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index accc8d294..a854de8de 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -182,10 +182,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
globalSeqNum = 1;
-#if FULL_SYSTEM
- checkInterrupts = false;
-#endif
-
lockFlag = 0;
// Setup rename table, initializing all values to ready.
@@ -684,8 +680,6 @@ OzoneCPU<Impl>::hwrei()
lockAddrList.clear();
thread.kernelStats->hwrei();
- checkInterrupts = true;
-
// FIXME: XXX check for interrupts? XXX
return NoFault;
}
@@ -704,7 +698,6 @@ OzoneCPU<Impl>::processInterrupts()
if (interrupt != NoFault) {
this->interrupts.updateIntrInfo(thread.getTC());
- this->checkInterrupts = false;
interrupt->invoke(thread.getTC());
}
}
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 87bf0a7a2..84f935a72 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -88,7 +88,6 @@ InorderBackEnd<Impl>::checkInterrupts()
int ipl = 0;
int summary = 0;
- cpu->checkInterrupts = false;
if (thread->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
@@ -151,8 +150,7 @@ InorderBackEnd<Impl>::tick()
// I'm waiting for it to drain. (for now just squash)
#if FULL_SYSTEM
if (interruptBlocked ||
- (cpu->checkInterrupts &&
- cpu->check_interrupts(tc))) {
+ cpu->check_interrupts(tc)) {
if (!robEmpty()) {
interruptBlocked = true;
//AlphaDep
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 14fefe103..b8d1f3bed 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -311,12 +311,11 @@ void
BaseSimpleCPU::checkForInterrupts()
{
#if FULL_SYSTEM
- if (checkInterrupts && check_interrupts(tc)) {
+ if (check_interrupts(tc)) {
Fault interrupt = interrupts.getInterrupt(tc);
if (interrupt != NoFault) {
interrupts.updateIntrInfo(tc);
- checkInterrupts = false;
interrupt->invoke(tc);
}
}
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index c39bfa9cd..31fd00977 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -186,7 +186,8 @@ class BaseSimpleCPU : public BaseCPU
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
- Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
+ Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
+ M5_DUMMY_RETURN}
void prefetch(Addr addr, unsigned flags)
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-14 03:56:54 +0000