summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base.cc12
-rw-r--r--src/cpu/base.hh3
-rw-r--r--src/cpu/memtest/memtest.cc10
-rw-r--r--src/cpu/memtest/memtest.hh4
-rw-r--r--src/cpu/o3/alpha/cpu_builder.cc2
-rw-r--r--src/cpu/o3/alpha/cpu_impl.hh18
-rw-r--r--src/cpu/o3/cpu.cc2
-rw-r--r--src/cpu/o3/fetch.hh2
-rw-r--r--src/cpu/o3/fetch_impl.hh9
-rw-r--r--src/cpu/o3/lsq.hh2
-rw-r--r--src/cpu/o3/lsq_impl.hh10
-rw-r--r--src/cpu/o3/mips/cpu_builder.cc2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh5
-rw-r--r--src/cpu/simple/atomic.cc18
-rw-r--r--src/cpu/simple/atomic.hh2
-rw-r--r--src/cpu/simple/timing.cc36
-rw-r--r--src/cpu/simple/timing.hh4
-rw-r--r--src/cpu/simple_thread.cc17
-rw-r--r--src/cpu/thread_context.hh4
-rw-r--r--src/cpu/thread_state.cc35
-rw-r--r--src/cpu/thread_state.hh15
22 files changed, 146 insertions, 68 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4c243a2e9..7cbbb0b96 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -97,11 +97,13 @@ CPUProgressEvent::description()
#if FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
: MemObject(p->name), clock(p->clock), checkInterrupts(true),
- params(p), number_of_threads(p->numberOfThreads), system(p->system)
+ params(p), number_of_threads(p->numberOfThreads), system(p->system),
+ phase(p->phase)
#else
BaseCPU::BaseCPU(Params *p)
: MemObject(p->name), clock(p->clock), params(p),
- number_of_threads(p->numberOfThreads), system(p->system)
+ number_of_threads(p->numberOfThreads), system(p->system),
+ phase(p->phase)
#endif
{
// currentTick = curTick;
@@ -257,8 +259,9 @@ BaseCPU::regStats()
Tick
BaseCPU::nextCycle()
{
- Tick next_tick = curTick + clock - 1;
+ Tick next_tick = curTick - phase + clock - 1;
next_tick -= (next_tick % clock);
+ next_tick += phase;
return next_tick;
}
@@ -266,11 +269,12 @@ Tick
BaseCPU::nextCycle(Tick begin_tick)
{
Tick next_tick = begin_tick;
+ next_tick -= (next_tick % clock);
+ next_tick += phase;
while (next_tick < curTick)
next_tick += clock;
- next_tick -= (next_tick % clock);
assert(next_tick >= curTick);
return next_tick;
}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 788f77e3a..1d9b6a93b 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -153,6 +153,7 @@ class BaseCPU : public MemObject
Tick functionTraceStart;
System *system;
int cpu_id;
+ Tick phase;
#if FULL_SYSTEM
Tick profile;
@@ -209,6 +210,8 @@ class BaseCPU : public MemObject
System *system;
+ Tick phase;
+
#if FULL_SYSTEM
/**
* Serialize this object to the given output stream.
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 91e073cf0..180f41541 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -81,8 +81,13 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
void
MemTest::CpuPort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("MemTest doesn't expect recvStatusChange callback!");
}
@@ -145,6 +150,9 @@ MemTest::MemTest(const string &name,
// thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
curTick = 0;
+ cachePort.snoopRangeSent = false;
+ funcPort.snoopRangeSent = true;
+
// Needs to be masked off once we know the block size.
traceBlockAddr = _traceAddr;
baseAddr1 = 0x100000;
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 2694efd39..7bf34d827 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -100,6 +100,8 @@ class MemTest : public MemObject
: Port(_name, _memtest), memtest(_memtest)
{ }
+ bool snoopRangeSent;
+
protected:
virtual bool recvTiming(PacketPtr pkt);
@@ -120,6 +122,8 @@ class MemTest : public MemObject
CpuPort cachePort;
CpuPort funcPort;
+ bool snoopRangeSent;
+
class MemTestSenderState : public Packet::SenderState
{
public:
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index 09ccc7f65..5a375a4b8 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -48,6 +48,7 @@ class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
Param<int> clock;
+ Param<int> phase;
Param<int> numThreads;
Param<int> activity;
@@ -158,6 +159,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(numThreads, "number of HW thread contexts"),
INIT_PARAM_DFLT(activity, "Initial activity count", 0),
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index b2ef78360..98fd0699a 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -116,24 +116,6 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
#if FULL_SYSTEM
// Setup quiesce event.
this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc);
-
- Port *mem_port;
- FunctionalPort *phys_port;
- VirtualPort *virt_port;
- phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
- name(), i));
- mem_port = this->system->physmem->getPort("functional");
- mem_port->setPeer(phys_port);
- phys_port->setPeer(mem_port);
-
- virt_port = new VirtualPort(csprintf("%s-%d-vport",
- name(), i));
- mem_port = this->system->physmem->getPort("functional");
- mem_port->setPeer(virt_port);
- virt_port->setPeer(mem_port);
-
- this->thread[i]->setPhysPort(phys_port);
- this->thread[i]->setVirtPort(virt_port);
#endif
// Give the thread the TC.
this->thread[i]->tc = tc;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 580816372..3dc353a9f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -497,6 +497,8 @@ FullO3CPU<Impl>::init()
}
#if FULL_SYSTEM
+ src_tc->init();
+
TheISA::initCPU(src_tc, src_tc->readCpuId());
#endif
}
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index cc9a8abf5..04016347a 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -83,6 +83,8 @@ class DefaultFetch
: Port(_fetch->name() + "-iport"), fetch(_fetch)
{ }
+ bool snoopRangeSent;
+
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 25faa407e..63d22b293 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -70,8 +70,13 @@ template<class Impl>
void
DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("DefaultFetch doesn't expect recvStatusChange callback!");
}
@@ -287,6 +292,8 @@ DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
// Name is finally available, so create the port.
icachePort = new IcachePort(this);
+ icachePort->snoopRangeSent = false;
+
#if USE_CHECKER
if (cpu->checker) {
cpu->checker->setIcachePort(icachePort);
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 6b12d75b4..7559a36d5 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -298,6 +298,8 @@ class LSQ {
: lsq(_lsq)
{ }
+ bool snoopRangeSent;
+
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 5e7945c1c..6758e51c8 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -53,9 +53,13 @@ template <class Impl>
void
LSQ<Impl>::DcachePort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
-
+ }
panic("O3CPU doesn't expect recvStatusChange callback!");
}
@@ -97,6 +101,8 @@ LSQ<Impl>::LSQ(Params *params)
{
DPRINTF(LSQ, "Creating LSQ object.\n");
+ dcachePort.snoopRangeSent = false;
+
//**********************************************/
//************ Handle SMT Parameters ***********/
//**********************************************/
diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc
index ee9f2b48d..66741aee9 100644
--- a/src/cpu/o3/mips/cpu_builder.cc
+++ b/src/cpu/o3/mips/cpu_builder.cc
@@ -49,6 +49,7 @@ class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
Param<int> clock;
+Param<int> phase;
Param<int> numThreads;
Param<int> activity;
@@ -146,6 +147,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(numThreads, "number of HW thread contexts"),
INIT_PARAM_DFLT(activity, "Initial activity count", 0),
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index daee2fc7d..031f36480 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -91,6 +91,8 @@ class O3ThreadContext : public ThreadContext
virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
void delVirtPort(VirtualPort *vp);
+
+ virtual void init() { thread->init(); }
#else
virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 8d623f5b8..0180756e3 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -41,12 +41,9 @@ O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc)
return thread->getVirtPort();
VirtualPort *vp;
- Port *mem_port;
vp = new VirtualPort("tc-vport", src_tc);
- mem_port = cpu->system->physmem->getPort("functional");
- mem_port->setPeer(vp);
- vp->setPeer(mem_port);
+ thread->connectToMemFunc(vp);
return vp;
}
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 58dc1fe5f..cd335e36d 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -77,6 +77,9 @@ AtomicSimpleCPU::init()
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
+ // initialize the mem pointers
+ tc->init();
+
// initialize CPU, including PC
TheISA::initCPU(tc, tc->readCpuId());
}
@@ -94,7 +97,7 @@ Tick
AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
//Snooping a coherence request, just return
- return curTick;
+ return 0;
}
void
@@ -107,8 +110,13 @@ AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
void
AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
}
@@ -127,6 +135,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
{
_status = Idle;
+ icachePort.snoopRangeSent = false;
+ dcachePort.snoopRangeSent = false;
+
ifetch_req = new Request();
ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
@@ -512,6 +523,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
#endif // FULL_SYSTEM
Param<int> clock;
+ Param<int> phase;
Param<bool> defer_registration;
Param<int> width;
@@ -547,6 +559,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(width, "cpu width"),
INIT_PARAM(function_trace, "Enable function trace"),
@@ -567,6 +580,7 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
params->max_loads_all_threads = max_loads_all_threads;
params->progress_interval = progress_interval;
params->deferRegistration = defer_registration;
+ params->phase = phase;
params->clock = clock;
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 166a18127..0df6fe079 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -90,6 +90,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
: Port(_name, _cpu), cpu(_cpu)
{ }
+ bool snoopRangeSent;
+
protected:
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index db2c940c0..aa23a00e8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -59,6 +59,9 @@ TimingSimpleCPU::init()
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
+ // initialize the mem pointers
+ tc->init();
+
// initialize CPU, including PC
TheISA::initCPU(tc, tc->readCpuId());
}
@@ -82,8 +85,13 @@ TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
void
TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
}
@@ -101,6 +109,10 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
cpu_id(p->cpu_id)
{
_status = Idle;
+
+ icachePort.snoopRangeSent = false;
+ dcachePort.snoopRangeSent = false;
+
ifetch_pkt = dcache_pkt = NULL;
drainEvent = NULL;
fetchEvent = NULL;
@@ -160,7 +172,7 @@ TimingSimpleCPU::resume()
fetchEvent =
new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
- fetchEvent->schedule(curTick);
+ fetchEvent->schedule(nextCycle());
}
changeState(SimObject::Running);
@@ -232,7 +244,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
// kick things off by initiating the fetch of the next instruction
fetchEvent =
new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
- fetchEvent->schedule(curTick + cycles(delay));
+ fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
}
@@ -281,6 +293,8 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// memory system takes ownership of packet
dcache_pkt = NULL;
}
+ } else {
+ delete req;
}
// This will need a new way to tell if it has a dcache attached.
@@ -366,6 +380,8 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_pkt = NULL;
}
}
+ } else {
+ delete req;
}
// This will need a new way to tell if it's hooked up to a cache or not.
@@ -448,6 +464,8 @@ TimingSimpleCPU::fetch()
ifetch_pkt = NULL;
}
} else {
+ delete ifetch_req;
+ delete ifetch_pkt;
// fetch fault: advance directly to next instruction (fault handler)
advanceInst(fault);
}
@@ -481,13 +499,13 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
_status = Running;
- delete pkt->req;
- delete pkt;
-
numCycles += curTick - previousTick;
previousTick = curTick;
if (getState() == SimObject::Draining) {
+ delete pkt->req;
+ delete pkt;
+
completeDrain();
return;
}
@@ -519,6 +537,9 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
postExecute();
advanceInst(fault);
}
+
+ delete pkt->req;
+ delete pkt;
}
void
@@ -674,6 +695,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
#endif // FULL_SYSTEM
Param<int> clock;
+ Param<int> phase;
Param<bool> defer_registration;
Param<int> width;
@@ -709,6 +731,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(width, "cpu width"),
INIT_PARAM(function_trace, "Enable function trace"),
@@ -730,6 +753,7 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
params->progress_interval = progress_interval;
params->deferRegistration = defer_registration;
params->clock = clock;
+ params->phase = phase;
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->system = system;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 408fa315e..fe5d03666 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -82,6 +82,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
: Port(_name, _cpu), cpu(_cpu), lat(_lat)
{ }
+ bool snoopRangeSent;
+
protected:
virtual Tick recvAtomic(PacketPtr pkt);
@@ -166,8 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
-
-
int cpu_id;
Tick previousTick;
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 1edcbf352..13d0e2e29 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -91,18 +91,6 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
} else {
kernelStats = NULL;
}
- Port *mem_port;
- physPort = new FunctionalPort(csprintf("%s-%d-funcport",
- cpu->name(), tid));
- mem_port = system->physmem->getPort("functional");
- mem_port->setPeer(physPort);
- physPort->setPeer(mem_port);
-
- virtPort = new VirtualPort(csprintf("%s-%d-vport",
- cpu->name(), tid));
- mem_port = system->physmem->getPort("functional");
- mem_port->setPeer(virtPort);
- virtPort->setPeer(mem_port);
}
#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
@@ -309,10 +297,7 @@ SimpleThread::getVirtPort(ThreadContext *src_tc)
return virtPort;
VirtualPort *vp = new VirtualPort("tc-vport", src_tc);
- Port *mem_port = getMemFuncPort();
-
- mem_port->setPeer(vp);
- vp->setPeer(mem_port);
+ connectToMemFunc(vp);
return vp;
}
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 1e6a907f8..baeb7a8be 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -133,6 +133,8 @@ class ThreadContext
virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
virtual void delVirtPort(VirtualPort *vp) = 0;
+
+ virtual void init() = 0;
#else
virtual TranslatingPort *getMemPort() = 0;
@@ -305,6 +307,8 @@ class ProxyThreadContext : public ThreadContext
VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
+
+ void init() {actualTC->init(); }
#else
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 8602f8a50..9cac4fd26 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -39,6 +39,7 @@
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#include "cpu/quiesce_event.hh"
+#include "mem/vport.hh"
#endif
#if FULL_SYSTEM
@@ -111,6 +112,28 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
}
#if FULL_SYSTEM
+void
+ThreadState::init()
+{
+ initPhysPort();
+ initVirtPort();
+}
+
+void
+ThreadState::initPhysPort()
+{
+ physPort = new FunctionalPort(csprintf("%s-%d-funcport",
+ baseCpu->name(), tid));
+ connectToMemFunc(physPort);
+}
+
+void
+ThreadState::initVirtPort()
+{
+ virtPort = new VirtualPort(csprintf("%s-%d-vport",
+ baseCpu->name(), tid));
+ connectToMemFunc(virtPort);
+}
void
ThreadState::profileClear()
@@ -138,17 +161,14 @@ ThreadState::getMemPort()
baseCpu->name(), tid),
process->pTable, false);
- Port *func_port = getMemFuncPort();
-
- func_port->setPeer(port);
- port->setPeer(func_port);
+ connectToMemFunc(port);
return port;
}
#endif
-Port *
-ThreadState::getMemFuncPort()
+void
+ThreadState::connectToMemFunc(Port *port)
{
Port *dcache_port, *func_mem_port;
@@ -161,5 +181,6 @@ ThreadState::getMemFuncPort()
func_mem_port = mem_object->getPort("functional");
assert(func_mem_port != NULL);
- return func_mem_port;
+ func_mem_port->setPeer(port);
+ port->setPeer(func_mem_port);
}
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 0a0af8b71..1844be8b7 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -91,6 +91,12 @@ struct ThreadState {
Tick readLastSuspend() { return lastSuspend; }
#if FULL_SYSTEM
+ void init();
+
+ void initPhysPort();
+
+ void initVirtPort();
+
void dumpFuncProfile();
EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
@@ -141,12 +147,11 @@ struct ThreadState {
/** Sets the status of this thread. */
void setStatus(Status new_status) { _status = new_status; }
- protected:
- /** Gets a functional port from the memory object that's connected
- * to the CPU. */
- Port *getMemFuncPort();
-
public:
+ /** Connects port to the functional port of the memory object
+ * below the CPU. */
+ void connectToMemFunc(Port *port);
+
/** Number of instructions committed. */
Counter numInst;
/** Stat for number instructions committed. */
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 06:27:32 +0000