summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/exetrace.cc33
-rw-r--r--src/cpu/exetrace.hh26
-rw-r--r--src/cpu/o3/commit_impl.hh3
-rw-r--r--src/cpu/simple/base.cc4
4 files changed, 37 insertions, 29 deletions
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index e34ae3731..683cb138e 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -123,8 +123,10 @@ inline void printLevelHeader(ostream & os, int level)
#endif
void
-Trace::InstRecord::dump(ostream &outs)
+Trace::InstRecord::dump()
{
+ ostream &outs = Trace::output();
+
DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
if (flags[PRINT_REG_DELTA])
{
@@ -194,7 +196,7 @@ Trace::InstRecord::dump(ostream &outs)
bool is_trace_system = true;
#endif
if (is_trace_system) {
- ccprintf(outs, "%7d ) ", cycle);
+ ccprintf(outs, "%7d ) ", when);
outs << "0x" << hex << PC << ":\t";
if (staticInst->isLoad()) {
outs << "<RD 0x" << hex << addr;
@@ -206,8 +208,8 @@ Trace::InstRecord::dump(ostream &outs)
outs << endl;
}
} else {
- if (flags[PRINT_CYCLE])
- ccprintf(outs, "%7d: ", cycle);
+ if (flags[PRINT_TICKS])
+ ccprintf(outs, "%7d: ", when);
outs << thread->getCpuPtr()->name() << " ";
@@ -324,7 +326,7 @@ Trace::InstRecord::dump(ostream &outs)
// We took a trap on a micro-op...
if (wasMicro && !staticInst->isMicroOp())
{
- // let's skip comparing this cycle
+ // let's skip comparing this tick
while (!compared)
if (shared_data->flags == OWN_M5) {
shared_data->flags = OWN_LEGION;
@@ -411,8 +413,14 @@ Trace::InstRecord::dump(ostream &outs)
if(shared_data->y !=
thread->readIntReg(NumIntArchRegs + 1))
diffY = true;
- if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR))
+ if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) {
diffFsr = true;
+ if (mbits(shared_data->fsr, 63,10) ==
+ mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) {
+ thread->setMiscReg(MISCREG_FSR, shared_data->fsr);
+ diffFsr = false;
+ }
+ }
//if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
if(shared_data->ccr !=
thread->readIntReg(NumIntArchRegs + 2))
@@ -450,16 +458,13 @@ Trace::InstRecord::dump(ostream &outs)
diffTlb = true;
}
- if ((diffPC || diffCC || diffInst || diffIntRegs ||
+ if (diffPC || diffCC || diffInst || diffIntRegs ||
diffFpRegs || diffTpc || diffTnpc || diffTstate ||
diffTt || diffHpstate || diffHtstate || diffHtba ||
diffPstate || diffY || diffCcr || diffTl || diffFsr ||
diffGl || diffAsi || diffPil || diffCwp || diffCansave ||
diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
- && !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
- && !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
- && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1)
- ) {
+ {
outs << "Differences found between M5 and Legion:";
if (diffPC)
@@ -639,7 +644,7 @@ Trace::InstRecord::dump(ostream &outs)
char label[8];
sprintf(label, "%%f%d", x);
printRegPair(outs, label,
- thread->readFloatRegBits(x,FloatRegFile::DoubleWidth),
+ thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth),
shared_data->fpregs[x]);
}
}
@@ -667,7 +672,7 @@ Trace::InstRecord::dump(ostream &outs)
}
diffcount++;
- if (diffcount > 2)
+ if (diffcount > 3)
fatal("Differences found between Legion and M5\n");
} else
diffcount = 0;
@@ -745,7 +750,7 @@ Trace::InstRecord::setParams()
{
flags[TRACE_MISSPEC] = exe_trace_spec;
- flags[PRINT_CYCLE] = exe_trace_print_cycle;
+ flags[PRINT_TICKS] = exe_trace_print_cycle;
flags[PRINT_OP_CLASS] = exe_trace_print_opclass;
flags[PRINT_THREAD_NUM] = exe_trace_print_thread;
flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index a825f6a82..95a142f3c 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -36,22 +36,24 @@
#include <fstream>
#include <vector>
-#include "sim/host.hh"
-#include "cpu/inst_seq.hh" // for InstSeqNum
#include "base/trace.hh"
-#include "cpu/thread_context.hh"
+#include "cpu/inst_seq.hh" // for InstSeqNum
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "sim/host.hh"
class ThreadContext;
namespace Trace {
-class InstRecord : public Record
+class InstRecord
{
protected:
typedef TheISA::IntRegFile IntRegFile;
+ Tick when;
+
// The following fields are initialized by the constructor and
// thus guaranteed to be valid.
ThreadContext *thread;
@@ -95,10 +97,10 @@ class InstRecord : public Record
bool regs_valid;
public:
- InstRecord(Tick _cycle, ThreadContext *_thread,
+ InstRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr &_staticInst,
Addr _pc, bool spec)
- : Record(_cycle), thread(_thread),
+ : when(_when), thread(_thread),
staticInst(_staticInst), PC(_pc),
misspeculating(spec)
{
@@ -110,9 +112,7 @@ class InstRecord : public Record
cp_seq_valid = false;
}
- virtual ~InstRecord() { }
-
- virtual void dump(std::ostream &outs);
+ ~InstRecord() { }
void setAddr(Addr a) { addr = a; addr_valid = true; }
@@ -136,11 +136,11 @@ class InstRecord : public Record
void setRegs(const IntRegFile &regs);
- void finalize() { theLog.append(this); }
+ void dump();
enum InstExecFlagBits {
TRACE_MISSPEC = 0,
- PRINT_CYCLE,
+ PRINT_TICKS,
PRINT_OP_CLASS,
PRINT_THREAD_NUM,
PRINT_RESULT_DATA,
@@ -176,13 +176,13 @@ InstRecord::setRegs(const IntRegFile &regs)
inline
InstRecord *
-getInstRecord(Tick cycle, ThreadContext *tc,
+getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst,
Addr pc)
{
if (DTRACE(InstExec) &&
(InstRecord::traceMisspec() || !tc->misspeculating())) {
- return new InstRecord(cycle, tc, staticInst, pc,
+ return new InstRecord(when, tc, staticInst, pc,
tc->misspeculating());
}
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f1457922c..18fb2aaa3 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1106,7 +1106,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
if (head_inst->traceData) {
head_inst->traceData->setFetchSeq(head_inst->seqNum);
head_inst->traceData->setCPSeq(thread[tid]->numInst);
- head_inst->traceData->finalize();
+ head_inst->traceData->dump();
+ delete head_inst->traceData;
head_inst->traceData = NULL;
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b8d1f3bed..80b137909 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -427,7 +427,9 @@ BaseSimpleCPU::postExecute()
traceFunctions(thread->readPC());
if (traceData) {
- traceData->finalize();
+ traceData->dump();
+ delete traceData;
+ traceData = NULL;
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-14 03:32:27 +0000