diff options
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/simple/atomic.cc | 28 | ||||
-rw-r--r-- | src/cpu/simple/base.cc | 2 | ||||
-rw-r--r-- | src/cpu/simple/timing.cc | 24 |
3 files changed, 16 insertions, 38 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 04a84c92a..ec629304b 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -126,31 +126,23 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p) // @todo fix me and get the real cpu iD!!! ifetch_req->setCpuNum(0); ifetch_req->setSize(sizeof(MachInst)); - ifetch_pkt = new Packet; - ifetch_pkt->cmd = Read; + ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); ifetch_pkt->dataStatic(&inst); - ifetch_pkt->req = ifetch_req; - ifetch_pkt->size = sizeof(MachInst); - ifetch_pkt->dest = Packet::Broadcast; data_read_req = new Request(true); // @todo fix me and get the real cpu iD!!! data_read_req->setCpuNum(0); data_read_req->setAsid(0); - data_read_pkt = new Packet; - data_read_pkt->cmd = Read; + data_read_pkt = new Packet(data_read_req, Packet::ReadReq, + Packet::Broadcast); data_read_pkt->dataStatic(&dataReg); - data_read_pkt->req = data_read_req; - data_read_pkt->dest = Packet::Broadcast; data_write_req = new Request(true); // @todo fix me and get the real cpu iD!!! data_write_req->setCpuNum(0); data_write_req->setAsid(0); - data_write_pkt = new Packet; - data_write_pkt->cmd = Write; - data_write_pkt->req = data_write_req; - data_write_pkt->dest = Packet::Broadcast; + data_write_pkt = new Packet(data_write_req, Packet::WriteReq, + Packet::Broadcast); } @@ -260,13 +252,12 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { data_read_pkt->reset(); - data_read_pkt->addr = data_read_req->getPaddr(); - data_read_pkt->size = sizeof(T); + data_read_pkt->reinitFromRequest(); dcache_complete = dcachePort.sendAtomic(data_read_pkt); dcache_access = true; - assert(data_read_pkt->result == Success); + assert(data_read_pkt->result == Packet::Success); data = data_read_pkt->get<T>(); } @@ -342,13 +333,12 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) data_write_pkt->reset(); data = htog(data); data_write_pkt->dataStatic(&data); - data_write_pkt->addr = data_write_req->getPaddr(); - data_write_pkt->size = sizeof(T); + data_write_pkt->reinitFromRequest(); dcache_complete = dcachePort.sendAtomic(data_write_pkt); dcache_access = true; - assert(data_write_pkt->result == Success); + assert(data_write_pkt->result == Packet::Success); if (res && data_write_req->getFlags() & LOCKED) { *res = data_write_req->getScResult(); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 30c002ed5..077df8134 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -372,7 +372,7 @@ BaseSimpleCPU::setupFetchPacket(Packet *ifetch_pkt) Fault fault = cpuXC->translateInstReq(ifetch_req); if (fault == NoFault) { - ifetch_pkt->addr = ifetch_req->getPaddr(); + ifetch_pkt->reinitFromRequest(); } return fault; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 70b88c4b1..d57935ed0 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -187,13 +187,9 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { - Packet *data_read_pkt = new Packet; - data_read_pkt->cmd = Read; - data_read_pkt->req = data_read_req; + Packet *data_read_pkt = + new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast); data_read_pkt->dataDynamic<T>(new T); - data_read_pkt->addr = data_read_req->getPaddr(); - data_read_pkt->size = sizeof(T); - data_read_pkt->dest = Packet::Broadcast; if (!dcachePort.sendTiming(data_read_pkt)) { _status = DcacheRetry; @@ -268,14 +264,10 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) Fault fault = cpuXC->translateDataWriteReq(data_write_req); // Now do the access. if (fault == NoFault) { - Packet *data_write_pkt = new Packet; - data_write_pkt->cmd = Write; - data_write_pkt->req = data_write_req; + Packet *data_write_pkt = + new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast); data_write_pkt->allocate(); - data_write_pkt->size = sizeof(T); data_write_pkt->set(data); - data_write_pkt->addr = data_write_req->getPaddr(); - data_write_pkt->dest = Packet::Broadcast; if (!dcachePort.sendTiming(data_write_pkt)) { _status = DcacheRetry; @@ -350,12 +342,8 @@ TimingSimpleCPU::fetch() Request *ifetch_req = new Request(true); ifetch_req->setSize(sizeof(MachInst)); - ifetch_pkt = new Packet; - ifetch_pkt->cmd = Read; + ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); ifetch_pkt->dataStatic(&inst); - ifetch_pkt->req = ifetch_req; - ifetch_pkt->size = sizeof(MachInst); - ifetch_pkt->dest = Packet::Broadcast; Fault fault = setupFetchPacket(ifetch_pkt); if (fault == NoFault) { @@ -441,7 +429,7 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt) { // received a response from the dcache: complete the load or store // instruction - assert(pkt->result == Success); + assert(pkt->result == Packet::Success); assert(_status == DcacheWaitResponse); _status = Running; |