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-rw-r--r--src/cpu/checker/thread_context.hh8
-rw-r--r--src/cpu/inorder/cpu.cc13
-rw-r--r--src/cpu/inorder/cpu.hh4
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc15
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh2
-rw-r--r--src/cpu/inorder/thread_context.cc6
-rw-r--r--src/cpu/inorder/thread_context.hh10
-rw-r--r--src/cpu/o3/cpu.cc12
-rw-r--r--src/cpu/o3/cpu.hh4
-rw-r--r--src/cpu/o3/lsq.hh7
-rw-r--r--src/cpu/o3/lsq_impl.hh13
-rwxr-xr-xsrc/cpu/o3/thread_context.hh10
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh6
-rw-r--r--src/cpu/ozone/cpu.hh8
-rw-r--r--src/cpu/ozone/cpu_impl.hh18
-rw-r--r--src/cpu/simple/atomic.cc15
-rw-r--r--src/cpu/simple/atomic.hh11
-rw-r--r--src/cpu/simple/timing.cc15
-rw-r--r--src/cpu/simple/timing.hh2
-rw-r--r--src/cpu/simple_thread.cc8
-rw-r--r--src/cpu/simple_thread.hh4
-rw-r--r--src/cpu/thread_context.hh28
-rw-r--r--src/cpu/thread_state.cc102
-rw-r--r--src/cpu/thread_state.hh42
24 files changed, 111 insertions, 252 deletions
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 5bd3ed734..4eb3eabfd 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -97,12 +97,12 @@ class CheckerThreadContext : public ThreadContext
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
- FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+ PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); }
- VirtualPort *getVirtPort()
- { return actualTC->getVirtPort(); }
+ FSTranslatingPortProxy* getVirtProxy()
+ { return actualTC->getVirtProxy(); }
#else
- TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+ SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
#endif
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 232554db2..9614a5df2 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -53,7 +53,6 @@
#include "debug/RefCount.hh"
#include "debug/SkedCache.hh"
#include "debug/Quiesce.hh"
-#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
#include "sim/process.hh"
#include "sim/stat_control.hh"
@@ -766,6 +765,8 @@ InOrderCPU::init()
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
+ // Initialise the ThreadContext's memory proxies
+ thread[tid]->initMemProxies(thread[tid]->getTC());
}
#endif
@@ -888,16 +889,6 @@ InOrderCPU::processInterrupts(Fault interrupt)
trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
}
-
-void
-InOrderCPU::updateMemPorts()
-{
- // Update all ThreadContext's memory ports (Functional/Virtual
- // Ports)
- ThreadID size = thread.size();
- for (ThreadID i = 0; i < size; ++i)
- thread[i]->connectMemPorts(thread[i]->getTC());
-}
#endif
void
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 098909cb7..1559874cd 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -430,10 +430,6 @@ class InOrderCPU : public BaseCPU
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Update the Virt and Phys ports of all ThreadContexts to
- * reflect change in memory connections. */
- void updateMemPorts();
-
/** Check if this address is a valid instruction address. */
bool validInstAddr(Addr addr) { return true; }
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 73dd9c527..7fcab6893 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -145,21 +145,6 @@ CacheUnit::tlb()
}
-void
-CacheUnit::CachePort::setPeer(Port *port)
-{
- Port::setPeer(port);
-
-#if FULL_SYSTEM
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- if (cachePortUnit->resName == "dcache_port") {
- cachePortUnit->cpu->updateMemPorts();
- }
-
-#endif
-}
-
Port *
CacheUnit::getPort(const string &if_name, int idx)
{
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 6bb5868b1..78eff9991 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -95,8 +95,6 @@ class CacheUnit : public Resource
bool snoopRangeSent;
- void setPeer(Port *port);
-
protected:
/** Atomic version of receive. Panics. */
Tick recvAtomic(PacketPtr pkt);
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index af6e18291..82e681f04 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -39,10 +39,10 @@ using namespace TheISA;
#if FULL_SYSTEM
-VirtualPort *
-InOrderThreadContext::getVirtPort()
+FSTranslatingPortProxy*
+InOrderThreadContext::getVirtProxy()
{
- return thread->getVirtPort();
+ return thread->getVirtProxy();
}
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 7ec17cb77..5b67d7e8b 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -118,12 +118,12 @@ class InOrderThreadContext : public ThreadContext
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
- FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+ PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
- VirtualPort *getVirtPort();
+ FSTranslatingPortProxy* getVirtProxy();
- void connectMemPorts(ThreadContext *tc)
- { thread->connectMemPorts(tc); }
+ void initMemProxies(ThreadContext *tc)
+ { thread->initMemProxies(tc); }
/** Dumps the function profiling information.
* @todo: Implement.
@@ -147,7 +147,7 @@ class InOrderThreadContext : public ThreadContext
return this->thread->quiesceEvent;
}
#else
- TranslatingPort *getMemPort() { return thread->getMemPort(); }
+ SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); }
/** Returns a pointer to this thread's process. */
Process *getProcessPtr() { return thread->getProcessPtr(); }
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 94fc5cdf3..ee0c3a88a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -610,6 +610,8 @@ FullO3CPU<Impl>::init()
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
+ // Initialise the ThreadContext's memory proxies
+ thread[tid]->initMemProxies(thread[tid]->getTC());
}
#endif
@@ -974,16 +976,6 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
this->trap(interrupt, 0, NULL);
}
-template <class Impl>
-void
-FullO3CPU<Impl>::updateMemPorts()
-{
- // Update all ThreadContext's memory ports (Functional/Virtual
- // Ports)
- ThreadID size = thread.size();
- for (ThreadID i = 0; i < size; ++i)
- thread[i]->connectMemPorts(thread[i]->getTC());
-}
#endif
template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index b2606c1e2..652e6d99a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -395,10 +395,6 @@ class FullO3CPU : public BaseO3CPU
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Update the Virt and Phys ports of all ThreadContexts to
- * reflect change in memory connections. */
- void updateMemPorts();
-
/** Check if this address is a valid instruction address. */
bool validInstAddr(Addr addr) { return true; }
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 14917bc16..d01a6b0a4 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -305,8 +305,6 @@ class LSQ {
bool snoopRangeSent;
- virtual void setPeer(Port *port);
-
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
@@ -334,11 +332,6 @@ class LSQ {
/** D-cache port. */
DcachePort dcachePort;
-#if FULL_SYSTEM
- /** Tell the CPU to update the Phys and Virt ports. */
- void updateMemPorts() { cpu->updateMemPorts(); }
-#endif
-
protected:
/** The LSQ policy for SMT mode. */
LSQPolicy lsqPolicy;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index ef9167d8c..61dced14f 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -40,19 +40,6 @@
using namespace std;
-template<class Impl>
-void
-LSQ<Impl>::DcachePort::setPeer(Port *port)
-{
- Port::setPeer(port);
-
-#if FULL_SYSTEM
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- lsq->updateMemPorts();
-#endif
-}
-
template <class Impl>
Tick
LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 38c94439a..6ac745770 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -97,13 +97,15 @@ class O3ThreadContext : public ThreadContext
virtual TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
- virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+ virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
- virtual VirtualPort *getVirtPort();
+ virtual FSTranslatingPortProxy* getVirtProxy();
- virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
+ virtual void initMemProxies(ThreadContext *tc)
+ { thread->initMemProxies(tc); }
#else
- virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
+ virtual SETranslatingPortProxy* getMemProxy()
+ { return thread->getMemProxy(); }
/** Returns a pointer to this thread's process. */
virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 4888cf92e..4c2fee22d 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -49,10 +49,10 @@
#if FULL_SYSTEM
template <class Impl>
-VirtualPort *
-O3ThreadContext<Impl>::getVirtPort()
+FSTranslatingPortProxy*
+O3ThreadContext<Impl>::getVirtProxy()
{
- return thread->getVirtPort();
+ return thread->getVirtProxy();
}
template <class Impl>
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 1867a4c51..541fea44c 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -124,12 +124,12 @@ class OzoneCPU : public BaseCPU
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }
- FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+ PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
- VirtualPort *getVirtPort()
- { return thread->getVirtPort(); }
+ FSTranslatingPortProxy* getVirtProxy()
+ { return thread->getVirtProxy(); }
#else
- TranslatingPort *getMemPort() { return thread->getMemPort(); }
+ SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); }
Process *getProcessPtr() { return thread->getProcessPtr(); }
#endif
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index bb6e96ecc..273d46bdc 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -195,23 +195,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
backEnd->renameTable.copyFrom(thread.renameTable);
#if FULL_SYSTEM
- Port *mem_port;
- FunctionalPort *phys_port;
- VirtualPort *virt_port;
- phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
- name(), 0));
- mem_port = system->physmem->getPort("functional");
- mem_port->setPeer(phys_port);
- phys_port->setPeer(mem_port);
-
- virt_port = new VirtualPort(csprintf("%s-%d-vport",
- name(), 0));
- mem_port = system->physmem->getPort("functional");
- mem_port->setPeer(virt_port);
- virt_port->setPeer(mem_port);
-
- thread.setPhysPort(phys_port);
- thread.setVirtPort(virt_port);
+ thread.connectMemPorts(tc);
#endif
DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 5376519d4..b40109ec1 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -91,6 +91,9 @@ AtomicSimpleCPU::init()
// initialize CPU, including PC
TheISA::initCPU(tc, tc->contextId());
}
+
+ // Initialise the ThreadContext's memory proxies
+ tcBase()->initMemProxies(tcBase());
#endif
if (hasPhysMemPort) {
bool snoop = false;
@@ -145,18 +148,6 @@ AtomicSimpleCPU::CpuPort::recvRetry()
panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
}
-void
-AtomicSimpleCPU::DcachePort::setPeer(Port *port)
-{
- Port::setPeer(port);
-
-#if FULL_SYSTEM
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- cpu->tcBase()->connectMemPorts(cpu->tcBase());
-#endif
-}
-
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
simulate_data_stalls(p->simulate_data_stalls),
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 246afa0b2..c3d78a381 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -95,16 +95,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
};
CpuPort icachePort;
- class DcachePort : public CpuPort
- {
- public:
- DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
- : CpuPort(_name, _cpu)
- { }
-
- virtual void setPeer(Port *port);
- };
- DcachePort dcachePort;
+ CpuPort dcachePort;
CpuPort physmemPort;
bool hasPhysMemPort;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index e2151d974..4375d2549 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -81,6 +81,9 @@ TimingSimpleCPU::init()
// initialize CPU, including PC
TheISA::initCPU(tc, _cpuId);
}
+
+ // Initialise the ThreadContext's memory proxies
+ tcBase()->initMemProxies(tcBase());
#endif
}
@@ -874,18 +877,6 @@ TimingSimpleCPU::completeDrain()
drainEvent->process();
}
-void
-TimingSimpleCPU::DcachePort::setPeer(Port *port)
-{
- Port::setPeer(port);
-
-#if FULL_SYSTEM
- // Update the ThreadContext's memory ports (Functional/Virtual
- // Ports)
- cpu->tcBase()->connectMemPorts(cpu->tcBase());
-#endif
-}
-
bool
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 4301dfca7..6e95ddd9d 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -212,8 +212,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
: CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
{ }
- virtual void setPeer(Port *port);
-
protected:
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 61174dd4e..2541bdee1 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -50,11 +50,11 @@
#include "base/trace.hh"
#include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
-#include "mem/vport.hh"
+#include "mem/fs_translating_port_proxy.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#else
-#include "mem/translating_port.hh"
+#include "mem/se_translating_port_proxy.hh"
#include "sim/process.hh"
#include "sim/system.hh"
#endif
@@ -117,10 +117,6 @@ SimpleThread::SimpleThread()
SimpleThread::~SimpleThread()
{
-#if FULL_SYSTEM
- delete physPort;
- delete virtPort;
-#endif
delete tc;
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 2b7b89030..ebc23276a 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -208,13 +208,13 @@ class SimpleThread : public ThreadState
System *getSystemPtr() { return system; }
#if FULL_SYSTEM
- FunctionalPort *getPhysPort() { return physPort; }
+ PortProxy* getPhysProxy() { return physProxy; }
/** Return a virtual port. This port cannot be cached locally in an object.
* After a CPU switch it may point to the wrong memory object which could
* mean stale data.
*/
- VirtualPort *getVirtPort() { return virtPort; }
+ FSTranslatingPortProxy* getVirtProxy() { return virtProxy; }
#endif
Status status() const { return _status; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 3b7f8b3c3..d80d26e3d 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -50,9 +50,9 @@ class BaseCPU;
class Checkpoint;
class Decoder;
class EndQuiesceEvent;
-class TranslatingPort;
-class FunctionalPort;
-class VirtualPort;
+class SETranslatingPortProxy;
+class FSTranslatingPortProxy;
+class PortProxy;
class Process;
class System;
namespace TheISA {
@@ -128,13 +128,19 @@ class ThreadContext
#if FULL_SYSTEM
virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
- virtual FunctionalPort *getPhysPort() = 0;
+ virtual PortProxy* getPhysProxy() = 0;
- virtual VirtualPort *getVirtPort() = 0;
+ virtual FSTranslatingPortProxy* getVirtProxy() = 0;
- virtual void connectMemPorts(ThreadContext *tc) = 0;
+ /**
+ * Initialise the physical and virtual port proxies and tie them to
+ * the data port of the CPU.
+ *
+ * tc ThreadContext for the virtual-to-physical translation
+ */
+ virtual void initMemProxies(ThreadContext *tc) = 0;
#else
- virtual TranslatingPort *getMemPort() = 0;
+ virtual SETranslatingPortProxy *getMemProxy() = 0;
virtual Process *getProcessPtr() = 0;
#endif
@@ -298,13 +304,13 @@ class ProxyThreadContext : public ThreadContext
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
- FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+ PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); }
- VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
+ FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); }
- void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
+ void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
#else
- TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+ SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
#endif
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index dedeccb3e..6c9bb99ea 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -32,14 +32,15 @@
#include "cpu/base.hh"
#include "cpu/profile.hh"
#include "cpu/thread_state.hh"
-#include "mem/port.hh"
-#include "mem/translating_port.hh"
+#include "mem/port_proxy.hh"
+#include "mem/se_translating_port_proxy.hh"
#include "sim/serialize.hh"
+#include "sim/system.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#include "cpu/quiesce_event.hh"
-#include "mem/vport.hh"
+#include "mem/fs_translating_port_proxy.hh"
#endif
#if FULL_SYSTEM
@@ -51,9 +52,9 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
#if FULL_SYSTEM
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
- kernelStats(NULL), physPort(NULL), virtPort(NULL),
+ kernelStats(NULL), physProxy(NULL), virtProxy(NULL),
#else
- port(NULL), process(_process),
+ proxy(NULL), process(_process),
#endif
funcExeInst(0), storeCondFailures(0)
{
@@ -61,10 +62,16 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
ThreadState::~ThreadState()
{
-#if !FULL_SYSTEM
- if (port) {
- delete port->getPeer();
- delete port;
+#if FULL_SYSTEM
+ if (physProxy != NULL) {
+ delete physProxy;
+ }
+ if (virtProxy != NULL) {
+ delete virtProxy;
+ }
+#else
+ if (proxy != NULL) {
+ delete proxy;
}
#endif
}
@@ -106,38 +113,16 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
#if FULL_SYSTEM
void
-ThreadState::connectMemPorts(ThreadContext *tc)
+ThreadState::initMemProxies(ThreadContext *tc)
{
- connectPhysPort();
- connectVirtPort(tc);
-}
-
-void
-ThreadState::connectPhysPort()
-{
- // @todo: For now this disregards any older port that may have
- // already existed. Fix this memory leak once the bus port IDs
- // for functional ports is resolved.
- if (physPort)
- physPort->removeConn();
- else
- physPort = new FunctionalPort(csprintf("%s-%d-funcport",
- baseCpu->name(), _threadId));
- connectToMemFunc(physPort);
-}
-
-void
-ThreadState::connectVirtPort(ThreadContext *tc)
-{
- // @todo: For now this disregards any older port that may have
- // already existed. Fix this memory leak once the bus port IDs
- // for functional ports is resolved.
- if (virtPort)
- virtPort->removeConn();
- else
- virtPort = new VirtualPort(csprintf("%s-%d-vport",
- baseCpu->name(), _threadId), tc);
- connectToMemFunc(virtPort);
+ // Note that this only refers to the port on the CPU side and can
+ // safely be done at init() time even if the CPU is not connected
+ // (i.e. due to restoring from a checkpoint and later switching
+ // in.
+ if (physProxy == NULL)
+ physProxy = new PortProxy(*baseCpu->getPort("dcache_port"));
+ if (virtProxy == NULL)
+ virtProxy = new FSTranslatingPortProxy(tc);
}
void
@@ -155,36 +140,17 @@ ThreadState::profileSample()
}
#else
-TranslatingPort *
-ThreadState::getMemPort()
+SETranslatingPortProxy *
+ThreadState::getMemProxy()
{
- if (port != NULL)
- return port;
-
- /* Use this port to for syscall emulation writes to memory. */
- port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), _threadId),
- process, TranslatingPort::NextPage);
+ if (proxy != NULL)
+ return proxy;
- connectToMemFunc(port);
+ /* Use this port proxy to for syscall emulation writes to memory. */
+ proxy = new SETranslatingPortProxy(*process->system->getSystemPort(),
+ process,
+ SETranslatingPortProxy::NextPage);
- return port;
+ return proxy;
}
#endif
-
-void
-ThreadState::connectToMemFunc(Port *port)
-{
- Port *dcache_port, *func_mem_port;
-
- dcache_port = baseCpu->getPort("dcache_port");
- assert(dcache_port != NULL);
-
- MemObject *mem_object = dcache_port->getPeer()->getOwner();
- assert(mem_object != NULL);
-
- func_mem_port = mem_object->getPort("functional");
- assert(func_mem_port != NULL);
-
- func_mem_port->setPeer(port);
- port->setPeer(func_mem_port);
-}
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 824579852..a007567c1 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -54,8 +54,9 @@ namespace TheISA {
#endif
class Checkpoint;
-class Port;
-class TranslatingPort;
+class PortProxy;
+class SETranslatingPort;
+class FSTranslatingPort;
/**
* Struct for holding general thread state that is needed across CPU
@@ -93,11 +94,13 @@ struct ThreadState {
Tick readLastSuspend() { return lastSuspend; }
#if FULL_SYSTEM
- void connectMemPorts(ThreadContext *tc);
-
- void connectPhysPort();
-
- void connectVirtPort(ThreadContext *tc);
+ /**
+ * Initialise the physical and virtual port proxies and tie them to
+ * the data port of the CPU.
+ *
+ * tc ThreadContext for the virtual-to-physical translation
+ */
+ void initMemProxies(ThreadContext *tc);
void dumpFuncProfile();
@@ -109,17 +112,13 @@ struct ThreadState {
TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
- FunctionalPort *getPhysPort() { return physPort; }
+ PortProxy* getPhysProxy() { return physProxy; }
- void setPhysPort(FunctionalPort *port) { physPort = port; }
-
- VirtualPort *getVirtPort() { return virtPort; }
+ FSTranslatingPortProxy* getVirtProxy() { return virtProxy; }
#else
Process *getProcessPtr() { return process; }
- TranslatingPort *getMemPort();
-
- void setMemPort(TranslatingPort *_port) { port = _port; }
+ SETranslatingPortProxy* getMemProxy();
#endif
/** Reads the number of instructions functionally executed and
@@ -139,9 +138,6 @@ struct ThreadState {
void setStatus(Status new_status) { _status = new_status; }
public:
- /** Connects port to the functional port of the memory object
- * below the CPU. */
- void connectToMemFunc(Port *port);
/** Number of instructions committed. */
Counter numInst;
@@ -186,15 +182,15 @@ struct ThreadState {
TheISA::Kernel::Statistics *kernelStats;
protected:
- /** A functional port outgoing only for functional accesses to physical
+ /** A port proxy outgoing only for functional accesses to physical
* addresses.*/
- FunctionalPort *physPort;
+ PortProxy *physProxy;
- /** A functional port, outgoing only, for functional accesse to virtual
- * addresses. */
- VirtualPort *virtPort;
+ /** A translating port proxy, outgoing only, for functional
+ * accesse to virtual addresses. */
+ FSTranslatingPortProxy* virtProxy;
#else
- TranslatingPort *port;
+ SETranslatingPortProxy* proxy;
Process *process;
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 13:33:25 +0000