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-rw-r--r--src/cpu/base.cc75
-rw-r--r--src/cpu/base.hh15
-rw-r--r--src/cpu/checker/cpu.hh6
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh2
-rw-r--r--src/cpu/o3/cpu.hh3
-rw-r--r--src/cpu/o3/lsq_unit.hh4
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh2
-rw-r--r--src/cpu/ozone/OzoneCPU.py3
-rw-r--r--src/cpu/ozone/cpu.hh2
-rw-r--r--src/cpu/ozone/cpu_impl.hh12
-rw-r--r--src/cpu/ozone/front_end.hh5
-rw-r--r--src/cpu/ozone/front_end_impl.hh6
-rw-r--r--src/cpu/ozone/lw_lsq.hh7
-rw-r--r--src/cpu/ozone/lw_lsq_impl.hh6
-rw-r--r--src/cpu/simple/atomic.cc10
-rw-r--r--src/cpu/simple/atomic.hh7
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.cc20
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.hh12
-rw-r--r--src/cpu/testers/memtest/memtest.cc15
-rw-r--r--src/cpu/testers/memtest/memtest.hh9
-rw-r--r--src/cpu/testers/networktest/networktest.cc13
-rw-r--r--src/cpu/testers/networktest/networktest.hh9
-rw-r--r--src/cpu/testers/rubytest/RubyTester.cc19
-rw-r--r--src/cpu/testers/rubytest/RubyTester.hh12
24 files changed, 105 insertions, 169 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 5d5f704db..d01dcbef3 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -299,19 +299,19 @@ BaseCPU::regStats()
threadContexts[0]->regStats(name());
}
-Port *
-BaseCPU::getPort(const string &if_name, int idx)
+MasterPort &
+BaseCPU::getMasterPort(const string &if_name, int idx)
{
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
// of getDataPort and getInstPort. In all cases there methods
// return a CpuPort pointer.
if (if_name == "dcache_port")
- return &getDataPort();
+ return getDataPort();
else if (if_name == "icache_port")
- return &getInstPort();
+ return getInstPort();
else
- panic("CPU %s has no port named %s\n", name(), if_name);
+ return MemObject::getMasterPort(if_name, idx);
}
Tick
@@ -381,8 +381,6 @@ BaseCPU::switchOut()
void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
- CpuPort &ic = getInstPort();
- CpuPort &dc = getDataPort();
assert(threadContexts.size() == oldCPU->threadContexts.size());
_cpuId = oldCPU->cpuId();
@@ -407,24 +405,21 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
ThreadContext::compare(oldTC, newTC);
*/
- Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
- old_itb_port = oldTC->getITBPtr()->getPort();
- old_dtb_port = oldTC->getDTBPtr()->getPort();
- new_itb_port = newTC->getITBPtr()->getPort();
- new_dtb_port = newTC->getDTBPtr()->getPort();
+ MasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
+ MasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
+ MasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
+ MasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist
if (new_itb_port && !new_itb_port->isConnected()) {
assert(old_itb_port);
- Port *peer = old_itb_port->getPeer();;
- new_itb_port->setPeer(peer);
- peer->setPeer(new_itb_port);
+ SlavePort &slavePort = old_itb_port->getSlavePort();
+ new_itb_port->bind(slavePort);
}
if (new_dtb_port && !new_dtb_port->isConnected()) {
assert(old_dtb_port);
- Port *peer = old_dtb_port->getPeer();;
- new_dtb_port->setPeer(peer);
- peer->setPeer(new_dtb_port);
+ SlavePort &slavePort = old_dtb_port->getSlavePort();
+ new_dtb_port->bind(slavePort);
}
// Checker whether or not we have to transfer CheckerCPU
@@ -432,26 +427,25 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
if (oldChecker && newChecker) {
- Port *old_checker_itb_port, *old_checker_dtb_port;
- Port *new_checker_itb_port, *new_checker_dtb_port;
-
- old_checker_itb_port = oldChecker->getITBPtr()->getPort();
- old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
- new_checker_itb_port = newChecker->getITBPtr()->getPort();
- new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
+ MasterPort *old_checker_itb_port =
+ oldChecker->getITBPtr()->getMasterPort();
+ MasterPort *old_checker_dtb_port =
+ oldChecker->getDTBPtr()->getMasterPort();
+ MasterPort *new_checker_itb_port =
+ newChecker->getITBPtr()->getMasterPort();
+ MasterPort *new_checker_dtb_port =
+ newChecker->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist for checker
if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
assert(old_checker_itb_port);
- Port *peer = old_checker_itb_port->getPeer();;
- new_checker_itb_port->setPeer(peer);
- peer->setPeer(new_checker_itb_port);
+ SlavePort &slavePort = old_checker_itb_port->getSlavePort();;
+ new_checker_itb_port->bind(slavePort);
}
if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
assert(old_checker_dtb_port);
- Port *peer = old_checker_dtb_port->getPeer();;
- new_checker_dtb_port->setPeer(peer);
- peer->setPeer(new_checker_dtb_port);
+ SlavePort &slavePort = old_checker_dtb_port->getSlavePort();;
+ new_checker_dtb_port->bind(slavePort);
}
}
}
@@ -470,16 +464,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
// Connect new CPU to old CPU's memory only if new CPU isn't
// connected to anything. Also connect old CPU's memory to new
// CPU.
- if (!ic.isConnected()) {
- Port *peer = oldCPU->getInstPort().getPeer();
- ic.setPeer(peer);
- peer->setPeer(&ic);
+ if (!getInstPort().isConnected()) {
+ getInstPort().bind(oldCPU->getInstPort().getSlavePort());
}
- if (!dc.isConnected()) {
- Port *peer = oldCPU->getDataPort().getPeer();
- dc.setPeer(peer);
- peer->setPeer(&dc);
+ if (!getDataPort().isConnected()) {
+ getDataPort().bind(oldCPU->getDataPort().getSlavePort());
}
}
@@ -568,8 +558,3 @@ BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
// long term this should never be called, but that assumed a split
// into master/slave and request/response.
}
-
-void
-BaseCPU::CpuPort::recvRangeChange()
-{
-}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 149d26aa3..145b014aa 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -117,7 +117,7 @@ class BaseCPU : public MemObject
* both atomic and timing access is to panic and the corresponding
* subclasses have to override these methods.
*/
- class CpuPort : public Port
+ class CpuPort : public MasterPort
{
public:
@@ -128,7 +128,7 @@ class BaseCPU : public MemObject
* @param _name structural owner of this port
*/
CpuPort(const std::string& _name, MemObject* _owner) :
- Port(_name, _owner)
+ MasterPort(_name, _owner)
{ }
protected:
@@ -141,8 +141,6 @@ class BaseCPU : public MemObject
void recvFunctional(PacketPtr pkt);
- void recvRangeChange();
-
};
public:
@@ -172,11 +170,11 @@ class BaseCPU : public MemObject
MasterID instMasterId() { return _instMasterId; }
/**
- * Get a port on this MemObject. This method is virtual to allow
+ * Get a master port on this MemObject. This method is virtual to allow
* the subclasses of the BaseCPU to override it. All CPUs have a
* data and instruction port, but the Atomic CPU (in its current
* form) adds a port directly connected to the memory and has to
- * override getPort.
+ * override getMasterPort.
*
* This method uses getDataPort and getInstPort to resolve the two
* ports.
@@ -184,9 +182,10 @@ class BaseCPU : public MemObject
* @param if_name the port name
* @param idx ignored index
*
- * @return a pointer to the port with the given name
+ * @return a reference to the port with the given name
*/
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual MasterPort &getMasterPort(const std::string &if_name,
+ int idx = -1);
// Tick currentTick;
inline Tick frequency() const { return SimClock::Frequency / clock; }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index afc453f87..d816578ae 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -132,12 +132,6 @@ class CheckerCPU : public BaseCPU
return *icachePort;
}
- virtual Port *getPort(const std::string &name, int idx)
- {
- panic("Not supported on checker!");
- return NULL;
- }
-
public:
// Primary thread being run.
SimpleThread *thread;
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index d9f98e42c..3f3ef12e6 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -139,7 +139,7 @@ class CacheUnit : public Resource
protected:
/** Cache interface. */
- Port *cachePort;
+ MasterPort *cachePort;
bool cachePortBlocked;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 42e9f01f9..493730458 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -186,8 +186,7 @@ class FullO3CPU : public BaseO3CPU
*
* @return true since we have to snoop
*/
- virtual bool isSnooping()
- { return true; }
+ virtual bool isSnooping() const { return true; }
};
class TickEvent : public Event
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 702606d39..44898eb38 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -90,7 +90,7 @@ class LSQUnit {
void regStats();
/** Sets the pointer to the dcache port. */
- void setDcachePort(Port *dcache_port);
+ void setDcachePort(MasterPort *dcache_port);
/** Switches out LSQ unit. */
void switchOut();
@@ -268,7 +268,7 @@ class LSQUnit {
LSQ *lsq;
/** Pointer to the dcache port. Used only for sending. */
- Port *dcachePort;
+ MasterPort *dcachePort;
/** Derived class to hold any sender state the LSQ needs. */
class LSQSenderState : public Packet::SenderState, public FastAlloc
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index d0a630f6d..2de349242 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -239,7 +239,7 @@ LSQUnit<Impl>::regStats()
template<class Impl>
void
-LSQUnit<Impl>::setDcachePort(Port *dcache_port)
+LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
{
dcachePort = dcache_port;
}
diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index d50d8d715..b4f37220c 100644
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -36,9 +36,6 @@ class DerivOzoneCPU(BaseCPU):
numThreads = Param.Unsigned("number of HW thread contexts")
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
-
width = Param.Unsigned("Width")
frontEndWidth = Param.Unsigned("Front end width")
frontEndLatency = Param.Unsigned("Front end latency")
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index d2b90bff3..1bd2ee25b 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -316,8 +316,6 @@ class OzoneCPU : public BaseCPU
System *system;
PhysicalMemory *physmem;
- virtual Port *getPort(const std::string &name, int idx);
-
FrontEnd *frontEnd;
BackEnd *backEnd;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index b111d4425..3a32c07c6 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -391,18 +391,6 @@ OzoneCPU<Impl>::init()
}
template <class Impl>
-Port *
-OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
-{
- if (if_name == "dcache_port")
- return backEnd->getDcachePort();
- else if (if_name == "icache_port")
- return frontEnd->getIcachePort();
- else
- panic("No Such Port\n");
-}
-
-template <class Impl>
void
OzoneCPU<Impl>::serialize(std::ostream &os)
{
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 41b86aab8..6c63bf8d9 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -68,7 +68,7 @@ class FrontEnd
/** IcachePort class. Handles doing the communication with the
* cache/memory.
*/
- class IcachePort : public Port
+ class IcachePort : public MasterPort
{
protected:
/** Pointer to FE. */
@@ -87,9 +87,6 @@ class FrontEnd
/** Functional version of receive. Panics. */
virtual void recvFunctional(PacketPtr pkt);
- /** Receives range change. */
- virtual void recvRangeChange();
-
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 2c9c70872..12aa0a321 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -59,12 +59,6 @@ FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
}
template<class Impl>
-void
-FrontEnd<Impl>::IcachePort::recvRangeChange()
-{
-}
-
-template<class Impl>
bool
FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 809725c0d..a581b242f 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -240,7 +240,7 @@ class OzoneLWLSQ {
/** Pointer to the back-end stage. */
BackEnd *be;
- class DcachePort : public Port
+ class DcachePort : public MasterPort
{
protected:
OzoneLWLSQ *lsq;
@@ -255,13 +255,10 @@ class OzoneLWLSQ {
virtual void recvFunctional(PacketPtr pkt);
- virtual void recvRangeChange();
-
/**
* Is a snooper due to LSQ maintenance
*/
- virtual bool isSnooping()
- { return true; }
+ virtual bool isSnooping() const { return true; }
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 82d0b4e8b..c0c6d7276 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -75,12 +75,6 @@ OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
}
template <class Impl>
-void
-OzoneLWLSQ<Impl>::DcachePort::recvRangeChange()
-{
-}
-
-template <class Impl>
bool
OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
{
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index e5b3bd67d..d7ad07a5e 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -65,14 +65,14 @@ AtomicSimpleCPU::TickEvent::description() const
return "AtomicSimpleCPU tick";
}
-Port *
-AtomicSimpleCPU::getPort(const string &if_name, int idx)
+MasterPort &
+AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
{
if (if_name == "physmem_port") {
hasPhysMemPort = true;
- return &physmemPort;
+ return physmemPort;
} else {
- return BaseCPU::getPort(if_name, idx);
+ return BaseCPU::getMasterPort(if_name, idx);
}
}
@@ -94,7 +94,7 @@ AtomicSimpleCPU::init()
}
if (hasPhysMemPort) {
- AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges();
+ AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
physMemAddr = *pmAddrList.begin();
}
// Atomic doesn't do MT right now, so contextId == threadId
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 8a1c9000f..126cd3765 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -112,10 +112,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
/**
- * Override the getPort of the BaseCPU so that we can provide a pointer
- * to the physmemPort, unique to the Atomic CPU.
+ * Override the getMasterPort of the BaseCPU so that we can
+ * provide the physmemPort, unique to the Atomic CPU.
*/
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual MasterPort &getMasterPort(const std::string &if_name,
+ int idx = -1);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc
index 4518066eb..bfdd28e08 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -75,19 +75,19 @@ RubyDirectedTester::init()
generator->setDirectedTester(this);
}
-Port *
-RubyDirectedTester::getPort(const std::string &if_name, int idx)
+MasterPort &
+RubyDirectedTester::getMasterPort(const std::string &if_name, int idx)
{
if (if_name != "cpuPort") {
- panic("RubyDirectedTester::getPort: unknown port %s requested",
- if_name);
- }
+ // pass it along to our super class
+ return MemObject::getMasterPort(if_name, idx);
+ } else {
+ if (idx >= static_cast<int>(ports.size())) {
+ panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
+ }
- if (idx >= static_cast<int>(ports.size())) {
- panic("RubyDirectedTester::getPort: unknown index %d requested\n", idx);
+ return *ports[idx];
}
-
- return ports[idx];
}
Tick
@@ -110,7 +110,7 @@ RubyDirectedTester::CpuPort::recvTiming(PacketPtr pkt)
return true;
}
-Port*
+MasterPort*
RubyDirectedTester::getCpuPort(int idx)
{
assert(idx >= 0 && idx < ports.size());
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh
index cd0632976..cb207ff80 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -47,7 +47,7 @@ class DirectedGenerator;
class RubyDirectedTester : public MemObject
{
public:
- class CpuPort : public Port
+ class CpuPort : public MasterPort
{
private:
RubyDirectedTester *tester;
@@ -55,25 +55,27 @@ class RubyDirectedTester : public MemObject
public:
CpuPort(const std::string &_name, RubyDirectedTester *_tester,
uint32_t _idx)
- : Port(_name, _tester), tester(_tester), idx(_idx)
+ : MasterPort(_name, _tester), tester(_tester), idx(_idx)
{}
uint32_t idx;
protected:
virtual bool recvTiming(PacketPtr pkt);
+ virtual void recvRetry()
+ { panic("%s does not expect a retry\n", name()); }
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt) { }
- virtual void recvRangeChange() { }
};
typedef RubyDirectedTesterParams Params;
RubyDirectedTester(const Params *p);
~RubyDirectedTester();
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual MasterPort &getMasterPort(const std::string &if_name,
+ int idx = -1);
- Port* getCpuPort(int idx);
+ MasterPort* getCpuPort(int idx);
virtual void init();
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index dffaa71ed..07cdf73a6 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -85,11 +85,6 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
}
void
-MemTest::CpuPort::recvRangeChange()
-{
-}
-
-void
MemTest::CpuPort::recvRetry()
{
memtest->doRetry();
@@ -161,15 +156,15 @@ MemTest::MemTest(const Params *p)
dmaOutstanding = false;
}
-Port *
-MemTest::getPort(const std::string &if_name, int idx)
+MasterPort &
+MemTest::getMasterPort(const std::string &if_name, int idx)
{
if (if_name == "functional")
- return &funcPort;
+ return funcPort;
else if (if_name == "test")
- return &cachePort;
+ return cachePort;
else
- panic("No Such Port\n");
+ return MemObject::getMasterPort(if_name, idx);
}
void
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index c56a37574..d179fa530 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -62,7 +62,8 @@ class MemTest : public MemObject
// main simulation loop (one cycle)
void tick();
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual MasterPort &getMasterPort(const std::string &if_name,
+ int idx = -1);
/**
* Print state of address in memory system via PrintReq (for
@@ -84,14 +85,14 @@ class MemTest : public MemObject
TickEvent tickEvent;
- class CpuPort : public Port
+ class CpuPort : public MasterPort
{
MemTest *memtest;
public:
CpuPort(const std::string &_name, MemTest *_memtest)
- : Port(_name, _memtest), memtest(_memtest)
+ : MasterPort(_name, _memtest), memtest(_memtest)
{ }
protected:
@@ -102,8 +103,6 @@ class MemTest : public MemObject
virtual void recvFunctional(PacketPtr pkt);
- virtual void recvRangeChange();
-
virtual void recvRetry();
};
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 3fe153c4e..01f247707 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -82,11 +82,6 @@ NetworkTest::CpuPort::recvFunctional(PacketPtr pkt)
}
void
-NetworkTest::CpuPort::recvRangeChange()
-{
-}
-
-void
NetworkTest::CpuPort::recvRetry()
{
networktest->doRetry();
@@ -126,13 +121,13 @@ NetworkTest::NetworkTest(const Params *p)
name(), id);
}
-Port *
-NetworkTest::getPort(const std::string &if_name, int idx)
+MasterPort &
+NetworkTest::getMasterPort(const std::string &if_name, int idx)
{
if (if_name == "test")
- return &cachePort;
+ return cachePort;
else
- panic("No Such Port\n");
+ return MemObject::getMasterPort(if_name, idx);
}
void
diff --git a/src/cpu/testers/networktest/networktest.hh b/src/cpu/testers/networktest/networktest.hh
index de67d41a0..21984f45d 100644
--- a/src/cpu/testers/networktest/networktest.hh
+++ b/src/cpu/testers/networktest/networktest.hh
@@ -57,7 +57,8 @@ class NetworkTest : public MemObject
// main simulation loop (one cycle)
void tick();
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual MasterPort &getMasterPort(const std::string &if_name,
+ int idx = -1);
/**
* Print state of address in memory system via PrintReq (for
@@ -79,14 +80,14 @@ class NetworkTest : public MemObject
TickEvent tickEvent;
- class CpuPort : public Port
+ class CpuPort : public MasterPort
{
NetworkTest *networktest;
public:
CpuPort(const std::string &_name, NetworkTest *_networktest)
- : Port(_name, _networktest), networktest(_networktest)
+ : MasterPort(_name, _networktest), networktest(_networktest)
{ }
protected:
@@ -97,8 +98,6 @@ class NetworkTest : public MemObject
virtual void recvFunctional(PacketPtr pkt);
- virtual void recvRangeChange();
-
virtual void recvRetry();
};
diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc
index 70ee40aed..e1942cf61 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -92,18 +92,19 @@ RubyTester::init()
m_checkTable_ptr = new CheckTable(m_num_cpu_sequencers, this);
}
-Port *
-RubyTester::getPort(const std::string &if_name, int idx)
+MasterPort &
+RubyTester::getMasterPort(const std::string &if_name, int idx)
{
if (if_name != "cpuPort") {
- panic("RubyTester::getPort: unknown port %s requested\n", if_name);
- }
+ // pass it along to our super class
+ return MemObject::getMasterPort(if_name, idx);
+ } else {
+ if (idx >= static_cast<int>(ports.size())) {
+ panic("RubyTester::getMasterPort: unknown index %d\n", idx);
+ }
- if (idx >= static_cast<int>(ports.size())) {
- panic("RubyTester::getPort: unknown index %d requested\n", idx);
+ return *ports[idx];
}
-
- return ports[idx];
}
Tick
@@ -135,7 +136,7 @@ RubyTester::CpuPort::recvTiming(PacketPtr pkt)
return true;
}
-Port*
+MasterPort*
RubyTester::getCpuPort(int idx)
{
assert(idx >= 0 && idx < ports.size());
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index e8cf4c874..b24dddd83 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -45,23 +45,24 @@
class RubyTester : public MemObject
{
public:
- class CpuPort : public Port
+ class CpuPort : public MasterPort
{
private:
RubyTester *tester;
public:
CpuPort(const std::string &_name, RubyTester *_tester, int _idx)
- : Port(_name, _tester), tester(_tester), idx(_idx)
+ : MasterPort(_name, _tester), tester(_tester), idx(_idx)
{}
int idx;
protected:
virtual bool recvTiming(PacketPtr pkt);
+ virtual void recvRetry()
+ { panic("%s does not expect a retry\n", name()); }
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt) { }
- virtual void recvRangeChange() { }
};
struct SenderState : public Packet::SenderState
@@ -86,9 +87,10 @@ class RubyTester : public MemObject
RubyTester(const Params *p);
~RubyTester();
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual MasterPort &getMasterPort(const std::string &if_name,
+ int idx = -1);
- Port* getCpuPort(int idx);
+ MasterPort* getCpuPort(int idx);
virtual void init();