diff options
Diffstat (limited to 'src/cpu')
35 files changed, 249 insertions, 760 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index fda0528ad..7dacc58ff 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -72,8 +72,7 @@ CheckerCPU::CheckerCPU(Params *p) systemPtr = NULL; #else process = p->process; - thread = new SimpleThread(this, /* thread_num */ 0, process, - /* asid */ 0); + thread = new SimpleThread(this, /* thread_num */ 0, process); tc = thread->getTC(); threadContexts.push_back(tc); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 3b378700e..450ce6228 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -211,25 +211,12 @@ class CheckerCPU : public BaseCPU return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatReg(reg_idx, width); - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatRegBits(reg_idx, width); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -242,21 +229,6 @@ class CheckerCPU : public BaseCPU result.integer = val; } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatReg(reg_idx, val, width); - switch(width) { - case 32: - result.dbl = (double)val; - break; - case 64: - result.dbl = val; - break; - }; - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -265,14 +237,6 @@ class CheckerCPU : public BaseCPU } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatRegBits(reg_idx, val, width); - result.integer = val; - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 2176c597a..d38bd2915 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -174,15 +174,9 @@ class CheckerThreadContext : public ThreadContext uint64_t readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - FloatReg readFloatReg(int reg_idx, int width) - { return actualTC->readFloatReg(reg_idx, width); } - FloatReg readFloatReg(int reg_idx) { return actualTC->readFloatReg(reg_idx); } - FloatRegBits readFloatRegBits(int reg_idx, int width) - { return actualTC->readFloatRegBits(reg_idx, width); } - FloatRegBits readFloatRegBits(int reg_idx) { return actualTC->readFloatRegBits(reg_idx); } @@ -192,24 +186,12 @@ class CheckerThreadContext : public ThreadContext checkerTC->setIntReg(reg_idx, val); } - void setFloatReg(int reg_idx, FloatReg val, int width) - { - actualTC->setFloatReg(reg_idx, val, width); - checkerTC->setFloatReg(reg_idx, val, width); - } - void setFloatReg(int reg_idx, FloatReg val) { actualTC->setFloatReg(reg_idx, val); checkerTC->setFloatReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, FloatRegBits val, int width) - { - actualTC->setFloatRegBits(reg_idx, val, width); - checkerTC->setFloatRegBits(reg_idx, val, width); - } - void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 2b9fe4bcf..3d07e95f3 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -50,17 +50,9 @@ class ExecContext { /** Reads an integer register. */ uint64_t readIntRegOperand(const StaticInst *si, int idx); - /** Reads a floating point register of a specific width. */ - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width); - /** Reads a floating point register of single register width. */ FloatReg readFloatRegOperand(const StaticInst *si, int idx); - /** Reads a floating point register of a specific width in its - * binary format, instead of by value. */ - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width); - /** Reads a floating point register in its binary format, instead * of by value. */ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); @@ -68,18 +60,9 @@ class ExecContext { /** Sets an integer register to a value. */ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); - /** Sets a floating point register of a specific width to a value. */ - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width); - /** Sets a floating point register of single width to a value. */ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); - /** Sets the bits of a floating point register of a specific width - * to a binary value. */ - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width); - /** Sets the bits of a floating point register of single width * to a binary value. */ void setFloatRegOperandBits(const StaticInst *si, int idx, diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 3d7d713e8..a2367db63 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -168,7 +168,6 @@ InOrderCPU::InOrderCPU(Params *params) coreType("default"), _status(Idle), tickEvent(this), - miscRegFile(this), timeBuffer(2 , 2), removeInstsThisCycle(false), activityRec(params->name, NumStages, 10, params->activity), @@ -208,12 +207,12 @@ InOrderCPU::InOrderCPU(Params *params) DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n", tid, this->thread[tid]); this->thread[tid] = - new Thread(this, tid, params->workload[tid], tid); + new Thread(this, tid, params->workload[tid]); } else { //Allocate Empty thread so M5 can use later //when scheduling threads to CPU Process* dummy_proc = params->workload[0]; - this->thread[tid] = new Thread(this, tid, dummy_proc, tid); + this->thread[tid] = new Thread(this, tid, dummy_proc); } // Setup the TC that will serve as the interface to the threads/CPU. @@ -265,17 +264,13 @@ InOrderCPU::InOrderCPU(Params *params) squashSeqNum[tid] = MaxAddr; lastSquashCycle[tid] = 0; - intRegFile[tid].clear(); - floatRegFile[tid].clear(); - } + memset(intRegs[tid], 0, sizeof(intRegs[tid])); + memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid])); + isa[tid].clear(); - // Update miscRegFile if necessary - if (numThreads > 1) { - miscRegFile.expandForMultithreading(numThreads, numVirtProcs); + isa[tid].expandForMultithreading(numThreads, numVirtProcs); } - miscRegFile.clear(); - lastRunningCycle = curTick; contextSwitch = false; @@ -461,7 +456,10 @@ InOrderCPU::readFunctional(Addr addr, uint32_t &buffer) void InOrderCPU::reset() { - miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this)); + for (int i = 0; i < numThreads; i++) { + isa[i].reset(coreType, numThreads, + numVirtProcs, dynamic_cast<BaseCPU*>(this)); + } } Port* @@ -888,41 +886,39 @@ InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid) uint64_t InOrderCPU::readIntReg(int reg_idx, ThreadID tid) { - return intRegFile[tid].readReg(reg_idx); + return intRegs[tid][reg_idx]; } FloatReg -InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatReg(int reg_idx, ThreadID tid) { - - return floatRegFile[tid].readReg(reg_idx, width); + return floatRegs.f[tid][reg_idx]; } FloatRegBits -InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid) {; - return floatRegFile[tid].readRegBits(reg_idx, width); + return floatRegs.i[tid][reg_idx]; } void InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid) { - intRegFile[tid].setReg(reg_idx, val); + intRegs[tid][reg_idx] = val; } void -InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width) +InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid) { - floatRegFile[tid].setReg(reg_idx, val, width); + floatRegs.f[tid][reg_idx] = val; } void -InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width) +InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid) { - floatRegFile[tid].setRegBits(reg_idx, val, width); + floatRegs.i[tid][reg_idx] = val; } uint64_t @@ -966,25 +962,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val, MiscReg InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return miscRegFile.readRegNoEffect(misc_reg, tid); + return isa[tid].readMiscRegNoEffect(misc_reg); } MiscReg InOrderCPU::readMiscReg(int misc_reg, ThreadID tid) { - return miscRegFile.readReg(misc_reg, tcBase(tid), tid); + return isa[tid].readMiscReg(misc_reg, tcBase(tid)); } void InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) { - miscRegFile.setRegNoEffect(misc_reg, val, tid); + isa[tid].setMiscRegNoEffect(misc_reg, val); } void InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid) { - miscRegFile.setReg(misc_reg, val, tcBase(tid), tid); + isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); } diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 794d81def..75d77c818 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -39,6 +39,7 @@ #include <vector> #include "arch/isa_traits.hh" +#include "arch/types.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "base/types.hh" @@ -77,7 +78,6 @@ class InOrderCPU : public BaseCPU typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::MiscReg MiscReg; - typedef TheISA::RegFile RegFile; //DynInstPtr TypeDefs typedef ThePipeline::DynInstPtr DynInstPtr; @@ -257,9 +257,14 @@ class InOrderCPU : public BaseCPU TheISA::IntReg nextNPC[ThePipeline::MaxThreads]; /** The Register File for the CPU */ - TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];; - TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];; - TheISA::MiscRegFile miscRegFile; + union { + FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + } floatRegs; + TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; + + /** ISA state */ + TheISA::ISA isa[ThePipeline::MaxThreads]; /** Dependency Tracker for Integer & Floating Point Regs */ RegDepMap archRegDepMap[ThePipeline::MaxThreads]; @@ -390,30 +395,18 @@ class InOrderCPU : public BaseCPU return cpuEventNum++; } - /** Get instruction asid. */ - int getInstAsid(ThreadID tid) - { return thread[tid]->getInstAsid(); } - - /** Get data asid. */ - int getDataAsid(ThreadID tid) - { return thread[tid]->getDataAsid(); } - /** Register file accessors */ uint64_t readIntReg(int reg_idx, ThreadID tid); - FloatReg readFloatReg(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatReg readFloatReg(int reg_idx, ThreadID tid); - FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid); void setIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setFloatReg(int reg_idx, FloatReg val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatReg(int reg_idx, FloatReg val, ThreadID tid); - void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid); /** Reads a miscellaneous register. */ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index ee2e5500e..a6abb28b2 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -366,14 +366,9 @@ InOrderDynInst::setIntSrc(int idx, uint64_t val) /** Records an fp register being set to a value. */ void -InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width) +InOrderDynInst::setFloatSrc(int idx, FloatReg val) { - if (width == 32) - instSrc[idx].dbl = val; - else if (width == 64) - instSrc[idx].dbl = val; - else - panic("Unsupported width!"); + instSrc[idx].dbl = val; } /** Records an fp register being set to an integer value. */ @@ -394,22 +389,15 @@ InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid) /** Reads a FP register. */ FloatReg -InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width) -{ - if (width == 32) - return (float)instSrc[idx].dbl; - else if (width == 64) - return instSrc[idx].dbl; - else { - panic("Unsupported Floating Point Width!"); - return 0; - } +InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx) +{ + return instSrc[idx].dbl; } /** Reads a FP register as a integer. */ FloatRegBits -InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width) +InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx) { return instSrc[idx].integer; } @@ -507,31 +495,22 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val) /** Sets a FP register. */ void -InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width) -{ - if (width == 32) { - instResult[idx].val.dbl = (float)val; - instResult[idx].type = Float; - } else if (width == 64) { - instResult[idx].val.dbl = val; - instResult[idx].type = Double; - } else { - panic("Unsupported Floating Point Width!"); - } +InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) +{ + instResult[idx].val.dbl = val; + instResult[idx].type = Float; instResult[idx].tick = curTick; - instResult[idx].width = width; } /** Sets a FP register as a integer. */ void InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + FloatRegBits val) { instResult[idx].type = Integer; instResult[idx].val.integer = val; instResult[idx].tick = curTick; - instResult[idx].width = width; } /** Sets a misc. register. */ diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index 031d882ee..e95a6d039 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -243,10 +243,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted ResultType type; InstValue val; Tick tick; - int width; InstResult() - : type(None), tick(0), width(0) + : type(None), tick(0) {} }; @@ -817,7 +816,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Functions that sets an integer or floating point * source register to a value. */ void setIntSrc(int idx, uint64_t val); - void setFloatSrc(int idx, FloatReg val, int width = 32); + void setFloatSrc(int idx, FloatReg val); void setFloatRegBitsSrc(int idx, uint64_t val); uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; } @@ -830,10 +829,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted * the source reg. value is set using the setSrcReg() function. */ IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0); - FloatReg readFloatRegOperand(const StaticInst *si, int idx, - int width = TheISA::SingleWidth); - TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width = TheISA::SingleWidth); + FloatReg readFloatRegOperand(const StaticInst *si, int idx); + TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); MiscReg readMiscReg(int misc_reg); MiscReg readMiscRegNoEffect(int misc_reg); MiscReg readMiscRegOperand(const StaticInst *si, int idx); @@ -853,15 +850,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Depending on type, return Float or Double */ double readFloatResult(int idx) { - //Should this function have a parameter for what width of return?x - return (instResult[idx].type == Float) ? - (float) instResult[idx].val.dbl : instResult[idx].val.dbl; - } - - double readDoubleResult(int idx) - { - assert(instResult[idx].type == Double); - return instResult[idx].val.dbl; + return instResult[idx].val.dbl; } Tick readResultTime(int idx) { return instResult[idx].tick; } @@ -872,10 +861,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted * it's destination register. */ void setIntRegOperand(const StaticInst *si, int idx, IntReg val); - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width = TheISA::SingleWidth); - void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val, - int width = TheISA::SingleWidth); + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); + void setFloatRegOperandBits(const StaticInst *si, int idx, + TheISA::FloatRegBits val); void setMiscReg(int misc_reg, const MiscReg &val); void setMiscRegNoEffect(int misc_reg, const MiscReg &val); void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val); diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc index c9072b5d5..6c44e2456 100644 --- a/src/cpu/inorder/resources/execution_unit.cc +++ b/src/cpu/inorder/resources/execution_unit.cc @@ -179,8 +179,7 @@ ExecutionUnit::execute(int slot_num) DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n", inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ? - inst->readFloatResult(0) : (inst->resultType(0) == InOrderDynInst::Double) ? - inst->readDoubleResult(0) : inst->readIntResult(0)); + inst->readFloatResult(0) : inst->readIntResult(0)); exec_req->done(); } else { diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index b30a3a1bf..2f1652c08 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -53,8 +53,6 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width, outWriteSeqNum[tid] = maxSeqNum; regDepMap[tid] = &cpu->archRegDepMap[tid]; - - floatRegSize[tid] = cpu->floatRegFile[tid].regWidth; } } @@ -138,12 +136,11 @@ UseDefUnit::execute(int slot_idx) DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File:%x (%08f).\n", tid, reg_idx, - cpu->readFloatRegBits(reg_idx, inst->readTid(), floatRegSize[tid]), - cpu->readFloatReg(reg_idx, inst->readTid(),floatRegSize[tid])); + cpu->readFloatRegBits(reg_idx, inst->readTid()), + cpu->readFloatReg(reg_idx, inst->readTid())); inst->setFloatSrc(ud_idx, - cpu->readFloatReg(reg_idx, inst->readTid(), floatRegSize[tid]), - floatRegSize[tid]); + cpu->readFloatReg(reg_idx, inst->readTid())); } else { reg_idx -= Ctrl_Base_DepTag; DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File:%i.\n", @@ -183,8 +180,7 @@ UseDefUnit::execute(int slot_idx) tid, forward_inst->readFloatResult(dest_reg_idx) , forward_inst->seqNum, inst->seqNum, ud_idx); inst->setFloatSrc(ud_idx, - forward_inst->readFloatResult(dest_reg_idx), - floatRegSize[tid]); + forward_inst->readFloatResult(dest_reg_idx)); } else { DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from " "[sn:%i] to [sn:%i] source #%i.\n", @@ -244,24 +240,21 @@ UseDefUnit::execute(int slot_idx) cpu->setFloatRegBits(reg_idx, // Check for FloatRegBits Here inst->readIntResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readTid()); } else if (inst->resultType(ud_idx) == InOrderDynInst::Float) { DPRINTF(InOrderUseDef, "[tid:%i]: Writing Float Result 0x%x (bits:0x%x) to register idx %i.\n", tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx); cpu->setFloatReg(reg_idx, inst->readFloatResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readTid()); } else if (inst->resultType(ud_idx) == InOrderDynInst::Double) { DPRINTF(InOrderUseDef, "[tid:%i]: Writing Double Result 0x%x (bits:0x%x) to register idx %i.\n", tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx); cpu->setFloatReg(reg_idx, // Check for FloatRegBits Here - inst->readDoubleResult(ud_idx), - inst->readTid(), - floatRegSize[tid]); + inst->readFloatResult(ud_idx), + inst->readTid()); } else { panic("Result Type Not Set For [sn:%i] %s.\n", inst->seqNum, inst->instName()); } diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc index a1e9b5948..fe1a0faa1 100644 --- a/src/cpu/inorder/thread_context.cc +++ b/src/cpu/inorder/thread_context.cc @@ -151,24 +151,12 @@ InOrderThreadContext::readIntReg(int reg_idx) } FloatReg -InOrderThreadContext::readFloatReg(int reg_idx, int width) -{ - return cpu->readFloatReg(reg_idx, thread->readTid(), width); -} - -FloatReg InOrderThreadContext::readFloatReg(int reg_idx) { return cpu->readFloatReg(reg_idx, thread->readTid()); } FloatRegBits -InOrderThreadContext::readFloatRegBits(int reg_idx, int width) -{ - return cpu->readFloatRegBits(reg_idx, thread->readTid(), width); -} - -FloatRegBits InOrderThreadContext::readFloatRegBits(int reg_idx) { return cpu->readFloatRegBits(reg_idx, thread->readTid()); @@ -187,25 +175,12 @@ InOrderThreadContext::setIntReg(int reg_idx, uint64_t val) } void -InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width) -{ - cpu->setFloatReg(reg_idx, val, thread->readTid(), width); -} - -void InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val) { cpu->setFloatReg(reg_idx, val, thread->readTid()); } void -InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width); -} - -void InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) { cpu->setFloatRegBits(reg_idx, val, thread->readTid()); diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index f3cf3ec44..327f8ac71 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -152,12 +152,8 @@ class InOrderThreadContext : public ThreadContext /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); - virtual FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); - virtual FloatRegBits readFloatRegBits(int reg_idx); virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid); @@ -165,12 +161,8 @@ class InOrderThreadContext : public ThreadContext /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val, int width); - virtual void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); virtual void setRegOtherThread(int misc_reg, const MiscReg &val, @@ -211,6 +203,12 @@ class InOrderThreadContext : public ThreadContext * write might have as defined by the architecture. */ virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual int flattenIntIndex(int reg) + { return cpu->isa[thread->readTid()].flattenIntIndex(reg); } + + virtual int flattenFloatIndex(int reg) + { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); } + virtual void activateContext(int delay) { cpu->activateContext(thread->readTid(), delay); } diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh index 803659487..9b3b39fcb 100644 --- a/src/cpu/inorder/thread_state.hh +++ b/src/cpu/inorder/thread_state.hh @@ -68,9 +68,9 @@ class InOrderThreadState : public ThreadState { InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num, - Process *_process, int _asid) + Process *_process) : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/, - _process, 0/*_asid*/), + _process), cpu(_cpu), inSyscall(0), trapPending(0) { } diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc index 0ca02eeec..5face4391 100644 --- a/src/cpu/legiontrace.cc +++ b/src/cpu/legiontrace.cc @@ -46,7 +46,7 @@ #include <sys/shm.h> #include "arch/sparc/predecoder.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/utility.hh" #include "base/socket.hh" #include "cpu/base.hh" @@ -232,8 +232,7 @@ Trace::LegionTraceRecord::dump() } } for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { - if (thread->readFloatRegBits(i*2, - FloatRegFile::DoubleWidth) != + if (thread->readFloatRegBits(i*2) != shared_data->fpregs[i]) { diffFpRegs = true; } @@ -539,8 +538,7 @@ Trace::LegionTraceRecord::dump() char label[8]; sprintf(label, "%%f%d", x); printRegPair(outs, label, - thread->readFloatRegBits(x*2, - FloatRegFile::DoubleWidth), + thread->readFloatRegBits(x*2), shared_data->fpregs[x]); } } diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index c23a9e4ad..fca8674f9 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -33,7 +33,7 @@ #include <errno.h> -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "arch/utility.hh" #include "base/loader/symtab.hh" #include "base/socket.hh" diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 621b6c1b9..6722941e4 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -361,7 +361,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) tid, this->thread[tid]); this->thread[tid] = new typename FullO3CPU<Impl>::Thread( (typename Impl::O3CPU *)(this), - tid, params->workload[tid], tid); + tid, params->workload[tid]); //usedTids[tid] = true; //threadMap[tid] = tid; @@ -372,7 +372,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) this->thread[tid] = new typename FullO3CPU<Impl>::Thread( (typename Impl::O3CPU *)(this), - tid, dummy_proc, tid); + tid, dummy_proc); //usedTids[tid] = false; } #endif // !FULL_SYSTEM @@ -1180,14 +1180,14 @@ template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return this->regFile.readMiscRegNoEffect(misc_reg, tid); + return this->isa[tid].readMiscRegNoEffect(misc_reg); } template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) { - return this->regFile.readMiscReg(misc_reg, tid); + return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); } template <class Impl> @@ -1195,7 +1195,7 @@ void FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscRegNoEffect(misc_reg, val, tid); + this->isa[tid].setMiscRegNoEffect(misc_reg, val); } template <class Impl> @@ -1203,7 +1203,7 @@ void FullO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscReg(misc_reg, val, tid); + this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); } template <class Impl> @@ -1215,13 +1215,6 @@ FullO3CPU<Impl>::readIntReg(int reg_idx) template <class Impl> FloatReg -FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) -{ - return regFile.readFloatReg(reg_idx, width); -} - -template <class Impl> -FloatReg FullO3CPU<Impl>::readFloatReg(int reg_idx) { return regFile.readFloatReg(reg_idx); @@ -1229,13 +1222,6 @@ FullO3CPU<Impl>::readFloatReg(int reg_idx) template <class Impl> FloatRegBits -FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) -{ - return regFile.readFloatRegBits(reg_idx, width); -} - -template <class Impl> -FloatRegBits FullO3CPU<Impl>::readFloatRegBits(int reg_idx) { return regFile.readFloatRegBits(reg_idx); @@ -1250,13 +1236,6 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) template <class Impl> void -FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) -{ - regFile.setFloatReg(reg_idx, val, width); -} - -template <class Impl> -void FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) { regFile.setFloatReg(reg_idx, val); @@ -1264,13 +1243,6 @@ FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) template <class Impl> void -FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) -{ - regFile.setFloatRegBits(reg_idx, val, width); -} - -template <class Impl> -void FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { regFile.setFloatRegBits(reg_idx, val); @@ -1287,7 +1259,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) template <class Impl> float -FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid) +FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); @@ -1296,16 +1268,6 @@ FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid) } template <class Impl> -double -FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid) -{ - int idx = reg_idx + TheISA::NumIntRegs; - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); - - return regFile.readFloatReg(phys_reg, 64); -} - -template <class Impl> uint64_t FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) { @@ -1326,7 +1288,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid) +FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); @@ -1336,16 +1298,6 @@ FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid) -{ - int idx = reg_idx + TheISA::NumIntRegs; - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); - - regFile.setFloatReg(phys_reg, val, 64); -} - -template <class Impl> -void FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 5cf27df75..0cc8eab78 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -392,23 +392,6 @@ class FullO3CPU : public BaseO3CPU /** Check if this address is a valid data address. */ bool validDataAddr(Addr addr) { return true; } - - /** Get instruction asid. */ - int getInstAsid(ThreadID tid) - { return regFile.miscRegs[tid].getInstAsid(); } - - /** Get data asid. */ - int getDataAsid(ThreadID tid) - { return regFile.miscRegs[tid].getDataAsid(); } -#else - /** Get instruction asid. */ - int getInstAsid(ThreadID tid) - { return thread[tid]->getInstAsid(); } - - /** Get data asid. */ - int getDataAsid(ThreadID tid) - { return thread[tid]->getDataAsid(); } - #endif /** Register accessors. Index refers to the physical register index. */ @@ -435,27 +418,17 @@ class FullO3CPU : public BaseO3CPU TheISA::FloatReg readFloatReg(int reg_idx); - TheISA::FloatReg readFloatReg(int reg_idx, int width); - TheISA::FloatRegBits readFloatRegBits(int reg_idx); - TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); - void setIntReg(int reg_idx, uint64_t val); void setFloatReg(int reg_idx, TheISA::FloatReg val); - void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); - void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); - void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); - uint64_t readArchIntReg(int reg_idx, ThreadID tid); - float readArchFloatRegSingle(int reg_idx, ThreadID tid); - - double readArchFloatRegDouble(int reg_idx, ThreadID tid); + float readArchFloatReg(int reg_idx, ThreadID tid); uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); @@ -466,9 +439,7 @@ class FullO3CPU : public BaseO3CPU */ void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid); - - void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid); + void setArchFloatReg(int reg_idx, float val, ThreadID tid); void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); @@ -603,6 +574,8 @@ class FullO3CPU : public BaseO3CPU /** Integer Register Scoreboard */ Scoreboard scoreboard; + TheISA::ISA isa[Impl::MaxThreads]; + public: /** Enum to give each stage a specific index, so when calling * activateStage() or deactivateStage(), they can specify which stage diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 292547b6b..3ef42e91f 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -196,22 +196,11 @@ class BaseO3DynInst : public BaseDynInst<Impl> return this->cpu->readIntReg(this->_srcRegIdx[idx]); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx], width); - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(this->_srcRegIdx[idx]); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); @@ -226,13 +215,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> BaseDynInst<Impl>::setIntRegOperand(si, idx, val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(this->_destRegIdx[idx], val); @@ -240,13 +222,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh index 79e10524b..e28c4910e 100644 --- a/src/cpu/o3/free_list.hh +++ b/src/cpu/o3/free_list.hh @@ -34,7 +34,7 @@ #include <iostream> #include <queue> -#include "arch/isa_traits.hh" +#include "arch/registers.hh" #include "base/misc.hh" #include "base/trace.hh" #include "base/traceflags.hh" diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 07f8d487b..d6beecdc5 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -33,7 +33,6 @@ #define __CPU_O3_REGFILE_HH__ #include "arch/isa_traits.hh" -#include "arch/regfile.hh" #include "arch/types.hh" #include "base/trace.hh" #include "config/full_system.hh" @@ -57,8 +56,6 @@ class PhysRegFile typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscRegFile MiscRegFile; - typedef TheISA::MiscReg MiscReg; typedef union { FloatReg d; @@ -95,21 +92,6 @@ class PhysRegFile return intRegFile[reg_idx]; } - FloatReg readFloatReg(PhysRegIndex reg_idx, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); - - FloatReg floatReg = floatRegFile[reg_idx].d; - - DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " - "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); - - return floatReg; - } - /** Reads a floating point register (double precision). */ FloatReg readFloatReg(PhysRegIndex reg_idx) { @@ -126,22 +108,6 @@ class PhysRegFile return floatReg; } - /** Reads a floating point register as an integer. */ - FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); - - FloatRegBits floatRegBits = floatRegFile[reg_idx].q; - - DPRINTF(IEW, "RegFile: Access to float register %i as int, " - "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); - - return floatRegBits; - } - FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) { // Remove the base Float reg dependency. @@ -169,23 +135,6 @@ class PhysRegFile intRegFile[reg_idx] = val; } - /** Sets a single precision floating point register to the given value. */ - void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs); - - DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", - int(reg_idx), (uint64_t)val); - -#if THE_ISA == ALPHA_ISA - if (reg_idx != TheISA::ZeroReg) -#endif - floatRegFile[reg_idx].d = val; - } - /** Sets a double precision floating point register to the given value. */ void setFloatReg(PhysRegIndex reg_idx, FloatReg val) { @@ -203,20 +152,6 @@ class PhysRegFile floatRegFile[reg_idx].d = val; } - /** Sets a floating point register to the given integer value. */ - void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs); - - DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", - int(reg_idx), (uint64_t)val); - - floatRegFile[reg_idx].q = val; - } - void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) { // Remove the base Float reg dependency. @@ -230,30 +165,6 @@ class PhysRegFile floatRegFile[reg_idx].q = val; } - MiscReg - readMiscRegNoEffect(int misc_reg, ThreadID tid) - { - return miscRegs[tid].readRegNoEffect(misc_reg); - } - - MiscReg - readMiscReg(int misc_reg, ThreadID tid) - { - return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid)); - } - - void - setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) - { - miscRegs[tid].setRegNoEffect(misc_reg, val); - } - - void - setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid) - { - miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid)); - } - public: /** (signed) integer register file. */ IntReg *intRegFile; @@ -261,9 +172,6 @@ class PhysRegFile /** Floating point register file. */ PhysFloatReg *floatRegFile; - /** Miscellaneous register file. */ - MiscRegFile miscRegs[Impl::MaxThreads]; - #if FULL_SYSTEM private: int intrflag; // interrupt flag @@ -289,10 +197,6 @@ PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, intRegFile = new IntReg[numPhysicalIntRegs]; floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; - for (int i = 0; i < Impl::MaxThreads; ++i) { - miscRegs[i].clear(); - } - memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); } diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 2bca6f81c..e4cc2674b 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -32,7 +32,7 @@ #include <list> #include "arch/isa_traits.hh" -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "config/full_system.hh" #include "cpu/o3/rename.hh" #include "params/DerivO3CPU.hh" @@ -959,11 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) RegIndex src_reg = inst->srcRegIdx(src_idx); RegIndex flat_src_reg = src_reg; if (src_reg < TheISA::FP_Base_DepTag) { - flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); + flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); } else if (src_reg < TheISA::Ctrl_Base_DepTag) { src_reg = src_reg - TheISA::FP_Base_DepTag; - flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); + flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); flat_src_reg += TheISA::NumIntRegs; } else { flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; @@ -1009,7 +1009,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) RegIndex flat_dest_reg = dest_reg; if (dest_reg < TheISA::FP_Base_DepTag) { // Integer registers are flattened. - flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); + flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); } else { // Floating point and Miscellaneous registers need their indexes diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index b10305d5d..ed5c6ac20 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -167,23 +167,15 @@ class O3ThreadContext : public ThreadContext /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); - virtual FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); - virtual FloatRegBits readFloatRegBits(int reg_idx); /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val, int width); - virtual void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); /** Reads this thread's PC. */ @@ -226,6 +218,9 @@ class O3ThreadContext : public ThreadContext * write might have as defined by the architecture. */ virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual int flattenIntIndex(int reg); + virtual int flattenFloatIndex(int reg); + /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. virtual unsigned readStCondFailures() diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index bce334dc4..e631c9244 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -29,7 +29,7 @@ * Korey Sewell */ -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "cpu/o3/thread_context.hh" #include "cpu/quiesce_event.hh" @@ -272,48 +272,23 @@ template <class Impl> uint64_t O3ThreadContext<Impl>::readIntReg(int reg_idx) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); return cpu->readArchIntReg(reg_idx, thread->threadId()); } template <class Impl> TheISA::FloatReg -O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) -{ - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - switch(width) { - case 32: - return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); - case 64: - return cpu->readArchFloatRegDouble(reg_idx, thread->threadId()); - default: - panic("Unsupported width!"); - return 0; - } -} - -template <class Impl> -TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); -} - -template <class Impl> -TheISA::FloatRegBits -O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) -{ - DPRINTF(Fault, "Reading floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + return cpu->readArchFloatReg(reg_idx, thread->threadId()); } template <class Impl> TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } @@ -321,7 +296,7 @@ template <class Impl> void O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); cpu->setArchIntReg(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -332,30 +307,10 @@ O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) template <class Impl> void -O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) -{ - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - switch(width) { - case 32: - cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); - break; - case 64: - cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId()); - break; - } - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->threadId()); - } -} - -template <class Impl> -void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + cpu->setArchFloatReg(reg_idx, val, thread->threadId()); if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->threadId()); @@ -364,24 +319,9 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) template <class Impl> void -O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - DPRINTF(Fault, "Setting floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); - cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->threadId()); - } -} - -template <class Impl> -void O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -439,6 +379,20 @@ O3ThreadContext<Impl>::setNextMicroPC(uint64_t val) } template <class Impl> +int +O3ThreadContext<Impl>::flattenIntIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenIntIndex(reg); +} + +template <class Impl> +int +O3ThreadContext<Impl>::flattenFloatIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenFloatIndex(reg); +} + +template <class Impl> void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 1f0e7a3bb..1171053b9 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -95,8 +95,8 @@ struct O3ThreadState : public ThreadState { profilePC = 3; } #else - O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid) - : ThreadState(_cpu, _thread_num, _process, _asid), + O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process) + : ThreadState(_cpu, _thread_num, _process), cpu(_cpu), inSyscall(0), trapPending(0) { } #endif diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 2e21411ae..5e36332af 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -33,7 +33,6 @@ #include <set> -#include "arch/regfile.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "config/full_system.hh" @@ -183,22 +182,14 @@ class OzoneCPU : public BaseCPU uint64_t readIntReg(int reg_idx); - FloatReg readFloatReg(int reg_idx, int width); - FloatReg readFloatReg(int reg_idx); - FloatRegBits readFloatRegBits(int reg_idx, int width); - FloatRegBits readFloatRegBits(int reg_idx); void setIntReg(int reg_idx, uint64_t val); - void setFloatReg(int reg_idx, FloatReg val, int width); - void setFloatReg(int reg_idx, FloatReg val); - void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - void setFloatRegBits(int reg_idx, FloatRegBits val); uint64_t readPC() { return thread->PC; } diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 25fa64071..f86b882d1 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -918,22 +918,6 @@ OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx) } template <class Impl> -TheISA::FloatReg -OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width) -{ - int idx = reg_idx + TheISA::FP_Base_DepTag; - switch(width) { - case 32: - return thread->renameTable[idx]->readFloatResult(); - case 64: - return thread->renameTable[idx]->readDoubleResult(); - default: - panic("Unsupported width!"); - return 0; - } -} - -template <class Impl> double OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx) { @@ -943,14 +927,6 @@ OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx) template <class Impl> uint64_t -OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width) -{ - int idx = reg_idx + TheISA::FP_Base_DepTag; - return thread->renameTable[idx]->readIntResult(); -} - -template <class Impl> -uint64_t OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx) { int idx = reg_idx + TheISA::FP_Base_DepTag; @@ -970,27 +946,6 @@ OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val) template <class Impl> void -OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width) -{ - int idx = reg_idx + TheISA::FP_Base_DepTag; - switch(width) { - case 32: - panic("Unimplemented!"); - break; - case 64: - thread->renameTable[idx]->setDoubleResult(val); - break; - default: - panic("Unsupported width!"); - } - - if (!thread->inSyscall) { - cpu->squashFromTC(); - } -} - -template <class Impl> -void OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val) { int idx = reg_idx + TheISA::FP_Base_DepTag; @@ -1004,14 +959,6 @@ OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val) template <class Impl> void -OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - panic("Unimplemented!"); -} - -template <class Impl> -void OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val) { panic("Unimplemented!"); diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index e138cbe13..a39f383ba 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -151,28 +151,14 @@ class OzoneDynInst : public BaseDynInst<Impl> return srcInsts[idx]->readIntResult(); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - switch(width) { - case 32: - return srcInsts[idx]->readFloatResult(); - case 64: - return srcInsts[idx]->readDoubleResult(); - default: - panic("Width not supported"); - return 0; - } - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return srcInsts[idx]->readFloatResult(); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { - return srcInsts[idx]->readIntResult(); + return srcInsts[idx]->readFloatResult(); } FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) @@ -188,24 +174,12 @@ class OzoneDynInst : public BaseDynInst<Impl> BaseDynInst<Impl>::setIntReg(si, idx, val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - BaseDynInst<Impl>::setFloatReg(si, idx, val, width); - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { BaseDynInst<Impl>::setFloatReg(si, idx, val); } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { BaseDynInst<Impl>::setFloatRegBits(si, idx, val); diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index 53776e7d9..971fba886 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -86,9 +86,8 @@ struct OzoneThreadState : public ThreadState { miscRegFile.clear(); } #else - OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process, - int _asid) - : ThreadState(_cpu, -1, _thread_num, _process, _asid), + OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process) + : ThreadState(_cpu, -1, _thread_num, _process), cpu(_cpu), inSyscall(0), trapPending(0) { miscRegFile.clear(); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 279fb98b7..921c8c19d 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -78,7 +78,7 @@ BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); #else thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], - p->itb, p->dtb, /* asid */ 0); + p->itb, p->dtb); #endif // !FULL_SYSTEM thread->setStatus(ThreadContext::Halted); diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 4e71d677e..466d0d1c9 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -262,25 +262,12 @@ class BaseSimpleCPU : public BaseCPU return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatReg(reg_idx, width); - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; - return thread->readFloatRegBits(reg_idx, width); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -292,13 +279,6 @@ class BaseSimpleCPU : public BaseCPU thread->setIntReg(si->destRegIdx(idx), val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatReg(reg_idx, val, width); - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; @@ -306,13 +286,6 @@ class BaseSimpleCPU : public BaseCPU } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; - thread->setFloatRegBits(reg_idx, val, width); - } - - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 73b23f89a..22bc283a3 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -63,15 +63,15 @@ using namespace std; SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, TheISA::TLB *_itb, TheISA::TLB *_dtb, bool use_kernel_stats) - : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb), - dtb(_dtb) + : ThreadState(_cpu, _thread_num), + cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) { tc = new ProxyThreadContext<SimpleThread>(this); quiesceEvent = new EndQuiesceEvent(tc); - regs.clear(); + clearArchRegs(); if (cpu->params()->profile) { profile = new FunctionProfile(system->kernelSymtab); @@ -92,11 +92,11 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, } #else SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, - TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid) - : ThreadState(_cpu, _thread_num, _process, _asid), + TheISA::TLB *_itb, TheISA::TLB *_dtb) + : ThreadState(_cpu, _thread_num, _process), cpu(_cpu), itb(_itb), dtb(_dtb) { - regs.clear(); + clearArchRegs(); tc = new ProxyThreadContext<SimpleThread>(this); } @@ -106,11 +106,10 @@ SimpleThread::SimpleThread() #if FULL_SYSTEM : ThreadState(NULL, -1) #else - : ThreadState(NULL, -1, NULL, -1) + : ThreadState(NULL, -1, NULL) #endif { tc = new ProxyThreadContext<SimpleThread>(this); - regs.clear(); } SimpleThread::~SimpleThread() @@ -191,7 +190,13 @@ void SimpleThread::serialize(ostream &os) { ThreadState::serialize(os); - regs.serialize(cpu, os); + SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); + SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); + SERIALIZE_SCALAR(microPC); + SERIALIZE_SCALAR(nextMicroPC); + SERIALIZE_SCALAR(PC); + SERIALIZE_SCALAR(nextPC); + SERIALIZE_SCALAR(nextNPC); // thread_num and cpu_id are deterministic from the config } @@ -200,7 +205,13 @@ void SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) { ThreadState::unserialize(cp, section); - regs.unserialize(cpu, cp, section); + UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); + UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); + UNSERIALIZE_SCALAR(microPC); + UNSERIALIZE_SCALAR(nextMicroPC); + UNSERIALIZE_SCALAR(PC); + UNSERIALIZE_SCALAR(nextPC); + UNSERIALIZE_SCALAR(nextNPC); // thread_num and cpu_id are deterministic from the config } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 08dd45640..d9d624e77 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -32,9 +32,11 @@ #ifndef __CPU_SIMPLE_THREAD_HH__ #define __CPU_SIMPLE_THREAD_HH__ +#include "arch/isa.hh" #include "arch/isa_traits.hh" -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "arch/tlb.hh" +#include "arch/types.hh" #include "base/types.hh" #include "config/full_system.hh" #include "cpu/thread_context.hh" @@ -88,9 +90,7 @@ class TranslatingPort; class SimpleThread : public ThreadState { protected: - typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; - typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; @@ -98,7 +98,34 @@ class SimpleThread : public ThreadState typedef ThreadContext::Status Status; protected: - RegFile regs; // correct-path register context + union { + FloatReg f[TheISA::NumFloatRegs]; + FloatRegBits i[TheISA::NumFloatRegs]; + } floatRegs; + TheISA::IntReg intRegs[TheISA::NumIntRegs]; + TheISA::ISA isa; // one "instance" of the current ISA. + + /** The current microcode pc for the currently executing macro + * operation. + */ + MicroPC microPC; + + /** The next microcode pc for the currently executing macro + * operation. + */ + MicroPC nextMicroPC; + + /** The current pc. + */ + Addr PC; + + /** The next pc. + */ + Addr nextPC; + + /** The next next pc. + */ + Addr nextNPC; public: // pointer to CPU associated with this SimpleThread @@ -118,7 +145,7 @@ class SimpleThread : public ThreadState bool use_kernel_stats = true); #else SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, - TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); + TheISA::TLB *_itb, TheISA::TLB *_dtb); #endif SimpleThread(); @@ -164,9 +191,6 @@ class SimpleThread : public ThreadState } #if FULL_SYSTEM - int getInstAsid() { return regs.instAsid(); } - int getDataAsid() { return regs.dataAsid(); } - void dumpFuncProfile(); Fault hwrei(); @@ -222,79 +246,68 @@ class SimpleThread : public ThreadState void copyArchRegs(ThreadContext *tc); - void clearArchRegs() { regs.clear(); } + void clearArchRegs() + { + microPC = 0; + nextMicroPC = 1; + PC = nextPC = nextNPC = 0; + memset(intRegs, 0, sizeof(intRegs)); + memset(floatRegs.i, 0, sizeof(floatRegs.i)); + } // // New accessors for new decoder. // uint64_t readIntReg(int reg_idx) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); - return regs.readIntReg(flatIndex); - } - - FloatReg readFloatReg(int reg_idx, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatReg(flatIndex, width); + int flatIndex = isa.flattenIntIndex(reg_idx); + assert(flatIndex < TheISA::NumIntRegs); + return intRegs[flatIndex]; } FloatReg readFloatReg(int reg_idx) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatReg(flatIndex); - } - - FloatRegBits readFloatRegBits(int reg_idx, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatRegBits(flatIndex, width); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + return floatRegs.f[flatIndex]; } FloatRegBits readFloatRegBits(int reg_idx) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - return regs.readFloatRegBits(flatIndex); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + return floatRegs.i[flatIndex]; } void setIntReg(int reg_idx, uint64_t val) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); - regs.setIntReg(flatIndex, val); - } - - void setFloatReg(int reg_idx, FloatReg val, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatReg(flatIndex, val, width); + int flatIndex = isa.flattenIntIndex(reg_idx); + assert(flatIndex < TheISA::NumIntRegs); + intRegs[flatIndex] = val; } void setFloatReg(int reg_idx, FloatReg val) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatReg(flatIndex, val); - } - - void setFloatRegBits(int reg_idx, FloatRegBits val, int width) - { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatRegBits(flatIndex, val, width); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + floatRegs.f[flatIndex] = val; } void setFloatRegBits(int reg_idx, FloatRegBits val) { - int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); - regs.setFloatRegBits(flatIndex, val); + int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); + floatRegs.i[flatIndex] = val; } uint64_t readPC() { - return regs.readPC(); + return PC; } void setPC(uint64_t val) { - regs.setPC(val); + PC = val; } uint64_t readMicroPC() @@ -309,12 +322,12 @@ class SimpleThread : public ThreadState uint64_t readNextPC() { - return regs.readNextPC(); + return nextPC; } void setNextPC(uint64_t val) { - regs.setNextPC(val); + nextPC = val; } uint64_t readNextMicroPC() @@ -329,36 +342,54 @@ class SimpleThread : public ThreadState uint64_t readNextNPC() { - return regs.readNextNPC(); +#if ISA_HAS_DELAY_SLOT + return nextNPC; +#else + return nextPC + sizeof(TheISA::MachInst); +#endif } void setNextNPC(uint64_t val) { - regs.setNextNPC(val); +#if ISA_HAS_DELAY_SLOT + nextNPC = val; +#endif } MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) { - return regs.readMiscRegNoEffect(misc_reg); + return isa.readMiscRegNoEffect(misc_reg); } MiscReg readMiscReg(int misc_reg, ThreadID tid = 0) { - return regs.readMiscReg(misc_reg, tc); + return isa.readMiscReg(misc_reg, tc); } void setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) { - return regs.setMiscRegNoEffect(misc_reg, val); + return isa.setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) { - return regs.setMiscReg(misc_reg, val, tc); + return isa.setMiscReg(misc_reg, val, tc); + } + + int + flattenIntIndex(int reg) + { + return isa.flattenIntIndex(reg); + } + + int + flattenFloatIndex(int reg) + { + return isa.flattenFloatIndex(reg); } unsigned readStCondFailures() { return storeCondFailures; } diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 3e37572d8..9e34204ef 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -31,7 +31,7 @@ #ifndef __CPU_THREAD_CONTEXT_HH__ #define __CPU_THREAD_CONTEXT_HH__ -#include "arch/regfile.hh" +#include "arch/registers.hh" #include "arch/types.hh" #include "base/types.hh" #include "config/full_system.hh" @@ -79,12 +79,10 @@ namespace TheISA { class ThreadContext { protected: - typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscReg MiscReg; public: @@ -188,24 +186,16 @@ class ThreadContext // virtual uint64_t readIntReg(int reg_idx) = 0; - virtual FloatReg readFloatReg(int reg_idx, int width) = 0; - virtual FloatReg readFloatReg(int reg_idx) = 0; - virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; - virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; virtual void setIntReg(int reg_idx, uint64_t val) = 0; - virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; - virtual void setFloatReg(int reg_idx, FloatReg val) = 0; virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; - virtual uint64_t readPC() = 0; virtual void setPC(uint64_t val) = 0; @@ -234,6 +224,9 @@ class ThreadContext virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual int flattenIntIndex(int reg) = 0; + virtual int flattenFloatIndex(int reg) = 0; + virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid) { @@ -375,30 +368,18 @@ class ProxyThreadContext : public ThreadContext uint64_t readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - FloatReg readFloatReg(int reg_idx, int width) - { return actualTC->readFloatReg(reg_idx, width); } - FloatReg readFloatReg(int reg_idx) { return actualTC->readFloatReg(reg_idx); } - FloatRegBits readFloatRegBits(int reg_idx, int width) - { return actualTC->readFloatRegBits(reg_idx, width); } - FloatRegBits readFloatRegBits(int reg_idx) { return actualTC->readFloatRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) { actualTC->setIntReg(reg_idx, val); } - void setFloatReg(int reg_idx, FloatReg val, int width) - { actualTC->setFloatReg(reg_idx, val, width); } - void setFloatReg(int reg_idx, FloatReg val) { actualTC->setFloatReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, FloatRegBits val, int width) - { actualTC->setFloatRegBits(reg_idx, val, width); } - void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); } @@ -434,6 +415,12 @@ class ProxyThreadContext : public ThreadContext void setMiscReg(int misc_reg, const MiscReg &val) { return actualTC->setMiscReg(misc_reg, val); } + int flattenIntIndex(int reg) + { return actualTC->flattenIntIndex(reg); } + + int flattenFloatIndex(int reg) + { return actualTC->flattenFloatIndex(reg); } + unsigned readStCondFailures() { return actualTC->readStCondFailures(); } diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index d9d83fb00..c62a7a3be 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -45,8 +45,7 @@ #if FULL_SYSTEM ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid) #else -ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, - Process *_process, short _asid) +ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) #endif : numInst(0), numLoad(0), _status(ThreadContext::Halted), baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0), @@ -54,9 +53,9 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), kernelStats(NULL), physPort(NULL), virtPort(NULL), #else - port(NULL), process(_process), asid(_asid), + port(NULL), process(_process), #endif - microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) + funcExeInst(0), storeCondFailures(0) { } @@ -77,8 +76,6 @@ ThreadState::serialize(std::ostream &os) // thread_num and cpu_id are deterministic from the config SERIALIZE_SCALAR(funcExeInst); SERIALIZE_SCALAR(inst); - SERIALIZE_SCALAR(microPC); - SERIALIZE_SCALAR(nextMicroPC); #if FULL_SYSTEM Tick quiesceEndTick = 0; @@ -98,8 +95,6 @@ ThreadState::unserialize(Checkpoint *cp, const std::string §ion) // thread_num and cpu_id are deterministic from the config UNSERIALIZE_SCALAR(funcExeInst); UNSERIALIZE_SCALAR(inst); - UNSERIALIZE_SCALAR(microPC); - UNSERIALIZE_SCALAR(nextMicroPC); #if FULL_SYSTEM Tick quiesceEndTick; diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 525ecca86..5c7c0ea56 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -68,7 +68,7 @@ struct ThreadState { #if FULL_SYSTEM ThreadState(BaseCPU *cpu, ThreadID _tid); #else - ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process, short _asid); + ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process); #endif ~ThreadState(); @@ -119,9 +119,6 @@ struct ThreadState { TranslatingPort *getMemPort(); void setMemPort(TranslatingPort *_port) { port = _port; } - - int getInstAsid() { return asid; } - int getDataAsid() { return asid; } #endif /** Sets the current instruction being committed. */ @@ -205,12 +202,6 @@ struct ThreadState { TranslatingPort *port; Process *process; - - // Address space ID. Note that this is used for TIMING cache - // simulation only; all functional memory accesses should use - // one of the FunctionalMemory pointers above. - short asid; - #endif /** Current instruction the thread is committing. Only set and @@ -218,16 +209,6 @@ struct ThreadState { */ TheISA::MachInst inst; - /** The current microcode pc for the currently executing macro - * operation. - */ - MicroPC microPC; - - /** The next microcode pc for the currently executing macro - * operation. - */ - MicroPC nextMicroPC; - public: /** * Temporary storage to pass the source address from copy_load to |