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-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py2
-rw-r--r--src/cpu/simple/TimingSimpleCPU.py2
2 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 87e8b5509..b7174bb43 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -35,8 +35,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
- function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index b7f044bfa..ce6839241 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -32,8 +32,6 @@ from BaseSimpleCPU import BaseSimpleCPU
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
- function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']