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-rw-r--r--src/cpu/o3/O3CPU.py4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 47b18a3ec..2a5b6782f 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -146,7 +146,3 @@ class DerivO3CPU(BaseCPU):
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
- def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
- BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
- self.icache.tgts_per_mshr = 20
- self.dcache.tgts_per_mshr = 20