diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/checker/thread_context.hh | 1 | ||||
| -rw-r--r-- | src/cpu/inorder/thread_context.hh | 3 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 1 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 7 | ||||
| -rw-r--r-- | src/cpu/simple_thread.hh | 8 | ||||
| -rw-r--r-- | src/cpu/thread_context.hh | 4 |
6 files changed, 23 insertions, 1 deletions
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index c06e03fc6..5c695c750 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -300,6 +300,7 @@ class CheckerThreadContext : public ThreadContext int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } + int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } unsigned readStCondFailures() { return actualTC->readStCondFailures(); } diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 5e1c65f8f..b1a361027 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -273,6 +273,9 @@ class InOrderThreadContext : public ThreadContext int flattenCCIndex(int reg) { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); } + int flattenMiscIndex(int reg) + { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); } + void activateContext(Cycles delay) { cpu->activateContext(thread->threadId(), delay); } diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 88cf75f4f..27f8e9561 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -244,6 +244,7 @@ class O3ThreadContext : public ThreadContext virtual int flattenIntIndex(int reg); virtual int flattenFloatIndex(int reg); virtual int flattenCCIndex(int reg); + virtual int flattenMiscIndex(int reg); /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index c818260f4..43e903135 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -292,6 +292,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg) } template <class Impl> +int +O3ThreadContext<Impl>::flattenMiscIndex(int reg) +{ + return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); +} + +template <class Impl> void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index fa0d20b0a..c5fae4e8e 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 ARM Limited + * Copyright (c) 2011-2012 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -415,6 +415,12 @@ class SimpleThread : public ThreadState return isa->flattenCCIndex(reg); } + int + flattenMiscIndex(int reg) + { + return isa->flattenMiscIndex(reg); + } + unsigned readStCondFailures() { return storeCondFailures; } void setStCondFailures(unsigned sc_failures) diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index be18f680f..efd3cc800 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -235,6 +235,7 @@ class ThreadContext virtual int flattenIntIndex(int reg) = 0; virtual int flattenFloatIndex(int reg) = 0; virtual int flattenCCIndex(int reg) = 0; + virtual int flattenMiscIndex(int reg) = 0; virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid) @@ -451,6 +452,9 @@ class ProxyThreadContext : public ThreadContext int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } + int flattenMiscIndex(int reg) + { return actualTC->flattenMiscIndex(reg); } + unsigned readStCondFailures() { return actualTC->readStCondFailures(); } |