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-rw-r--r--src/cpu/checker/cpu.cc8
-rw-r--r--src/cpu/kvm/base.cc5
-rw-r--r--src/cpu/kvm/base.hh3
-rw-r--r--src/cpu/kvm/x86_cpu.cc5
-rw-r--r--src/cpu/kvm/x86_cpu.hh3
-rw-r--r--src/cpu/simple/timing.cc16
-rw-r--r--src/cpu/simple/timing.hh2
-rw-r--r--src/cpu/testers/memtest/memtest.cc6
-rw-r--r--src/cpu/testers/networktest/networktest.cc12
9 files changed, 25 insertions, 35 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index f91bad294..d6a8bd032 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -154,8 +154,8 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
// Need to account for multiple accesses like the Atomic and TimingSimple
while (1) {
- memReq = new Request();
- memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
+ memReq = new Request(0, addr, size, flags, masterId,
+ thread->pcState().instAddr(), tc->contextId(), 0);
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
@@ -242,8 +242,8 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
// Need to account for a multiple access like Atomic and Timing CPUs
while (1) {
- memReq = new Request();
- memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
+ memReq = new Request(0, addr, size, flags, masterId,
+ thread->pcState().instAddr(), tc->contextId(), 0);
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 95d91467e..e09c4b7f2 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -118,8 +118,6 @@ BaseKvmCPU::init()
// initialize CPU, including PC
if (FullSystem && !switchedOut())
TheISA::initCPU(tc, tc->contextId());
-
- mmio_req.setThreadContext(tc->contextId(), 0);
}
void
@@ -995,7 +993,8 @@ BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write)
ThreadContext *tc(thread->getTC());
syncThreadContext();
- mmio_req.setPhys(paddr, size, Request::UNCACHEABLE, dataMasterId());
+ Request mmio_req(paddr, size, Request::UNCACHEABLE, dataMasterId());
+ mmio_req.setThreadContext(tc->contextId(), 0);
// Some architectures do need to massage physical addresses a bit
// before they are inserted into the memory system. This enables
// APIC accesses on x86 and m5ops where supported through a MMIO
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 249398293..dac4934cb 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -574,9 +574,6 @@ class BaseKvmCPU : public BaseCPU
/** Unused dummy port for the instruction interface */
KVMCpuPort instPort;
- /** Pre-allocated MMIO memory request */
- Request mmio_req;
-
/**
* Is the gem5 context dirty? Set to true to force an update of
* the KVM vCPU state upon the next call to kvmRun().
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index 3e736a913..34b51f137 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -554,8 +554,6 @@ X86KvmCPU::startup()
updateCPUID();
- io_req.setThreadContext(tc->contextId(), 0);
-
// TODO: Do we need to create an identity mapped TSS area? We
// should call kvm.vm.setTSSAddress() here in that case. It should
// only be needed for old versions of the virtualization
@@ -1346,8 +1344,9 @@ X86KvmCPU::handleKvmExitIO()
pAddr = X86ISA::x86IOAddress(port);
}
- io_req.setPhys(pAddr, kvm_run.io.size, Request::UNCACHEABLE,
+ Request io_req(pAddr, kvm_run.io.size, Request::UNCACHEABLE,
dataMasterId());
+ io_req.setThreadContext(tc->contextId(), 0);
const MemCmd cmd(isWrite ? MemCmd::WriteReq : MemCmd::ReadReq);
// Temporarily lock and migrate to the event queue of the
diff --git a/src/cpu/kvm/x86_cpu.hh b/src/cpu/kvm/x86_cpu.hh
index bfd090ff7..18471040c 100644
--- a/src/cpu/kvm/x86_cpu.hh
+++ b/src/cpu/kvm/x86_cpu.hh
@@ -234,9 +234,6 @@ class X86KvmCPU : public BaseKvmCPU
*/
void handleIOMiscReg32(int miscreg);
- /** Reusable IO request */
- Request io_req;
-
/** Cached intersection of supported MSRs */
mutable Kvm::MSRIndexVector cachedMsrIntersection;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c7db5c4f8..8c90d7c4e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -270,8 +270,7 @@ void
TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
bool read)
{
- PacketPtr pkt;
- buildPacket(pkt, req, read);
+ PacketPtr pkt = buildPacket(req, read);
pkt->dataDynamic<uint8_t>(data);
if (req->getFlags().isSet(Request::NO_ACCESS)) {
assert(!dcache_pkt);
@@ -354,10 +353,10 @@ TimingSimpleCPU::translationFault(const Fault &fault)
advanceInst(fault);
}
-void
-TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
+PacketPtr
+TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
{
- pkt = read ? Packet::createRead(req) : Packet::createWrite(req);
+ return read ? Packet::createRead(req) : Packet::createWrite(req);
}
void
@@ -370,14 +369,13 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
if (req->getFlags().isSet(Request::NO_ACCESS)) {
- buildPacket(pkt1, req, read);
+ pkt1 = buildPacket(req, read);
return;
}
- buildPacket(pkt1, req1, read);
- buildPacket(pkt2, req2, read);
+ pkt1 = buildPacket(req1, read);
+ pkt2 = buildPacket(req2, read);
- req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
pkt->dataDynamic<uint8_t>(data);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 52eb6b1ba..d8460515b 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -137,7 +137,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void translationFault(const Fault &fault);
- void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
+ PacketPtr buildPacket(RequestPtr req, bool read);
void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
RequestPtr req1, RequestPtr req2, RequestPtr req,
uint8_t *data, bool read);
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 53c01b7f7..a94f6950d 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -300,16 +300,16 @@ MemTest::tick()
bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
!uncacheable;
- Request *req = new Request();
+ Request *req = nullptr;
uint8_t *result = new uint8_t[8];
if (issueDmas) {
paddr &= ~((1 << dma_access_size) - 1);
- req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
+ req = new Request(paddr, 1 << dma_access_size, flags, masterId);
req->setThreadContext(id,0);
} else {
paddr &= ~((1 << access_size) - 1);
- req->setPhys(paddr, 1 << access_size, flags, masterId);
+ req = new Request(paddr, 1 << access_size, flags, masterId);
req->setThreadContext(id,0);
}
assert(req->getSize() == 1);
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 8ad32d140..4a79d5a17 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -198,9 +198,6 @@ NetworkTest::generatePkt()
destination = dest_y*networkDimension + dest_x;
}
- Request *req = new Request();
- Request::Flags flags;
-
// The source of the packets is a cache.
// The destination of the packets is a directory.
// The destination bits are embedded in the address after byte-offset.
@@ -234,21 +231,24 @@ NetworkTest::generatePkt()
//
MemCmd::Command requestType;
+ Request *req = nullptr;
+ Request::Flags flags;
+
unsigned randomReqType = random_mt.random(0, 2);
if (randomReqType == 0) {
// generate packet for virtual network 0
requestType = MemCmd::ReadReq;
- req->setPhys(paddr, access_size, flags, masterId);
+ req = new Request(paddr, access_size, flags, masterId);
} else if (randomReqType == 1) {
// generate packet for virtual network 1
requestType = MemCmd::ReadReq;
flags.set(Request::INST_FETCH);
- req->setVirt(0, 0x0, access_size, flags, 0x0, masterId);
+ req = new Request(0, 0x0, access_size, flags, masterId, 0x0, 0, 0);
req->setPaddr(paddr);
} else { // if (randomReqType == 2)
// generate packet for virtual network 2
requestType = MemCmd::WriteReq;
- req->setPhys(paddr, access_size, flags, masterId);
+ req = new Request(paddr, access_size, flags, masterId);
}
req->setThreadContext(id,0);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 09:54:05 +0000