summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base.cc10
-rw-r--r--src/cpu/o3/commit_impl.hh3
-rw-r--r--src/cpu/o3/cpu.cc15
-rw-r--r--src/cpu/o3/fetch_impl.hh7
-rw-r--r--src/cpu/o3/lsq_unit.hh5
-rw-r--r--src/cpu/simple/timing.cc4
6 files changed, 34 insertions, 10 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4017140a5..893b0e06b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -385,8 +385,7 @@ void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
-
- _cpuId = oldCPU->cpuId();
+ assert(_cpuId == oldCPU->cpuId());
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
@@ -418,11 +417,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(old_itb_port);
SlavePort &slavePort = old_itb_port->getSlavePort();
new_itb_port->bind(slavePort);
+ old_itb_port->unBind();
}
if (new_dtb_port && !new_dtb_port->isConnected()) {
assert(old_dtb_port);
SlavePort &slavePort = old_dtb_port->getSlavePort();
new_dtb_port->bind(slavePort);
+ old_dtb_port->unBind();
}
// Checker whether or not we have to transfer CheckerCPU
@@ -444,17 +445,20 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(old_checker_itb_port);
SlavePort &slavePort = old_checker_itb_port->getSlavePort();;
new_checker_itb_port->bind(slavePort);
+ old_checker_itb_port->unBind();
}
if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
assert(old_checker_dtb_port);
SlavePort &slavePort = old_checker_dtb_port->getSlavePort();;
new_checker_dtb_port->bind(slavePort);
+ old_checker_dtb_port->unBind();
}
}
}
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
+ oldCPU->interrupts = NULL;
if (FullSystem) {
for (ThreadID i = 0; i < size; ++i)
@@ -469,10 +473,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
// CPU.
if (!getInstPort().isConnected()) {
getInstPort().bind(oldCPU->getInstPort().getSlavePort());
+ oldCPU->getInstPort().unBind();
}
if (!getDataPort().isConnected()) {
getDataPort().bind(oldCPU->getDataPort().getSlavePort());
+ oldCPU->getDataPort().unBind();
}
}
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 45f5bc02b..31398c3d9 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -631,7 +631,8 @@ DefaultCommit<Impl>::tick()
wroteToTimeBuffer = false;
_nextStatus = Inactive;
- if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() &&
+ interrupt == NoFault) {
cpu->signalDrained();
drainPending = false;
return;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e8fc968b7..64c54e26a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -55,6 +55,7 @@
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Activity.hh"
+#include "debug/Drain.hh"
#include "debug/O3CPU.hh"
#include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh"
@@ -260,7 +261,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
if (!deferRegistration) {
_status = Running;
} else {
- _status = Idle;
+ _status = SwitchedOut;
}
if (params->checker) {
@@ -1119,9 +1120,8 @@ FullO3CPU<Impl>::drain(Event *drain_event)
DPRINTF(O3CPU, "Switching out\n");
// If the CPU isn't doing anything, then return immediately.
- if (_status == Idle || _status == SwitchedOut) {
+ if (_status == SwitchedOut)
return 0;
- }
drainCount = 0;
fetch.drain();
@@ -1142,6 +1142,8 @@ FullO3CPU<Impl>::drain(Event *drain_event)
wakeCPU();
activityRec.activity();
+ DPRINTF(Drain, "CPU not drained\n");
+
return 1;
} else {
return 0;
@@ -1160,7 +1162,7 @@ FullO3CPU<Impl>::resume()
changeState(SimObject::Running);
- if (_status == SwitchedOut || _status == Idle)
+ if (_status == SwitchedOut)
return;
assert(system->getMemoryMode() == Enums::timing);
@@ -1183,6 +1185,7 @@ FullO3CPU<Impl>::signalDrained()
BaseCPU::switchOut();
if (drainEvent) {
+ DPRINTF(Drain, "CPU done draining, processing drain event\n");
drainEvent->process();
drainEvent = NULL;
}
@@ -1237,6 +1240,10 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
assert(!tickEvent.scheduled() || tickEvent.squashed());
+ FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
+ if (oldO3CPU)
+ globalSeqNum = oldO3CPU->globalSeqNum;
+
// @todo: Figure out how to properly select the tid to put onto
// the active threads list.
ThreadID tid = 0;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b6eb25c08..81d70bd61 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -132,8 +132,10 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
// Get the size of an instruction.
instSize = sizeof(TheISA::MachInst);
- for (int i = 0; i < Impl::MaxThreads; i++)
+ for (int i = 0; i < Impl::MaxThreads; i++) {
+ cacheData[i] = NULL;
decoder[i] = new TheISA::Decoder(NULL);
+ }
}
template <class Impl>
@@ -346,7 +348,8 @@ DefaultFetch<Impl>::setIcache()
for (ThreadID tid = 0; tid < numThreads; tid++) {
// Create space to store a cache line.
- cacheData[tid] = new uint8_t[cacheBlkSize];
+ if (!cacheData[tid])
+ cacheData[tid] = new uint8_t[cacheBlkSize];
cacheDataPC[tid] = 0;
cacheDataValid[tid] = false;
}
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 7093b5fee..b886a2259 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -335,6 +335,11 @@ class LSQUnit {
std::memset(data, 0, sizeof(data));
}
+ ~SQEntry()
+ {
+ inst = NULL;
+ }
+
/** Constructs a store queue entry for a given instruction. */
SQEntry(DynInstPtr &_inst)
: inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index bae40eba4..6a9fe7efc 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -48,6 +48,7 @@
#include "cpu/simple/timing.hh"
#include "cpu/exetrace.hh"
#include "debug/Config.hh"
+#include "debug/Drain.hh"
#include "debug/ExecFaulting.hh"
#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
@@ -129,6 +130,7 @@ TimingSimpleCPU::drain(Event *drain_event)
} else {
changeState(SimObject::Draining);
drainEvent = drain_event;
+ DPRINTF(Drain, "CPU not drained\n");
return 1;
}
}
@@ -829,7 +831,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
void
TimingSimpleCPU::completeDrain()
{
- DPRINTF(Config, "Done draining\n");
+ DPRINTF(Drain, "CPU done draining, processing drain event\n");
changeState(SimObject::Drained);
drainEvent->process();
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 09:56:01 +0000