diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/fetch.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 11 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 85654cebc..0331cf07f 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -404,6 +404,9 @@ class DefaultFetch /** The cache line being fetched. */ uint8_t *cacheData[Impl::MaxThreads]; + /** The PC of the cacheline that has been loaded. */ + Addr cacheDataPC[Impl::MaxThreads]; + /** Size of instructions. */ int instSize; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index de883b5ba..4045492ca 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -357,6 +357,8 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) return; } + memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); + if (!drainPending) { // Wake up the CPU (if it went to sleep and was waiting on // this completion event). @@ -517,6 +519,11 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Align the fetch PC so it's at the start of a cache block. fetch_PC = icacheBlockAlignPC(fetch_PC); + // If we've already got the block, no need to try to fetch it again. + if (fetch_PC == cacheDataPC[tid]) { + return true; + } + // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. @@ -548,7 +555,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Build packet here. PacketPtr data_pkt = new Packet(mem_req, Packet::ReadReq, Packet::Broadcast); - data_pkt->dataStatic(cacheData[tid]); + data_pkt->dataDynamic(new uint8_t[cacheBlkSize]); + + cacheDataPC[tid] = fetch_PC; DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); |