diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/base.cc | 2 | ||||
| -rw-r--r-- | src/cpu/base.hh | 4 | ||||
| -rw-r--r-- | src/cpu/exetrace.cc | 19 | ||||
| -rw-r--r-- | src/cpu/m5legion_interface.h | 4 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 19 |
5 files changed, 41 insertions, 7 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 7cbbb0b96..31604ad58 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -96,7 +96,7 @@ CPUProgressEvent::description() #if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) - : MemObject(p->name), clock(p->clock), checkInterrupts(true), + : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true), params(p), number_of_threads(p->numberOfThreads), system(p->system), phase(p->phase) #else diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 1d9b6a93b..8c6b079da 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -70,12 +70,16 @@ class BaseCPU : public MemObject protected: // CPU's clock period in terms of the number of ticks of curTime. Tick clock; + // @todo remove me after debugging with legion done + Tick instCnt; public: // Tick currentTick; inline Tick frequency() const { return Clock::Frequency / clock; } inline Tick cycles(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } + // @todo remove me after debugging with legion done + Tick instCount() { return instCnt; } /** The next cycle the CPU should be scheduled, given a cache * access or quiesce event returning on this cycle. This function diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index f3b9b51b2..2ef89c57d 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -285,6 +285,7 @@ Trace::InstRecord::dump(ostream &outs) { bool compared = false; bool diffPC = false; + bool diffCC = false; bool diffInst = false; bool diffRegs = false; bool diffTpc = false; @@ -317,6 +318,11 @@ Trace::InstRecord::dump(ostream &outs) lgnPc = shared_data->pc & TheISA::PAddrImplMask; if (lgnPc != m5Pc) diffPC = true; + + if (shared_data->cycle_count != + thread->getCpuPtr()->instCount()) + diffCC = true; + if (shared_data->instruction != (SparcISA::MachInst)staticInst->machInst) { diffInst = true; @@ -385,8 +391,8 @@ Trace::InstRecord::dump(ostream &outs) if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) diffCleanwin = true; - if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc || - diffTstate || diffTt || diffHpstate || + if (diffPC || diffCC || diffInst || diffRegs || diffTpc || + diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || diffPstate || diffY || diffCcr || diffTl || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || @@ -394,6 +400,8 @@ Trace::InstRecord::dump(ostream &outs) outs << "Differences found between M5 and Legion:"; if (diffPC) outs << " [PC]"; + if (diffCC) + outs << " [CC]"; if (diffInst) outs << " [Instruction]"; if (diffRegs) @@ -445,6 +453,13 @@ Trace::InstRecord::dump(ostream &outs) << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex << lgnPc << endl << endl; + outs << right << setfill(' ') << setw(15) + << "M5 CC: " << "0x"<< setw(16) << setfill('0') + << hex << thread->getCpuPtr()->instCount() << endl; + outs << setfill(' ') << setw(15) + << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex + << shared_data->cycle_count << endl << endl; + outs << setfill(' ') << setw(15) << "M5 Inst: " << "0x"<< setw(8) << setfill('0') << hex << staticInst->machInst diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index 373fbeb11..bfb88485a 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -30,7 +30,7 @@ #include <unistd.h> -#define VERSION 0xA1000005 +#define VERSION 0xA1000006 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -42,6 +42,8 @@ typedef struct { uint64_t pc; uint64_t new_pc; + uint64_t cycle_count; + uint64_t new_cycle_count; uint32_t instruction; uint32_t new_instruction; uint64_t intregs[32]; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 67611e815..8db864153 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -295,8 +295,11 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) else dcache_latency = dcachePort.sendAtomic(pkt); dcache_access = true; - - assert(pkt->result == Packet::Success); +#if !defined(NDEBUG) + if (pkt->result != Packet::Success) + panic("Unable to find responder for address pa = %#X va = %#X\n", + pkt->req->getPaddr(), pkt->req->getVaddr()); +#endif data = pkt->get<T>(); if (req->isLocked()) { @@ -391,7 +394,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } dcache_access = true; - assert(pkt->result == Packet::Success); +#if !defined(NDEBUG) + if (pkt->result != Packet::Success) + panic("Unable to find responder for address pa = %#X va = %#X\n", + pkt->req->getPaddr(), pkt->req->getVaddr()); +#endif } if (req->isLocked()) { @@ -484,9 +491,15 @@ AtomicSimpleCPU::tick() dcache_access = false; // assume no dcache access preExecute(); + fault = curStaticInst->execute(this, traceData); postExecute(); + // @todo remove me after debugging with legion done + if (curStaticInst && (!curStaticInst->isMicroOp() || + curStaticInst->isLastMicroOp())) + instCnt++; + if (simulate_stalls) { Tick icache_stall = icache_latency - cycles(1); Tick dcache_stall = |