diff options
Diffstat (limited to 'src/cpu')
22 files changed, 43 insertions, 47 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 93cb6e071..6dd460cbe 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -52,10 +52,10 @@ from m5.params import * from m5.proxy import * from m5.util.fdthelper import * +from m5.objects.ClockedObject import ClockedObject from m5.objects.XBar import L2XBar from m5.objects.InstTracer import InstTracer from m5.objects.CPUTracers import ExeTracer -from m5.objects.MemObject import MemObject from m5.objects.SubSystem import SubSystem from m5.objects.ClockDomain import * from m5.objects.Platform import Platform @@ -99,7 +99,7 @@ elif buildEnv['TARGET_ISA'] == 'riscv': from m5.objects.RiscvISA import RiscvISA default_isa_class = RiscvISA -class BaseCPU(MemObject): +class BaseCPU(ClockedObject): type = 'BaseCPU' abstract = True cxx_header = "cpu/base.hh" diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 8e49fb103..a9f68bb26 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -126,7 +126,7 @@ CPUProgressEvent::description() const } BaseCPU::BaseCPU(Params *p, bool is_checker) - : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), + : ClockedObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), _instMasterId(p->system->getMasterId(this, "inst")), _dataMasterId(p->system->getMasterId(this, "data")), _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), @@ -421,7 +421,7 @@ BaseCPU::probeInstCommit(const StaticInstPtr &inst, Addr pc) void BaseCPU::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); using namespace Stats; @@ -462,7 +462,7 @@ BaseCPU::getPort(const string &if_name, PortID idx) else if (if_name == "icache_port") return getInstPort(); else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/cpu/base.hh b/src/cpu/base.hh index f9b24b923..f013a3e02 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -58,7 +58,7 @@ #include "arch/isa_traits.hh" #include "arch/microcode_rom.hh" #include "base/statistics.hh" -#include "mem/mem_object.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/full_system.hh" #include "sim/insttracer.hh" @@ -106,7 +106,7 @@ class CPUProgressEvent : public Event virtual const char *description() const; }; -class BaseCPU : public MemObject +class BaseCPU : public ClockedObject { protected: diff --git a/src/cpu/o3/checker.cc b/src/cpu/o3/checker.cc index 970af5300..16c5a8704 100644 --- a/src/cpu/o3/checker.cc +++ b/src/cpu/o3/checker.cc @@ -45,8 +45,6 @@ #include "cpu/checker/cpu_impl.hh" #include "params/O3Checker.hh" -class MemObject; - template class Checker<O3CPUImpl>; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 21cae444b..c2c48535f 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -76,7 +76,6 @@ template <class> class O3ThreadContext; class Checkpoint; -class MemObject; class Process; struct BaseCPUParams; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 49bc1ad73..b687a17e0 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -70,7 +70,6 @@ #include "debug/Decode.hh" #include "debug/Fetch.hh" #include "debug/Quiesce.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/request.hh" #include "params/BaseSimpleCPU.hh" diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index cd367b498..afe2b1447 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -47,7 +47,7 @@ #include "sim/sim_exit.hh" RubyDirectedTester::RubyDirectedTester(const Params *p) - : MemObject(p), + : ClockedObject(p), directedStartEvent([this]{ wakeup(); }, "Directed tick", false, Event::CPU_Tick_Pri), m_requests_to_complete(p->requests_to_complete), @@ -83,7 +83,7 @@ RubyDirectedTester::getPort(const std::string &if_name, PortID idx) { if (if_name != "cpuPort") { // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } else { if (idx >= static_cast<int>(ports.size())) { panic("RubyDirectedTester::getPort: unknown index %d\n", idx); diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 740843562..f0c694e82 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -34,16 +34,17 @@ #include <string> #include <vector> +#include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/DataBlock.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/common/TypeDefines.hh" -#include "mem/mem_object.hh" -#include "mem/packet.hh" #include "params/RubyDirectedTester.hh" +#include "sim/clocked_object.hh" class DirectedGenerator; -class RubyDirectedTester : public MemObject +class RubyDirectedTester : public ClockedObject { public: class CpuPort : public MasterPort diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index 9f90c9b41..5b513e42e 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -30,7 +30,7 @@ from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject class DirectedGenerator(SimObject): type = 'DirectedGenerator' @@ -52,7 +52,7 @@ class InvalidateGenerator(DirectedGenerator): cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" addr_increment_size = Param.Int(64, "address increment size") -class RubyDirectedTester(MemObject): +class RubyDirectedTester(ClockedObject): type = 'RubyDirectedTester' cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" cpuPort = VectorMasterPort("the cpu ports") diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc index 1a07205e6..5b542bc19 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc @@ -40,7 +40,6 @@ #include "base/random.hh" #include "base/statistics.hh" #include "debug/GarnetSyntheticTraffic.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/port.hh" #include "mem/request.hh" @@ -75,7 +74,7 @@ GarnetSyntheticTraffic::sendPkt(PacketPtr pkt) } GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p) - : MemObject(p), + : ClockedObject(p), tickEvent([this]{ tick(); }, "GarnetSyntheticTraffic tick", false, Event::CPU_Tick_Pri), cachePort("GarnetSyntheticTraffic", this), @@ -116,7 +115,7 @@ GarnetSyntheticTraffic::getPort(const std::string &if_name, PortID idx) if (if_name == "test") return cachePort; else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh index 7f9ca5f7c..3e77e9e0c 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh @@ -34,9 +34,9 @@ #include <set> #include "base/statistics.hh" -#include "mem/mem_object.hh" #include "mem/port.hh" #include "params/GarnetSyntheticTraffic.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/sim_exit.hh" #include "sim/sim_object.hh" @@ -53,7 +53,7 @@ enum TrafficType {BIT_COMPLEMENT_ = 0, NUM_TRAFFIC_PATTERNS_}; class Packet; -class GarnetSyntheticTraffic : public MemObject +class GarnetSyntheticTraffic : public ClockedObject { public: typedef GarnetSyntheticTrafficParams Params; diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py index 4c7772348..ba99db455 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py @@ -26,11 +26,11 @@ # # Authors: Tushar Krishna -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -class GarnetSyntheticTraffic(MemObject): +class GarnetSyntheticTraffic(ClockedObject): type = 'GarnetSyntheticTraffic' cxx_header = \ "cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh" diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 5585b1f70..b4eb0b528 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -41,9 +41,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class MemTest(MemObject): +class MemTest(ClockedObject): type = 'MemTest' cxx_header = "cpu/testers/memtest/memtest.hh" diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 346f88246..93a6ac6b9 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -48,7 +48,6 @@ #include "base/statistics.hh" #include "base/trace.hh" #include "debug/MemTest.hh" -#include "mem/mem_object.hh" #include "sim/sim_exit.hh" #include "sim/stats.hh" #include "sim/system.hh" @@ -85,7 +84,7 @@ MemTest::sendPkt(PacketPtr pkt) { } MemTest::MemTest(const Params *p) - : MemObject(p), + : ClockedObject(p), tickEvent([this]{ tick(); }, name()), noRequestEvent([this]{ noRequest(); }, name()), noResponseEvent([this]{ noResponse(); }, name()), @@ -130,7 +129,7 @@ MemTest::getPort(const std::string &if_name, PortID idx) if (if_name == "port") return port; else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void @@ -197,7 +196,7 @@ MemTest::completeRequest(PacketPtr pkt, bool functional) void MemTest::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); using namespace Stats; diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index b429fed69..f536f0369 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -49,8 +49,9 @@ #include <unordered_map> #include "base/statistics.hh" -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/MemTest.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/stats.hh" @@ -67,7 +68,7 @@ * both requests and responses, thus checking that the memory-system * is making progress. */ -class MemTest : public MemObject +class MemTest : public ClockedObject { public: diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index cb23688c4..30af47586 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -50,7 +50,7 @@ #include "sim/system.hh" RubyTester::RubyTester(const Params *p) - : MemObject(p), + : ClockedObject(p), checkStartEvent([this]{ wakeup(); }, "RubyTester tick", false, Event::CPU_Tick_Pri), _masterId(p->system->getMasterId(this)), @@ -134,7 +134,7 @@ RubyTester::getPort(const std::string &if_name, PortID idx) if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && if_name != "cpuDataPort") { // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } else { if (if_name == "cpuInstPort") { if (idx > m_num_inst_only_ports) { diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index 3ca71f608..4ac553b4c 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -47,13 +47,14 @@ #include <vector> #include "cpu/testers/rubytest/CheckTable.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/common/TypeDefines.hh" #include "params/RubyTester.hh" +#include "sim/clocked_object.hh" -class RubyTester : public MemObject +class RubyTester : public ClockedObject { public: class CpuPort : public MasterPort diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index 2ac1697fd..ecf52b668 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -28,9 +28,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class RubyTester(MemObject): +class RubyTester(ClockedObject): type = 'RubyTester' cxx_header = "cpu/testers/rubytest/RubyTester.hh" num_cpus = Param.Int("number of cpus / RubyPorts") diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py index 94e3319d5..7fd8b3066 100644 --- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py +++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py @@ -39,7 +39,7 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject # Types of Stream Generators. # Those are orthogonal to the other generators in the TrafficGen @@ -55,7 +55,7 @@ class StreamGenType(Enum): vals = [ 'none', 'fixed', 'random' ] # controllers, or function as a black-box replacement for system # components that are not yet modelled in detail, e.g. a video engine # or baseband subsystem in an SoC. -class BaseTrafficGen(MemObject): +class BaseTrafficGen(ClockedObject): type = 'BaseTrafficGen' abstract = True cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc index 80fa8a9d6..43a1b831a 100644 --- a/src/cpu/testers/traffic_gen/base.cc +++ b/src/cpu/testers/traffic_gen/base.cc @@ -68,7 +68,7 @@ using namespace std; BaseTrafficGen::BaseTrafficGen(const BaseTrafficGenParams* p) - : MemObject(p), + : ClockedObject(p), system(p->system), elasticReq(p->elastic_req), progressCheck(p->progress_check), @@ -94,14 +94,14 @@ BaseTrafficGen::getPort(const string &if_name, PortID idx) if (if_name == "port") { return port; } else { - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } } void BaseTrafficGen::init() { - MemObject::init(); + ClockedObject::init(); if (!port.isConnected()) fatal("The port of %s is not connected!\n", name()); diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh index 2443e6223..811770fe4 100644 --- a/src/cpu/testers/traffic_gen/base.hh +++ b/src/cpu/testers/traffic_gen/base.hh @@ -46,8 +46,8 @@ #include <tuple> #include "base/statistics.hh" -#include "mem/mem_object.hh" #include "mem/qport.hh" +#include "sim/clocked_object.hh" class BaseGen; class StreamGen; @@ -63,7 +63,7 @@ struct BaseTrafficGenParams; * system components that are not yet modelled in detail, e.g. a video * engine or baseband subsystem. */ -class BaseTrafficGen : public MemObject +class BaseTrafficGen : public ClockedObject { friend class BaseGen; diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index e3b6af9da..574193d0e 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -36,7 +36,6 @@ #include "cpu/base.hh" #include "cpu/profile.hh" #include "cpu/thread_context.hh" -#include "mem/mem_object.hh" #include "sim/process.hh" class EndQuiesceEvent; |