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-rw-r--r--src/cpu/base.cc59
-rw-r--r--src/cpu/base.hh6
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.cc8
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.hh4
-rw-r--r--src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc6
-rw-r--r--src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh4
-rw-r--r--src/cpu/testers/memtest/memtest.cc6
-rw-r--r--src/cpu/testers/memtest/memtest.hh4
-rw-r--r--src/cpu/testers/rubytest/RubyTester.cc12
-rw-r--r--src/cpu/testers/rubytest/RubyTester.hh4
-rw-r--r--src/cpu/testers/traffic_gen/base.cc6
-rw-r--r--src/cpu/testers/traffic_gen/base.hh4
-rw-r--r--src/cpu/trace/trace_cpu.cc4
13 files changed, 64 insertions, 63 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 09de64646..8dfcf3cda 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -449,19 +449,18 @@ BaseCPU::regStats()
threadContexts[0]->regStats(name());
}
-BaseMasterPort &
-BaseCPU::getMasterPort(const string &if_name, PortID idx)
+Port &
+BaseCPU::getPort(const string &if_name, PortID idx)
{
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
- // of getDataPort and getInstPort. In all cases there methods
- // return a MasterPort pointer.
+ // of getDataPort and getInstPort.
if (if_name == "dcache_port")
return getDataPort();
else if (if_name == "icache_port")
return getInstPort();
else
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
@@ -621,21 +620,18 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
ThreadContext::compare(oldTC, newTC);
*/
- BaseMasterPort *old_itb_port =
- oldTC->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *old_dtb_port =
- oldTC->getDTBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_itb_port =
- newTC->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_dtb_port =
- newTC->getDTBPtr()->getTableWalkerMasterPort();
+ Port *old_itb_port = oldTC->getITBPtr()->getTableWalkerPort();
+ Port *old_dtb_port = oldTC->getDTBPtr()->getTableWalkerPort();
+ Port *new_itb_port = newTC->getITBPtr()->getTableWalkerPort();
+ Port *new_dtb_port = newTC->getDTBPtr()->getTableWalkerPort();
// Move over any table walker ports if they exist
if (new_itb_port) {
assert(!new_itb_port->isConnected());
assert(old_itb_port);
assert(old_itb_port->isConnected());
- BaseSlavePort &slavePort = old_itb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_itb_port)->getSlavePort();
old_itb_port->unbind();
new_itb_port->bind(slavePort);
}
@@ -643,7 +639,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(!new_dtb_port->isConnected());
assert(old_dtb_port);
assert(old_dtb_port->isConnected());
- BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_dtb_port)->getSlavePort();
old_dtb_port->unbind();
new_dtb_port->bind(slavePort);
}
@@ -655,14 +652,14 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
if (oldChecker && newChecker) {
- BaseMasterPort *old_checker_itb_port =
- oldChecker->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *old_checker_dtb_port =
- oldChecker->getDTBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_checker_itb_port =
- newChecker->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_checker_dtb_port =
- newChecker->getDTBPtr()->getTableWalkerMasterPort();
+ Port *old_checker_itb_port =
+ oldChecker->getITBPtr()->getTableWalkerPort();
+ Port *old_checker_dtb_port =
+ oldChecker->getDTBPtr()->getTableWalkerPort();
+ Port *new_checker_itb_port =
+ newChecker->getITBPtr()->getTableWalkerPort();
+ Port *new_checker_dtb_port =
+ newChecker->getDTBPtr()->getTableWalkerPort();
newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
@@ -672,8 +669,9 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(!new_checker_itb_port->isConnected());
assert(old_checker_itb_port);
assert(old_checker_itb_port->isConnected());
- BaseSlavePort &slavePort =
- old_checker_itb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_checker_itb_port)->
+ getSlavePort();
old_checker_itb_port->unbind();
new_checker_itb_port->bind(slavePort);
}
@@ -681,8 +679,9 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(!new_checker_dtb_port->isConnected());
assert(old_checker_dtb_port);
assert(old_checker_dtb_port->isConnected());
- BaseSlavePort &slavePort =
- old_checker_dtb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_checker_dtb_port)->
+ getSlavePort();
old_checker_dtb_port->unbind();
new_checker_dtb_port->bind(slavePort);
}
@@ -709,13 +708,15 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
// we are switching to.
assert(!getInstPort().isConnected());
assert(oldCPU->getInstPort().isConnected());
- BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
+ auto &inst_peer_port =
+ dynamic_cast<BaseMasterPort &>(oldCPU->getInstPort()).getSlavePort();
oldCPU->getInstPort().unbind();
getInstPort().bind(inst_peer_port);
assert(!getDataPort().isConnected());
assert(oldCPU->getDataPort().isConnected());
- BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
+ auto &data_peer_port =
+ dynamic_cast<BaseMasterPort &>(oldCPU->getDataPort()).getSlavePort();
oldCPU->getDataPort().unbind();
getDataPort().bind(data_peer_port);
}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 8673d2330..9075d4b33 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -180,7 +180,7 @@ class BaseCPU : public MemObject
MasterID instMasterId() { return _instMasterId; }
/**
- * Get a master port on this CPU. All CPUs have a data and
+ * Get a port on this CPU. All CPUs have a data and
* instruction port, and this method uses getDataPort and
* getInstPort of the subclasses to resolve the two ports.
*
@@ -189,8 +189,8 @@ class BaseCPU : public MemObject
*
* @return a reference to the port with the given name
*/
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/** Get cpu task id */
uint32_t taskId() const { return _taskId; }
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc
index be7f3c256..cd367b498 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -78,15 +78,15 @@ RubyDirectedTester::init()
generator->setDirectedTester(this);
}
-BaseMasterPort &
-RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+RubyDirectedTester::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "cpuPort") {
// pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
} else {
if (idx >= static_cast<int>(ports.size())) {
- panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
+ panic("RubyDirectedTester::getPort: unknown index %d\n", idx);
}
return *ports[idx];
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh
index 00278a65e..0f519762c 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -67,8 +67,8 @@ class RubyDirectedTester : public MemObject
RubyDirectedTester(const Params *p);
~RubyDirectedTester();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
MasterPort* getCpuPort(int idx);
diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
index 0ced9df84..1a07205e6 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -110,13 +110,13 @@ GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p)
name(), id);
}
-BaseMasterPort &
-GarnetSyntheticTraffic::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+GarnetSyntheticTraffic::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "test")
return cachePort;
else
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
index 3da7e2774..a18f5bbda 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
@@ -64,8 +64,8 @@ class GarnetSyntheticTraffic : public MemObject
// main simulation loop (one cycle)
void tick();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* Print state of address in memory system via PrintReq (for
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 09e7e88a1..346f88246 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -124,13 +124,13 @@ MemTest::MemTest(const Params *p)
schedule(noResponseEvent, clockEdge(progressCheck));
}
-BaseMasterPort &
-MemTest::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+MemTest::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port")
return port;
else
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index 023b878c9..8e8f73996 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -77,8 +77,8 @@ class MemTest : public MemObject
virtual void regStats();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
protected:
diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc
index 93754467d..cb23688c4 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -128,17 +128,17 @@ RubyTester::init()
m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
}
-BaseMasterPort &
-RubyTester::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+RubyTester::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
if_name != "cpuDataPort") {
// pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
} else {
if (if_name == "cpuInstPort") {
if (idx > m_num_inst_only_ports) {
- panic("RubyTester::getMasterPort: unknown inst port %d\n",
+ panic("RubyTester::getPort: unknown inst port %d\n",
idx);
}
//
@@ -147,7 +147,7 @@ RubyTester::getMasterPort(const std::string &if_name, PortID idx)
return *readPorts[idx];
} else if (if_name == "cpuInstDataPort") {
if (idx > m_num_inst_data_ports) {
- panic("RubyTester::getMasterPort: unknown inst+data port %d\n",
+ panic("RubyTester::getPort: unknown inst+data port %d\n",
idx);
}
int read_idx = idx + m_num_inst_only_ports;
@@ -162,7 +162,7 @@ RubyTester::getMasterPort(const std::string &if_name, PortID idx)
//
if (idx > (static_cast<int>(readPorts.size()) -
(m_num_inst_only_ports + m_num_inst_data_ports))) {
- panic("RubyTester::getMasterPort: unknown data port %d\n",
+ panic("RubyTester::getPort: unknown data port %d\n",
idx);
}
int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports;
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index 007035977..2509aa2cd 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -94,8 +94,8 @@ class RubyTester : public MemObject
RubyTester(const Params *p);
~RubyTester();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
bool isInstOnlyCpuPort(int idx);
bool isInstDataCpuPort(int idx);
diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc
index ad4f67d9d..80fa8a9d6 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -88,13 +88,13 @@ BaseTrafficGen::~BaseTrafficGen()
{
}
-BaseMasterPort&
-BaseTrafficGen::getMasterPort(const string& if_name, PortID idx)
+Port &
+BaseTrafficGen::getPort(const string &if_name, PortID idx)
{
if (if_name == "port") {
return port;
} else {
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh
index 272dcb587..2443e6223 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -182,8 +182,8 @@ class BaseTrafficGen : public MemObject
~BaseTrafficGen();
- BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void init() override;
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 2b198e966..6e499dbac 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -108,13 +108,13 @@ TraceCPU::takeOverFrom(BaseCPU *oldCPU)
// Unbind the ports of the old CPU and bind the ports of the TraceCPU.
assert(!getInstPort().isConnected());
assert(oldCPU->getInstPort().isConnected());
- BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
+ Port &inst_peer_port = oldCPU->getInstPort().getSlavePort();
oldCPU->getInstPort().unbind();
getInstPort().bind(inst_peer_port);
assert(!getDataPort().isConnected());
assert(oldCPU->getDataPort().isConnected());
- BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
+ Port &data_peer_port = oldCPU->getDataPort().getSlavePort();
oldCPU->getDataPort().unbind();
getDataPort().bind(data_peer_port);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-28 10:19:22 +0000