diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 5 | ||||
| -rw-r--r-- | src/cpu/inorder/comm.hh | 8 | ||||
| -rw-r--r-- | src/cpu/inorder/inorder_dyn_inst.cc | 5 | ||||
| -rw-r--r-- | src/cpu/inorder/pipeline_stage.cc | 32 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/mult_div_unit.cc | 5 |
5 files changed, 24 insertions, 31 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index a5e81a090..9faadc68c 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -34,9 +34,8 @@ from BaseCPU import BaseCPU class InOrderCPU(BaseCPU): type = 'InOrderCPU' activity = Param.Unsigned(0, "Initial count") - numThreads = Param.Unsigned(1, "number of HW thread contexts") - cachePorts = Param.Unsigned("Cache Ports") + cachePorts = Param.Unsigned(2, "Cache Ports") stageWidth = Param.Unsigned(1, "Stage width") fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from") @@ -66,7 +65,7 @@ class InOrderCPU(BaseCPU): functionTraceStart = Param.Tick(0, "Cycle to start function trace") stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU") - memBlockSize = Param.Unsigned("Memory Block Size") + memBlockSize = Param.Unsigned(64, "Memory Block Size") multLatency = Param.Unsigned(1, "Latency for Multiply Operations") multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations") diff --git a/src/cpu/inorder/comm.hh b/src/cpu/inorder/comm.hh index c687a9ab4..18bb24169 100644 --- a/src/cpu/inorder/comm.hh +++ b/src/cpu/inorder/comm.hh @@ -53,6 +53,14 @@ struct InterStageStruct { uint64_t nextPC; InstSeqNum squashedSeqNum; bool includeSquashInst; + + InterStageStruct() + :size(0), squash(false), + branchMispredict(false), branchTaken(false), + mispredPC(0), nextPC(0), + squashedSeqNum(0), includeSquashInst(false) + { } + }; /** Turn This into a Class */ diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index 3a45bd01e..e5fac7141 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -84,7 +84,10 @@ InOrderDynInst::InOrderDynInst(StaticInstPtr &_staticInst) InOrderDynInst::InOrderDynInst() : traceData(NULL), cpu(cpu) -{ initVars(); } +{ + seqNum = 0; + initVars(); +} int InOrderDynInst::instcount = 0; diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index f356c0e1a..4ded50bf0 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -38,35 +38,10 @@ using namespace std; using namespace ThePipeline; PipelineStage::PipelineStage(Params *params, unsigned stage_num) - : numThreads(ThePipeline::MaxThreads) { - stageNum = stage_num; - stageWidth = ThePipeline::StageWidth; - - _status = Inactive; - - prevStageValid = false; - nextStageValid = false; - - // Init. structures - for(int tid=0; tid < numThreads; tid++) { - stageStatus[tid] = Idle; - - for (int stNum = 0; stNum < NumStages; stNum++) { - stalls[tid].stage[stNum] = false; - } - stalls[tid].resources.clear(); - - if (stageNum < BackEndStartStage) - lastStallingStage[tid] = BackEndStartStage - 1; - else - lastStallingStage[tid] = NumStages - 1; - } - - stageBufferMax = ThePipeline::interStageBuffSize[stage_num]; + init(params, stage_num); } - void PipelineStage::init(Params *params, unsigned stage_num) { @@ -189,7 +164,7 @@ PipelineStage::setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr) // Setup wire to write information to proper place in stage queue. nextStage = nextStageQueue->getWire(0); - + nextStage->size = 0; nextStageValid = true; } @@ -682,6 +657,9 @@ PipelineStage::tick() bool status_change = false; + if (nextStageValid) + nextStage->size = 0; + toNextStageIndex = 0; sortInsts(); diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc index abef11247..e98e97be7 100644 --- a/src/cpu/inorder/resources/mult_div_unit.cc +++ b/src/cpu/inorder/resources/mult_div_unit.cc @@ -57,6 +57,8 @@ MultDivUnit::MultDivUnit(string res_name, int res_id, int res_width, div32RepeatRate = params->div32RepeatRate; div32Latency = params->div32Latency; + + lastMDUCycle = 0; } void @@ -150,6 +152,9 @@ MultDivUnit::getSlot(DynInstPtr inst) rval); if (rval != -1) { + lastMDUCycle = curTick; + lastOpType = inst->opClass(); + lastInstName = inst->staticInst->getName(); } return rval; |