diff options
Diffstat (limited to 'src/dev/alpha')
| -rw-r--r-- | src/dev/alpha/AlphaBackdoor.py (renamed from src/dev/alpha/AlphaConsole.py) | 6 | ||||
| -rw-r--r-- | src/dev/alpha/SConscript | 7 | ||||
| -rw-r--r-- | src/dev/alpha/Tsunami.py | 10 | ||||
| -rw-r--r-- | src/dev/alpha/access.h | 34 | ||||
| -rw-r--r-- | src/dev/alpha/backdoor.cc (renamed from src/dev/alpha/console.cc) | 42 | ||||
| -rw-r--r-- | src/dev/alpha/backdoor.hh (renamed from src/dev/alpha/console.hh) | 22 | ||||
| -rw-r--r-- | src/dev/alpha/tsunami.cc | 16 | ||||
| -rw-r--r-- | src/dev/alpha/tsunami.hh | 12 | ||||
| -rw-r--r-- | src/dev/alpha/tsunami_cchip.cc | 10 | ||||
| -rw-r--r-- | src/dev/alpha/tsunami_io.cc | 404 | ||||
| -rw-r--r-- | src/dev/alpha/tsunami_io.hh | 228 | ||||
| -rw-r--r-- | src/dev/alpha/tsunami_pchip.cc | 11 | ||||
| -rw-r--r-- | src/dev/alpha/tsunami_pchip.hh | 2 |
13 files changed, 137 insertions, 667 deletions
diff --git a/src/dev/alpha/AlphaConsole.py b/src/dev/alpha/AlphaBackdoor.py index 43c7ef954..fa9627164 100644 --- a/src/dev/alpha/AlphaConsole.py +++ b/src/dev/alpha/AlphaBackdoor.py @@ -30,9 +30,9 @@ from m5.params import * from m5.proxy import * from Device import BasicPioDevice -class AlphaConsole(BasicPioDevice): - type = 'AlphaConsole' +class AlphaBackdoor(BasicPioDevice): + type = 'AlphaBackdoor' cpu = Param.BaseCPU(Parent.cpu[0], "Processor") disk = Param.SimpleDisk("Simple Disk") - sim_console = Param.SimConsole(Parent.any, "The Simulator Console") + terminal = Param.Terminal(Parent.any, "The console terminal") system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript index 2292c3c57..4dbb73903 100644 --- a/src/dev/alpha/SConscript +++ b/src/dev/alpha/SConscript @@ -32,15 +32,14 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha': - SimObject('AlphaConsole.py') + SimObject('AlphaBackdoor.py') SimObject('Tsunami.py') - Source('console.cc') + Source('backdoor.cc') Source('tsunami.cc') Source('tsunami_cchip.cc') Source('tsunami_io.cc') Source('tsunami_pchip.cc') - TraceFlag('AlphaConsole') - TraceFlag('MC146818') + TraceFlag('AlphaBackdoor') TraceFlag('Tsunami') diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py index 484976c09..5440486b6 100644 --- a/src/dev/alpha/Tsunami.py +++ b/src/dev/alpha/Tsunami.py @@ -28,12 +28,12 @@ from m5.params import * from m5.proxy import * +from BadDevice import BadDevice +from AlphaBackdoor import AlphaBackdoor from Device import BasicPioDevice, IsaFake, BadAddr +from Pci import PciConfigAll from Platform import Platform -from AlphaConsole import AlphaConsole from Uart import Uart8250 -from Pci import PciConfigAll -from BadDevice import BadDevice class TsunamiCChip(BasicPioDevice): type = 'TsunamiCChip' @@ -87,7 +87,7 @@ class Tsunami(Platform): fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') io = TsunamiIO(pio_addr=0x801fc000000) uart = Uart8250(pio_addr=0x801fc0003f8) - console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk) + backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the @@ -120,4 +120,4 @@ class Tsunami(Platform): self.fb.pio = bus.port self.io.pio = bus.port self.uart.pio = bus.port - self.console.pio = bus.port + self.backdoor.pio = bus.port diff --git a/src/dev/alpha/access.h b/src/dev/alpha/access.h index 4adeaf84b..72eb4950a 100644 --- a/src/dev/alpha/access.h +++ b/src/dev/alpha/access.h @@ -45,31 +45,31 @@ typedef unsigned long uint64_t; // This structure hacked up from simos struct AlphaAccess { - uint32_t last_offset; // 00: must be first field - uint32_t version; // 04: - uint32_t numCPUs; // 08: - uint32_t intrClockFrequency; // 0C: Hz - uint64_t cpuClock; // 10: MHz - uint64_t mem_size; // 18: + uint32_t last_offset; // 00: must be first field + uint32_t version; // 04: + uint32_t numCPUs; // 08: + uint32_t intrClockFrequency; // 0C: Hz + uint64_t cpuClock; // 10: MHz + uint64_t mem_size; // 18: // Loaded kernel - uint64_t kernStart; // 20: - uint64_t kernEnd; // 28: - uint64_t entryPoint; // 30: + uint64_t kernStart; // 20: + uint64_t kernEnd; // 28: + uint64_t entryPoint; // 30: // console disk stuff - uint64_t diskUnit; // 38: - uint64_t diskCount; // 40: - uint64_t diskPAddr; // 48: - uint64_t diskBlock; // 50: - uint64_t diskOperation; // 58: + uint64_t diskUnit; // 38: + uint64_t diskCount; // 40: + uint64_t diskPAddr; // 48: + uint64_t diskBlock; // 50: + uint64_t diskOperation; // 58: // console simple output stuff - uint64_t outputChar; // 60: Placeholder for output - uint64_t inputChar; // 68: Placeholder for input + uint64_t outputChar; // 60: Placeholder for output + uint64_t inputChar; // 68: Placeholder for input // MP boot - uint64_t cpuStack[64]; // 70: + uint64_t cpuStack[64]; // 70: }; #endif // __ALPHA_ACCESS_H__ diff --git a/src/dev/alpha/console.cc b/src/dev/alpha/backdoor.cc index 493a21f99..66f682e66 100644 --- a/src/dev/alpha/console.cc +++ b/src/dev/alpha/backdoor.cc @@ -32,7 +32,7 @@ */ /** @file - * Alpha Console Definition + * Alpha Console Backdoor Definition */ #include <cstddef> @@ -44,21 +44,21 @@ #include "base/trace.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" -#include "dev/alpha/console.hh" +#include "dev/alpha/backdoor.hh" #include "dev/platform.hh" -#include "dev/simconsole.hh" #include "dev/simple_disk.hh" +#include "dev/terminal.hh" #include "mem/packet.hh" #include "mem/packet_access.hh" #include "mem/physical.hh" -#include "params/AlphaConsole.hh" +#include "params/AlphaBackdoor.hh" #include "sim/sim_object.hh" using namespace std; using namespace AlphaISA; -AlphaConsole::AlphaConsole(const Params *p) - : BasicPioDevice(p), disk(p->disk), console(p->sim_console), +AlphaBackdoor::AlphaBackdoor(const Params *p) + : BasicPioDevice(p), disk(p->disk), terminal(p->terminal), system(p->system), cpu(p->cpu) { @@ -81,10 +81,10 @@ AlphaConsole::AlphaConsole(const Params *p) } void -AlphaConsole::startup() +AlphaBackdoor::startup() { system->setAlphaAccess(pioAddr); - alphaAccess->numCPUs = system->getNumCPUs(); + alphaAccess->numCPUs = system->numContexts(); alphaAccess->kernStart = system->getKernelStart(); alphaAccess->kernEnd = system->getKernelEnd(); alphaAccess->entryPoint = system->getKernelEntry(); @@ -94,7 +94,7 @@ AlphaConsole::startup() } Tick -AlphaConsole::read(PacketPtr pkt) +AlphaBackdoor::read(PacketPtr pkt) { /** XXX Do we want to push the addr munging to a bus brige or something? So @@ -132,14 +132,14 @@ AlphaConsole::read(PacketPtr pkt) */ pkt->setBadAddress(); } - DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, + DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, pkt->get<uint32_t>()); break; case sizeof(uint64_t): switch (daddr) { case offsetof(AlphaAccess, inputChar): - pkt->set(console->console_in()); + pkt->set(terminal->console_in()); break; case offsetof(AlphaAccess, cpuClock): pkt->set(alphaAccess->cpuClock); @@ -183,7 +183,7 @@ AlphaConsole::read(PacketPtr pkt) else panic("Unknown 64bit access, %#x\n", daddr); } - DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, + DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, pkt->get<uint64_t>()); break; default: @@ -193,7 +193,7 @@ AlphaConsole::read(PacketPtr pkt) } Tick -AlphaConsole::write(PacketPtr pkt) +AlphaBackdoor::write(PacketPtr pkt) { assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); Addr daddr = pkt->getAddr() - pioAddr; @@ -228,7 +228,7 @@ AlphaConsole::write(PacketPtr pkt) break; case offsetof(AlphaAccess, outputChar): - console->out((char)(val & 0xff)); + terminal->out((char)(val & 0xff)); break; default: @@ -248,7 +248,7 @@ AlphaConsole::write(PacketPtr pkt) } void -AlphaConsole::Access::serialize(ostream &os) +AlphaBackdoor::Access::serialize(ostream &os) { SERIALIZE_SCALAR(last_offset); SERIALIZE_SCALAR(version); @@ -270,7 +270,7 @@ AlphaConsole::Access::serialize(ostream &os) } void -AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) +AlphaBackdoor::Access::unserialize(Checkpoint *cp, const std::string §ion) { UNSERIALIZE_SCALAR(last_offset); UNSERIALIZE_SCALAR(version); @@ -292,19 +292,19 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) } void -AlphaConsole::serialize(ostream &os) +AlphaBackdoor::serialize(ostream &os) { alphaAccess->serialize(os); } void -AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion) +AlphaBackdoor::unserialize(Checkpoint *cp, const std::string §ion) { alphaAccess->unserialize(cp, section); } -AlphaConsole * -AlphaConsoleParams::create() +AlphaBackdoor * +AlphaBackdoorParams::create() { - return new AlphaConsole(this); + return new AlphaBackdoor(this); } diff --git a/src/dev/alpha/console.hh b/src/dev/alpha/backdoor.hh index e77a7fad6..ad3c79823 100644 --- a/src/dev/alpha/console.hh +++ b/src/dev/alpha/backdoor.hh @@ -29,28 +29,28 @@ */ /** @file - * System Console Interface + * System Console Backdoor Interface */ -#ifndef __ALPHA_CONSOLE_HH__ -#define __ALPHA_CONSOLE_HH__ +#ifndef __DEV_ALPHA_BACKDOOR_HH__ +#define __DEV_ALPHA_BACKDOOR_HH__ #include "base/range.hh" #include "dev/alpha/access.h" #include "dev/io_device.hh" -#include "params/AlphaConsole.hh" +#include "params/AlphaBackdoor.hh" #include "sim/host.hh" #include "sim/sim_object.hh" class BaseCPU; -class SimConsole; +class Terminal; class AlphaSystem; class SimpleDisk; /** * Memory mapped interface to the system console. This device * represents a shared data region between the OS Kernel and the - * System Console. + * System Console Backdoor. * * The system console is a small standalone program that is initially * run when the system boots. It contains the necessary code to @@ -72,7 +72,7 @@ class SimpleDisk; * primarily used doing boot before the kernel has loaded its device * drivers. */ -class AlphaConsole : public BasicPioDevice +class AlphaBackdoor : public BasicPioDevice { protected: struct Access : public AlphaAccess @@ -90,7 +90,7 @@ class AlphaConsole : public BasicPioDevice SimpleDisk *disk; /** the system console (the terminal) is accessable from the console */ - SimConsole *console; + Terminal *terminal; /** a pointer to the system we are running in */ AlphaSystem *system; @@ -99,8 +99,8 @@ class AlphaConsole : public BasicPioDevice BaseCPU *cpu; public: - typedef AlphaConsoleParams Params; - AlphaConsole(const Params *p); + typedef AlphaBackdoorParams Params; + AlphaBackdoor(const Params *p); const Params * params() const @@ -123,4 +123,4 @@ class AlphaConsole : public BasicPioDevice virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -#endif // __ALPHA_CONSOLE_HH__ +#endif // __DEV_ALPHA_BACKDOOR_HH__ diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc index 5bc0de5da..b6478fe22 100644 --- a/src/dev/alpha/tsunami.cc +++ b/src/dev/alpha/tsunami.cc @@ -37,11 +37,11 @@ #include <vector> #include "cpu/intr_control.hh" -#include "dev/simconsole.hh" #include "dev/alpha/tsunami_cchip.hh" #include "dev/alpha/tsunami_pchip.hh" #include "dev/alpha/tsunami_io.hh" #include "dev/alpha/tsunami.hh" +#include "dev/terminal.hh" #include "sim/system.hh" using namespace std; @@ -96,11 +96,23 @@ Tsunami::pciToDma(Addr pciAddr) const Addr -Tsunami::calcConfigAddr(int bus, int dev, int func) +Tsunami::calcPciConfigAddr(int bus, int dev, int func) { return pchip->calcConfigAddr(bus, dev, func); } +Addr +Tsunami::calcPciIOAddr(Addr addr) +{ + return pchip->calcIOAddr(addr); +} + +Addr +Tsunami::calcPciMemAddr(Addr addr) +{ + return pchip->calcMemAddr(addr); +} + void Tsunami::serialize(std::ostream &os) { diff --git a/src/dev/alpha/tsunami.hh b/src/dev/alpha/tsunami.hh index 44c5d41a4..64aafe533 100644 --- a/src/dev/alpha/tsunami.hh +++ b/src/dev/alpha/tsunami.hh @@ -116,7 +116,17 @@ class Tsunami : public Platform /** * Calculate the configuration address given a bus/dev/func. */ - virtual Addr calcConfigAddr(int bus, int dev, int func); + virtual Addr calcPciConfigAddr(int bus, int dev, int func); + + /** + * Calculate the address for an IO location on the PCI bus. + */ + virtual Addr calcPciIOAddr(Addr addr); + + /** + * Calculate the address for a memory location on the PCI bus. + */ + virtual Addr calcPciMemAddr(Addr addr); /** * Serialize this object to the given output stream. diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc index 891fe17da..52a2aea14 100644 --- a/src/dev/alpha/tsunami_cchip.cc +++ b/src/dev/alpha/tsunami_cchip.cc @@ -109,8 +109,14 @@ TsunamiCChip::read(PacketPtr pkt) panic("TSDEV_CC_MTR not implemeted\n"); break; case TSDEV_CC_MISC: - pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF | - (pkt->req->getCpuNum() & 0x3)); + pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) | + (pkt->req->contextId() & 0x3)); + // currently, FS cannot handle MT so contextId and + // cpuId are effectively the same, don't know if it will + // matter if FS becomes MT enabled. I suspect no because + // we are currently able to boot up to 64 procs anyway + // which would render the CPUID of this register useless + // anyway break; case TSDEV_CC_AAR0: case TSDEV_CC_AAR1: diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc index 710aca48d..9c88904e3 100644 --- a/src/dev/alpha/tsunami_io.cc +++ b/src/dev/alpha/tsunami_io.cc @@ -42,7 +42,6 @@ #include "base/time.hh" #include "base/trace.hh" -#include "dev/pitreg.h" #include "dev/rtcreg.h" #include "dev/alpha/tsunami_cchip.hh" #include "dev/alpha/tsunami.hh" @@ -57,386 +56,15 @@ using namespace std; //Should this be AlphaISA? using namespace TheISA; -TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, - const TsunamiIO::Params *p) - : _name(n), event(tsunami, p->frequency), addr(0) +TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) + : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), + tsunami(p->tsunami) { - memset(clock_data, 0, sizeof(clock_data)); - stat_regA = RTCA_32768HZ | RTCA_1024HZ; - stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR; - - year = p->time.tm_year; - - if (p->year_is_bcd) { - // The datasheet says that the year field can be either BCD or - // years since 1900. Linux seems to be happy with years since - // 1900. - year = year % 100; - int tens = year / 10; - int ones = year % 10; - year = (tens << 4) + ones; - } - - // Unix is 0-11 for month, data seet says start at 1 - mon = p->time.tm_mon + 1; - mday = p->time.tm_mday; - hour = p->time.tm_hour; - min = p->time.tm_min; - sec = p->time.tm_sec; - - // Datasheet says 1 is sunday - wday = p->time.tm_wday + 1; - - DPRINTFN("Real-time clock set to %s", asctime(&p->time)); -} - -void -TsunamiIO::RTC::writeAddr(const uint8_t data) -{ - if (data <= RTC_STAT_REGD) - addr = data; - else - panic("RTC addresses over 0xD are not implemented.\n"); -} - -void -TsunamiIO::RTC::writeData(const uint8_t data) -{ - if (addr < RTC_STAT_REGA) - clock_data[addr] = data; - else { - switch (addr) { - case RTC_STAT_REGA: - if (data != (RTCA_32768HZ | RTCA_1024HZ)) - panic("Unimplemented RTC register A value write!\n"); - stat_regA = data; - break; - case RTC_STAT_REGB: - if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR)) - panic("Write to RTC reg B bits that are not implemented!\n"); - - if (data & RTCB_PRDC_IE) { - if (!event.scheduled()) - event.scheduleIntr(); - } else { - if (event.scheduled()) - event.deschedule(); - } - stat_regB = data; - break; - case RTC_STAT_REGC: - case RTC_STAT_REGD: - panic("RTC status registers C and D are not implemented.\n"); - break; - } - } -} - -uint8_t -TsunamiIO::RTC::readData() -{ - if (addr < RTC_STAT_REGA) - return clock_data[addr]; - else { - switch (addr) { - case RTC_STAT_REGA: - // toggle UIP bit for linux - stat_regA ^= RTCA_UIP; - return stat_regA; - break; - case RTC_STAT_REGB: - return stat_regB; - break; - case RTC_STAT_REGC: - case RTC_STAT_REGD: - return 0x00; - break; - default: - panic("Shouldn't be here"); - } - } -} - -void -TsunamiIO::RTC::serialize(const string &base, ostream &os) -{ - paramOut(os, base + ".addr", addr); - arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data)); - paramOut(os, base + ".stat_regA", stat_regA); - paramOut(os, base + ".stat_regB", stat_regB); -} - -void -TsunamiIO::RTC::unserialize(const string &base, Checkpoint *cp, - const string §ion) -{ - paramIn(cp, section, base + ".addr", addr); - arrayParamIn(cp, section, base + ".clock_data", clock_data, - sizeof(clock_data)); - paramIn(cp, section, base + ".stat_regA", stat_regA); - paramIn(cp, section, base + ".stat_regB", stat_regB); - - // We're not unserializing the event here, but we need to - // rescehedule the event since curTick was moved forward by the - // checkpoint - event.reschedule(curTick + event.interval); -} - -TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i) - : Event(&mainEventQueue), tsunami(t), interval(i) -{ - DPRINTF(MC146818, "RTC Event Initilizing\n"); - schedule(curTick + interval); -} - -void -TsunamiIO::RTC::RTCEvent::scheduleIntr() -{ - schedule(curTick + interval); -} - -void -TsunamiIO::RTC::RTCEvent::process() -{ - DPRINTF(MC146818, "RTC Timer Interrupt\n"); - schedule(curTick + interval); - //Actually interrupt the processor here - tsunami->cchip->postRTC(); -} - -const char * -TsunamiIO::RTC::RTCEvent::description() const -{ - return "tsunami RTC interrupt"; -} - -TsunamiIO::PITimer::PITimer(const string &name) - : _name(name), counter0(name + ".counter0"), counter1(name + ".counter1"), - counter2(name + ".counter2") -{ - counter[0] = &counter0; - counter[1] = &counter0; - counter[2] = &counter0; -} - -void -TsunamiIO::PITimer::writeControl(const uint8_t data) -{ - int rw; - int sel; - - sel = GET_CTRL_SEL(data); - - if (sel == PIT_READ_BACK) - panic("PITimer Read-Back Command is not implemented.\n"); - - rw = GET_CTRL_RW(data); - - if (rw == PIT_RW_LATCH_COMMAND) - counter[sel]->latchCount(); - else { - counter[sel]->setRW(rw); - counter[sel]->setMode(GET_CTRL_MODE(data)); - counter[sel]->setBCD(GET_CTRL_BCD(data)); - } -} - -void -TsunamiIO::PITimer::serialize(const string &base, ostream &os) -{ - // serialize the counters - counter0.serialize(base + ".counter0", os); - counter1.serialize(base + ".counter1", os); - counter2.serialize(base + ".counter2", os); -} - -void -TsunamiIO::PITimer::unserialize(const string &base, Checkpoint *cp, - const string §ion) -{ - // unserialze the counters - counter0.unserialize(base + ".counter0", cp, section); - counter1.unserialize(base + ".counter1", cp, section); - counter2.unserialize(base + ".counter2", cp, section); -} - -TsunamiIO::PITimer::Counter::Counter(const string &name) - : _name(name), event(this), count(0), latched_count(0), period(0), - mode(0), output_high(false), latch_on(false), read_byte(LSB), - write_byte(LSB) -{ - -} - -void -TsunamiIO::PITimer::Counter::latchCount() -{ - // behave like a real latch - if(!latch_on) { - latch_on = true; - read_byte = LSB; - latched_count = count; - } -} - -uint8_t -TsunamiIO::PITimer::Counter::read() -{ - if (latch_on) { - switch (read_byte) { - case LSB: - read_byte = MSB; - return (uint8_t)latched_count; - break; - case MSB: - read_byte = LSB; - latch_on = false; - return latched_count >> 8; - break; - default: - panic("Shouldn't be here"); - } - } else { - switch (read_byte) { - case LSB: - read_byte = MSB; - return (uint8_t)count; - break; - case MSB: - read_byte = LSB; - return count >> 8; - break; - default: - panic("Shouldn't be here"); - } - } -} - -void -TsunamiIO::PITimer::Counter::write(const uint8_t data) -{ - switch (write_byte) { - case LSB: - count = (count & 0xFF00) | data; - - if (event.scheduled()) - event.deschedule(); - output_high = false; - write_byte = MSB; - break; - - case MSB: - count = (count & 0x00FF) | (data << 8); - period = count; - - if (period > 0) { - DPRINTF(Tsunami, "Timer set to curTick + %d\n", - count * event.interval); - event.schedule(curTick + count * event.interval); - } - write_byte = LSB; - break; - } -} - -void -TsunamiIO::PITimer::Counter::setRW(int rw_val) -{ - if (rw_val != PIT_RW_16BIT) - panic("Only LSB/MSB read/write is implemented.\n"); -} - -void -TsunamiIO::PITimer::Counter::setMode(int mode_val) -{ - if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN && - mode_val != PIT_MODE_SQWAVE) - panic("PIT mode %#x is not implemented: \n", mode_val); - - mode = mode_val; -} - -void -TsunamiIO::PITimer::Counter::setBCD(int bcd_val) -{ - if (bcd_val != PIT_BCD_FALSE) - panic("PITimer does not implement BCD counts.\n"); -} - -bool -TsunamiIO::PITimer::Counter::outputHigh() -{ - return output_high; -} - -void -TsunamiIO::PITimer::Counter::serialize(const string &base, ostream &os) -{ - paramOut(os, base + ".count", count); - paramOut(os, base + ".latched_count", latched_count); - paramOut(os, base + ".period", period); - paramOut(os, base + ".mode", mode); - paramOut(os, base + ".output_high", output_high); - paramOut(os, base + ".latch_on", latch_on); - paramOut(os, base + ".read_byte", read_byte); - paramOut(os, base + ".write_byte", write_byte); - - Tick event_tick = 0; - if (event.scheduled()) - event_tick = event.when(); - paramOut(os, base + ".event_tick", event_tick); -} - -void -TsunamiIO::PITimer::Counter::unserialize(const string &base, Checkpoint *cp, - const string §ion) -{ - paramIn(cp, section, base + ".count", count); - paramIn(cp, section, base + ".latched_count", latched_count); - paramIn(cp, section, base + ".period", period); - paramIn(cp, section, base + ".mode", mode); - paramIn(cp, section, base + ".output_high", output_high); - paramIn(cp, section, base + ".latch_on", latch_on); - paramIn(cp, section, base + ".read_byte", read_byte); - paramIn(cp, section, base + ".write_byte", write_byte); - - Tick event_tick; - paramIn(cp, section, base + ".event_tick", event_tick); - if (event_tick) - event.schedule(event_tick); -} - -TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter* c_ptr) - : Event(&mainEventQueue) -{ - interval = (Tick)(Clock::Float::s / 1193180.0); - counter = c_ptr; -} - -void -TsunamiIO::PITimer::Counter::CounterEvent::process() -{ - DPRINTF(Tsunami, "Timer Interrupt\n"); - switch (counter->mode) { - case PIT_MODE_INTTC: - counter->output_high = true; - case PIT_MODE_RATEGEN: - case PIT_MODE_SQWAVE: - break; - default: - panic("Unimplemented PITimer mode.\n"); - } -} - -const char * -TsunamiIO::PITimer::Counter::CounterEvent::description() const -{ - return "tsunami 8254 Interval timer"; } TsunamiIO::TsunamiIO(const Params *p) - : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"), - rtc(p->name + ".rtc", p->tsunami, p) + : BasicPioDevice(p), tsunami(p->tsunami), + pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) { pioSize = 0x100; @@ -486,19 +114,19 @@ TsunamiIO::read(PacketPtr pkt) pkt->set(0x00); break; case TSDEV_TMR0_DATA: - pkt->set(pitimer.counter0.read()); + pkt->set(pitimer.readCounter(0)); break; case TSDEV_TMR1_DATA: - pkt->set(pitimer.counter1.read()); + pkt->set(pitimer.readCounter(1)); break; case TSDEV_TMR2_DATA: - pkt->set(pitimer.counter2.read()); + pkt->set(pitimer.readCounter(2)); break; case TSDEV_RTC_DATA: - pkt->set(rtc.readData()); + pkt->set(rtc.readData(rtcAddr)); break; case TSDEV_CTRL_PORTB: - if (pitimer.counter2.outputHigh()) + if (pitimer.outputHigh(2)) pkt->set(PORTB_SPKR_HIGH); else pkt->set(0x00); @@ -561,22 +189,22 @@ TsunamiIO::write(PacketPtr pkt) mode2 = pkt->get<uint8_t>(); break; case TSDEV_TMR0_DATA: - pitimer.counter0.write(pkt->get<uint8_t>()); + pitimer.writeCounter(0, pkt->get<uint8_t>()); break; case TSDEV_TMR1_DATA: - pitimer.counter1.write(pkt->get<uint8_t>()); + pitimer.writeCounter(1, pkt->get<uint8_t>()); break; case TSDEV_TMR2_DATA: - pitimer.counter2.write(pkt->get<uint8_t>()); + pitimer.writeCounter(2, pkt->get<uint8_t>()); break; case TSDEV_TMR_CTRL: pitimer.writeControl(pkt->get<uint8_t>()); break; case TSDEV_RTC_ADDR: - rtc.writeAddr(pkt->get<uint8_t>()); + rtcAddr = pkt->get<uint8_t>(); break; case TSDEV_RTC_DATA: - rtc.writeData(pkt->get<uint8_t>()); + rtc.writeData(rtcAddr, pkt->get<uint8_t>()); break; case TSDEV_KBD: case TSDEV_DMA1_CMND: @@ -623,6 +251,7 @@ TsunamiIO::clearPIC(uint8_t bitvector) void TsunamiIO::serialize(ostream &os) { + SERIALIZE_SCALAR(rtcAddr); SERIALIZE_SCALAR(timerData); SERIALIZE_SCALAR(mask1); SERIALIZE_SCALAR(mask2); @@ -639,6 +268,7 @@ TsunamiIO::serialize(ostream &os) void TsunamiIO::unserialize(Checkpoint *cp, const string §ion) { + UNSERIALIZE_SCALAR(rtcAddr); UNSERIALIZE_SCALAR(timerData); UNSERIALIZE_SCALAR(mask1); UNSERIALIZE_SCALAR(mask2); diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh index 05c4ee910..b6d63322b 100644 --- a/src/dev/alpha/tsunami_io.hh +++ b/src/dev/alpha/tsunami_io.hh @@ -39,6 +39,8 @@ #include "base/range.hh" #include "dev/alpha/tsunami.hh" +#include "dev/intel_8254_timer.hh" +#include "dev/mc146818.hh" #include "dev/io_device.hh" #include "params/TsunamiIO.hh" #include "sim/eventq.hh" @@ -53,223 +55,19 @@ class TsunamiIO : public BasicPioDevice struct tm tm; protected: - /** Real-Time Clock (MC146818) */ - class RTC - { - private: - /** Event for RTC periodic interrupt */ - struct RTCEvent : public Event - { - /** A pointer back to tsunami to create interrupt the processor. */ - Tsunami* tsunami; - Tick interval; - - RTCEvent(Tsunami* t, Tick i); - - /** Schedule the RTC periodic interrupt */ - void scheduleIntr(); - - /** Event process to occur at interrupt*/ - virtual void process(); - - /** Event description */ - virtual const char *description() const; - }; - - private: - std::string _name; - const std::string &name() const { return _name; } - /** RTC periodic interrupt event */ - RTCEvent event; - - /** Current RTC register address/index */ - int addr; - - /** Data for real-time clock function */ - union { - uint8_t clock_data[10]; - - struct { - uint8_t sec; - uint8_t sec_alrm; - uint8_t min; - uint8_t min_alrm; - uint8_t hour; - uint8_t hour_alrm; - uint8_t wday; - uint8_t mday; - uint8_t mon; - uint8_t year; - }; - }; - - /** RTC status register A */ - uint8_t stat_regA; - - /** RTC status register B */ - uint8_t stat_regB; - - public: - RTC(const std::string &name, Tsunami* tsunami, - const TsunamiIOParams *params); - - /** RTC address port: write address of RTC RAM data to access */ - void writeAddr(const uint8_t data); - - /** RTC write data */ - void writeData(const uint8_t data); - - /** RTC read data */ - uint8_t readData(); - - /** - * Serialize this object to the given output stream. - * @param base The base name of the counter object. - * @param os The stream to serialize to. - */ - void serialize(const std::string &base, std::ostream &os); - - /** - * Reconstruct the state of this object from a checkpoint. - * @param base The base name of the counter object. - * @param cp The checkpoint use. - * @param section The section name of this object - */ - void unserialize(const std::string &base, Checkpoint *cp, - const std::string §ion); - }; - - /** Programmable Interval Timer (Intel 8254) */ - class PITimer + class RTC : public MC146818 { - /** Counter element for PIT */ - class Counter - { - /** Event for counter interrupt */ - class CounterEvent : public Event - { - private: - /** Pointer back to Counter */ - Counter* counter; - Tick interval; - - public: - CounterEvent(Counter*); - - /** Event process */ - virtual void process(); - - /** Event description */ - virtual const char *description() const; - - friend class Counter; - }; - - private: - std::string _name; - const std::string &name() const { return _name; } - - CounterEvent event; - - /** Current count value */ - uint16_t count; - - /** Latched count */ - uint16_t latched_count; - - /** Interrupt period */ - uint16_t period; - - /** Current mode of operation */ - uint8_t mode; - - /** Output goes high when the counter reaches zero */ - bool output_high; - - /** State of the count latch */ - bool latch_on; - - /** Set of values for read_byte and write_byte */ - enum {LSB, MSB}; - - /** Determine which byte of a 16-bit count value to read/write */ - uint8_t read_byte, write_byte; - - public: - Counter(const std::string &name); - - /** Latch the current count (if one is not already latched) */ - void latchCount(); - - /** Set the read/write mode */ - void setRW(int rw_val); - - /** Set operational mode */ - void setMode(int mode_val); - - /** Set count encoding */ - void setBCD(int bcd_val); - - /** Read a count byte */ - uint8_t read(); - - /** Write a count byte */ - void write(const uint8_t data); - - /** Is the output high? */ - bool outputHigh(); - - /** - * Serialize this object to the given output stream. - * @param base The base name of the counter object. - * @param os The stream to serialize to. - */ - void serialize(const std::string &base, std::ostream &os); - - /** - * Reconstruct the state of this object from a checkpoint. - * @param base The base name of the counter object. - * @param cp The checkpoint use. - * @param section The section name of this object - */ - void unserialize(const std::string &base, Checkpoint *cp, - const std::string §ion); - }; - - private: - std::string _name; - const std::string &name() const { return _name; } - - /** PIT has three seperate counters */ - Counter *counter[3]; - public: - /** Public way to access individual counters (avoid array accesses) */ - Counter counter0; - Counter counter1; - Counter counter2; - - PITimer(const std::string &name); - - /** Write control word */ - void writeControl(const uint8_t data); + Tsunami *tsunami; + RTC(const std::string &n, const TsunamiIOParams *p); - /** - * Serialize this object to the given output stream. - * @param base The base name of the counter object. - * @param os The stream to serialize to. - */ - void serialize(const std::string &base, std::ostream &os); - - /** - * Reconstruct the state of this object from a checkpoint. - * @param base The base name of the counter object. - * @param cp The checkpoint use. - * @param section The section name of this object - */ - void unserialize(const std::string &base, Checkpoint *cp, - const std::string §ion); + protected: + void handleEvent() + { + //Actually interrupt the processor here + tsunami->cchip->postRTC(); + } }; /** Mask of the PIC1 */ @@ -294,10 +92,12 @@ class TsunamiIO : public BasicPioDevice Tsunami *tsunami; /** Intel 8253 Periodic Interval Timer */ - PITimer pitimer; + Intel8254Timer pitimer; RTC rtc; + uint8_t rtcAddr; + /** The interval is set via two writes to the PIT. * This variable contains a flag as to how many writes have happened, and * the time so far. diff --git a/src/dev/alpha/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc index 83bcf8e65..4df7d1150 100644 --- a/src/dev/alpha/tsunami_pchip.cc +++ b/src/dev/alpha/tsunami_pchip.cc @@ -300,6 +300,7 @@ TsunamiPChip::translatePciToDma(Addr busAddr) // if no match was found, then return the original address return busAddr; } + Addr TsunamiPChip::calcConfigAddr(int bus, int dev, int func) { @@ -310,7 +311,17 @@ TsunamiPChip::calcConfigAddr(int bus, int dev, int func) return TsunamiPciBus0Config | (func << 8) | (dev << 11); } +Addr +TsunamiPChip::calcIOAddr(Addr addr) +{ + return TSUNAMI_PCI0_IO + addr; +} +Addr +TsunamiPChip::calcMemAddr(Addr addr) +{ + return TSUNAMI_PCI0_MEMORY + addr; +} void TsunamiPChip::serialize(std::ostream &os) diff --git a/src/dev/alpha/tsunami_pchip.hh b/src/dev/alpha/tsunami_pchip.hh index 53050565f..d31a28dbe 100644 --- a/src/dev/alpha/tsunami_pchip.hh +++ b/src/dev/alpha/tsunami_pchip.hh @@ -84,6 +84,8 @@ class TsunamiPChip : public BasicPioDevice Addr translatePciToDma(Addr busAddr); Addr calcConfigAddr(int bus, int dev, int func); + Addr calcIOAddr(Addr addr); + Addr calcMemAddr(Addr addr); virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); |