diff options
Diffstat (limited to 'src/dev/pci/device.cc')
-rw-r--r-- | src/dev/pci/device.cc | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/src/dev/pci/device.cc b/src/dev/pci/device.cc index 4d9d29b1d..1097573f8 100644 --- a/src/dev/pci/device.cc +++ b/src/dev/pci/device.cc @@ -228,13 +228,13 @@ PciDevice::readConfig(PacketPtr pkt) "not implemented for %s!\n", this->name()); switch (pkt->getSize()) { case sizeof(uint8_t): - pkt->set<uint8_t>(0); + pkt->setLE<uint8_t>(0); break; case sizeof(uint16_t): - pkt->set<uint16_t>(0); + pkt->setLE<uint16_t>(0); break; case sizeof(uint32_t): - pkt->set<uint32_t>(0); + pkt->setLE<uint32_t>(0); break; default: panic("invalid access size(?) for PCI configspace!\n"); @@ -245,25 +245,25 @@ PciDevice::readConfig(PacketPtr pkt) switch (pkt->getSize()) { case sizeof(uint8_t): - pkt->set<uint8_t>(config.data[offset]); + pkt->setLE<uint8_t>(config.data[offset]); DPRINTF(PciDevice, "readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n", _busAddr.dev, _busAddr.func, offset, - (uint32_t)pkt->get<uint8_t>()); + (uint32_t)pkt->getLE<uint8_t>()); break; case sizeof(uint16_t): - pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]); + pkt->setLE<uint16_t>(*(uint16_t*)&config.data[offset]); DPRINTF(PciDevice, "readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n", _busAddr.dev, _busAddr.func, offset, - (uint32_t)pkt->get<uint16_t>()); + (uint32_t)pkt->getLE<uint16_t>()); break; case sizeof(uint32_t): - pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]); + pkt->setLE<uint32_t>(*(uint32_t*)&config.data[offset]); DPRINTF(PciDevice, "readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n", _busAddr.dev, _busAddr.func, offset, - (uint32_t)pkt->get<uint32_t>()); + (uint32_t)pkt->getLE<uint32_t>()); break; default: panic("invalid access size(?) for PCI configspace!\n"); @@ -310,13 +310,13 @@ PciDevice::writeConfig(PacketPtr pkt) case sizeof(uint8_t): switch (offset) { case PCI0_INTERRUPT_LINE: - config.interruptLine = pkt->get<uint8_t>(); + config.interruptLine = pkt->getLE<uint8_t>(); break; case PCI_CACHE_LINE_SIZE: - config.cacheLineSize = pkt->get<uint8_t>(); + config.cacheLineSize = pkt->getLE<uint8_t>(); break; case PCI_LATENCY_TIMER: - config.latencyTimer = pkt->get<uint8_t>(); + config.latencyTimer = pkt->getLE<uint8_t>(); break; /* Do nothing for these read-only registers */ case PCI0_INTERRUPT_PIN: @@ -331,18 +331,18 @@ PciDevice::writeConfig(PacketPtr pkt) DPRINTF(PciDevice, "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n", _busAddr.dev, _busAddr.func, offset, - (uint32_t)pkt->get<uint8_t>()); + (uint32_t)pkt->getLE<uint8_t>()); break; case sizeof(uint16_t): switch (offset) { case PCI_COMMAND: - config.command = pkt->get<uint8_t>(); + config.command = pkt->getLE<uint8_t>(); break; case PCI_STATUS: - config.status = pkt->get<uint8_t>(); + config.status = pkt->getLE<uint8_t>(); break; case PCI_CACHE_LINE_SIZE: - config.cacheLineSize = pkt->get<uint8_t>(); + config.cacheLineSize = pkt->getLE<uint8_t>(); break; default: panic("writing to a read only register"); @@ -350,7 +350,7 @@ PciDevice::writeConfig(PacketPtr pkt) DPRINTF(PciDevice, "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n", _busAddr.dev, _busAddr.func, offset, - (uint32_t)pkt->get<uint16_t>()); + (uint32_t)pkt->getLE<uint16_t>()); break; case sizeof(uint32_t): switch (offset) { @@ -366,7 +366,7 @@ PciDevice::writeConfig(PacketPtr pkt) if (!legacyIO[barnum]) { // convert BAR values to host endianness uint32_t he_old_bar = letoh(config.baseAddr[barnum]); - uint32_t he_new_bar = letoh(pkt->get<uint32_t>()); + uint32_t he_new_bar = letoh(pkt->getLE<uint32_t>()); uint32_t bar_mask = BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK; @@ -393,17 +393,17 @@ PciDevice::writeConfig(PacketPtr pkt) break; case PCI0_ROM_BASE_ADDR: - if (letoh(pkt->get<uint32_t>()) == 0xfffffffe) + if (letoh(pkt->getLE<uint32_t>()) == 0xfffffffe) config.expansionROM = htole((uint32_t)0xffffffff); else - config.expansionROM = pkt->get<uint32_t>(); + config.expansionROM = pkt->getLE<uint32_t>(); break; case PCI_COMMAND: // This could also clear some of the error bits in the Status // register. However they should never get set, so lets ignore // it for now - config.command = pkt->get<uint32_t>(); + config.command = pkt->getLE<uint32_t>(); break; default: @@ -412,7 +412,7 @@ PciDevice::writeConfig(PacketPtr pkt) DPRINTF(PciDevice, "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n", _busAddr.dev, _busAddr.func, offset, - (uint32_t)pkt->get<uint32_t>()); + (uint32_t)pkt->getLE<uint32_t>()); break; default: panic("invalid access size(?) for PCI configspace!\n"); |