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Diffstat (limited to 'src/dev/pcidev.cc')
-rw-r--r--src/dev/pcidev.cc134
1 files changed, 56 insertions, 78 deletions
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index e81e0d1ee..8ea22cb24 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -39,6 +39,7 @@
#include <vector>
#include "base/inifile.hh"
+#include "base/intmath.hh" // for isPowerOf2(
#include "base/misc.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
@@ -56,8 +57,8 @@ using namespace std;
PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
int funcid, Platform *p)
- : PioPort(dev,p->system,"-pciconf"), device(dev), platform(p),
- busId(busid), deviceId(devid), functionId(funcid)
+ : SimpleTimingPort(dev->name() + "-pciconf"), device(dev), platform(p),
+ busId(busid), deviceId(devid), functionId(funcid)
{
configAddr = platform->calcConfigAddr(busId, deviceId, functionId);
}
@@ -67,45 +68,20 @@ Tick
PciDev::PciConfigPort::recvAtomic(Packet *pkt)
{
assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
- PCI_CONFIG_SIZE);
- return device->recvConfig(pkt);
+ assert(pkt->getAddr() >= configAddr &&
+ pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
+ return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
}
void
-PciDev::PciConfigPort::recvFunctional(Packet *pkt)
-{
- assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
- PCI_CONFIG_SIZE);
- device->recvConfig(pkt);
-}
-
-void
-PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
+PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop)
{
snoop.clear();
resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
}
-bool
-PciDev::PciConfigPort::recvTiming(Packet *pkt)
-{
- if (pkt->result == Packet::Nacked) {
- resendNacked(pkt);
- } else {
- assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
- PCI_CONFIG_SIZE);
- Tick latency = device->recvConfig(pkt);
- // turn packet around to go back to requester
- pkt->makeTimingResponse();
- sendTiming(pkt, latency);
- }
- return true;
-}
-
PciDev::PciDev(Params *p)
: DmaDevice(p), plat(p->platform), configData(p->configData),
pioDelay(p->pio_delay), configDelay(p->config_delay),
@@ -115,10 +91,11 @@ PciDev::PciDev(Params *p)
if (configData) {
memcpy(config.data, configData->config.data, sizeof(config.data));
memcpy(BARSize, configData->BARSize, sizeof(BARSize));
- memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
} else
panic("NULL pointer to configuration data");
+ memset(BARAddrs, 0, sizeof(BARAddrs));
+
plat->registerPciDevice(0, p->deviceNum, p->functionNum,
letoh(configData->config.interruptLine));
}
@@ -157,21 +134,21 @@ PciDev::readConfig(Packet *pkt)
case sizeof(uint8_t):
pkt->set<uint8_t>(config.data[offset]);
DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
+ "readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
(uint32_t)pkt->get<uint8_t>());
break;
case sizeof(uint16_t):
pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
+ "readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
(uint32_t)pkt->get<uint16_t>());
break;
case sizeof(uint32_t):
pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
+ "readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
(uint32_t)pkt->get<uint32_t>());
break;
@@ -221,7 +198,7 @@ PciDev::writeConfig(Packet *pkt)
panic("writing to a read only register");
}
DPRINTF(PCIDEV,
- "write device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
+ "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
(uint32_t)pkt->get<uint8_t>());
break;
@@ -238,7 +215,7 @@ PciDev::writeConfig(Packet *pkt)
panic("writing to a read only register");
}
DPRINTF(PCIDEV,
- "write device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
+ "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
(uint32_t)pkt->get<uint16_t>());
break;
@@ -250,40 +227,33 @@ PciDev::writeConfig(Packet *pkt)
case PCI0_BASE_ADDR3:
case PCI0_BASE_ADDR4:
case PCI0_BASE_ADDR5:
-
- uint32_t barnum, bar_mask;
- Addr base_addr, base_size, space_base;
-
- barnum = BAR_NUMBER(offset);
-
- if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
- bar_mask = BAR_IO_MASK;
- space_base = TSUNAMI_PCI0_IO;
- } else {
- bar_mask = BAR_MEM_MASK;
- space_base = TSUNAMI_PCI0_MEMORY;
- }
-
- // Writing 0xffffffff to a BAR tells the card to set the
- // value of the bar to size of memory it needs
- if (letoh(pkt->get<uint32_t>()) == 0xffffffff) {
- // This is I/O Space, bottom two bits are read only
-
- config.baseAddr[barnum] = letoh(
- (~(BARSize[barnum] - 1) & ~bar_mask) |
- (letoh(config.baseAddr[barnum]) & bar_mask));
- } else {
- config.baseAddr[barnum] = letoh(
- (letoh(pkt->get<uint32_t>()) & ~bar_mask) |
- (letoh(config.baseAddr[barnum]) & bar_mask));
-
- if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
- base_addr = (letoh(pkt->get<uint32_t>()) & ~bar_mask) + space_base;
- base_size = BARSize[barnum];
- BARAddrs[barnum] = base_addr;
-
- pioPort->sendStatusChange(Port::RangeChange);
+ {
+ int barnum = BAR_NUMBER(offset);
+
+ // convert BAR values to host endianness
+ uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
+ uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
+
+ uint32_t bar_mask =
+ BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
+
+ // Writing 0xffffffff to a BAR tells the card to set the
+ // value of the bar to a bitmask indicating the size of
+ // memory it needs
+ if (he_new_bar == 0xffffffff) {
+ he_new_bar = ~(BARSize[barnum] - 1);
+ } else {
+ // does it mean something special to write 0 to a BAR?
+ he_new_bar &= ~bar_mask;
+ if (he_new_bar) {
+ Addr space_base = BAR_IO_SPACE(he_old_bar) ?
+ TSUNAMI_PCI0_IO : TSUNAMI_PCI0_MEMORY;
+ BARAddrs[barnum] = he_new_bar + space_base;
+ pioPort->sendStatusChange(Port::RangeChange);
+ }
}
+ config.baseAddr[barnum] = htole((he_new_bar & ~bar_mask) |
+ (he_old_bar & bar_mask));
}
break;
@@ -305,7 +275,7 @@ PciDev::writeConfig(Packet *pkt)
DPRINTF(PCIDEV, "Writing to a read only register");
}
DPRINTF(PCIDEV,
- "write device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
+ "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
params()->deviceNum, params()->functionNum, offset,
(uint32_t)pkt->get<uint32_t>());
break;
@@ -427,12 +397,12 @@ CREATE_SIM_OBJECT(PciConfigData)
data->config.headerType = htole(HeaderType);
data->config.bist = htole(BIST);
- data->config.baseAddr0 = htole(BAR0);
- data->config.baseAddr1 = htole(BAR1);
- data->config.baseAddr2 = htole(BAR2);
- data->config.baseAddr3 = htole(BAR3);
- data->config.baseAddr4 = htole(BAR4);
- data->config.baseAddr5 = htole(BAR5);
+ data->config.baseAddr[0] = htole(BAR0);
+ data->config.baseAddr[1] = htole(BAR1);
+ data->config.baseAddr[2] = htole(BAR2);
+ data->config.baseAddr[3] = htole(BAR3);
+ data->config.baseAddr[4] = htole(BAR4);
+ data->config.baseAddr[5] = htole(BAR5);
data->config.cardbusCIS = htole(CardbusCIS);
data->config.subsystemVendorID = htole(SubsystemVendorID);
data->config.subsystemID = htole(SubsystemVendorID);
@@ -449,6 +419,14 @@ CREATE_SIM_OBJECT(PciConfigData)
data->BARSize[4] = BAR4Size;
data->BARSize[5] = BAR5Size;
+ for (int i = 0; i < 6; ++i) {
+ uint32_t barsize = data->BARSize[i];
+ if (barsize != 0 && !isPowerOf2(barsize)) {
+ fatal("%s: BAR %d size %d is not a power of 2\n",
+ getInstanceName(), i, data->BARSize[i]);
+ }
+ }
+
return data;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-01 10:51:51 +0000