summaryrefslogtreecommitdiff
path: root/src/dev/x86/SouthBridge.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/dev/x86/SouthBridge.py')
-rw-r--r--src/dev/x86/SouthBridge.py1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 87f4c3798..7ac208d5e 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -45,7 +45,6 @@ def x86IOAddress(port):
class SouthBridge(SimObject):
type = 'SouthBridge'
- pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
platform = Param.Platform(Parent.any, "Platform this device is part of")
_pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')