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-rw-r--r--src/dev/x86/SouthBridge.py20
1 files changed, 8 insertions, 12 deletions
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 7029eb358..80b432d62 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -36,7 +36,6 @@ from m5.objects.I8254 import I8254
from m5.objects.I8259 import I8259
from m5.objects.Ide import IdeController
from m5.objects.PcSpeaker import PcSpeaker
-from m5.objects.X86IntPin import X86IntLine
from m5.SimObject import SimObject
def x86IOAddress(port):
@@ -87,17 +86,14 @@ class SouthBridge(SimObject):
ide.LegacyIOBase = x86IOAddress(0)
def attachIO(self, bus, dma_ports):
- # Route interupt signals
- self.int_lines = \
- [X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
- X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)),
- X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)),
- X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)),
- X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
- X86IntLine(source=self.keyboard.keyboard_int_pin,
- sink=self.io_apic.pin(1)),
- X86IntLine(source=self.keyboard.mouse_int_pin,
- sink=self.io_apic.pin(12))]
+ # Route interrupt signals
+ self.pic1.output = self.io_apic.inputs[0]
+ self.pic2.output = self.pic1.inputs[2]
+ self.cmos.int_pin = self.pic2.inputs[0]
+ self.pit.int_pin = self.pic1.inputs[0]
+ self.pit.int_pin = self.io_apic.inputs[2]
+ self.keyboard.keyboard_int_pin = self.io_apic.inputs[1]
+ self.keyboard.mouse_int_pin = self.io_apic.inputs[12]
# Tell the devices about each other
self.pic1.slave = self.pic2
self.speaker.i8254 = self.pit