diff options
Diffstat (limited to 'src/dev/x86/south_bridge/SouthBridge.py')
| -rw-r--r-- | src/dev/x86/south_bridge/SouthBridge.py | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/src/dev/x86/south_bridge/SouthBridge.py b/src/dev/x86/south_bridge/SouthBridge.py index bec3c4223..2f4b8438a 100644 --- a/src/dev/x86/south_bridge/SouthBridge.py +++ b/src/dev/x86/south_bridge/SouthBridge.py @@ -28,8 +28,42 @@ from m5.params import * from m5.proxy import * -from Device import PioDevice +from Cmos import Cmos +from I8254 import I8254 +from I8259 import I8259 +from PcSpeaker import PcSpeaker +from m5.SimObject import SimObject -class SouthBridge(PioDevice): +def x86IOAddress(port): + IO_address_space_base = 0x8000000000000000 + return IO_address_space_base + port; + +class SouthBridge(SimObject): type = 'SouthBridge' pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") + platform = Param.Platform(Parent.any, "Platform this device is part of") + + _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') + _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave') + _cmos = Cmos(pio_addr=x86IOAddress(0x70)) + _pit = I8254(pio_addr=x86IOAddress(0x40)) + _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) + + pic1 = Param.I8259(_pic1, "Master PIC") + pic2 = Param.I8259(_pic2, "Slave PIC") + cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") + pit = Param.I8254(_pit, "Programmable interval timer") + speaker = Param.PcSpeaker(_speaker, "PC speaker") + + def attachIO(self, bus): + # Make internal connections + self.pic2.output = self.pic1.pin(2) + self.cmos.int_pin = self.pic2.pin(0) + self.pit.int_pin = self.pic1.pin(0) + self.speaker.i8254 = self.pit + # Connect to the bus + self.cmos.pio = bus.port + self.pic1.pio = bus.port + self.pic2.pio = bus.port + self.pit.pio = bus.port + self.speaker.pio = bus.port |