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-rw-r--r--src/dev/x86/i82094aa.cc4
-rw-r--r--src/dev/x86/i82094aa.hh6
-rw-r--r--src/dev/x86/intdev.cc8
-rw-r--r--src/dev/x86/intdev.hh37
4 files changed, 39 insertions, 16 deletions
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index 3d7454dfd..54824c778 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -222,8 +222,8 @@ X86ISA::I82094AA::signalInterrupt(int line)
apics.push_back(selected);
}
}
- intPort.sendMessage(apics, message,
- sys->getMemoryMode() == Enums::timing);
+ intMasterPort.sendMessage(apics, message,
+ sys->getMemoryMode() == Enums::timing);
}
}
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index f0837cc27..d3eedea7b 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -121,11 +121,11 @@ class I82094AA : public PioDevice, public IntDev
void writeReg(uint8_t offset, uint32_t value);
uint32_t readReg(uint8_t offset);
- Port *getPort(const std::string &if_name, int idx = -1)
+ MasterPort &getMasterPort(const std::string &if_name, int idx = -1)
{
if (if_name == "int_master")
- return &intPort;
- return PioDevice::getPort(if_name, idx);
+ return intMasterPort;
+ return PioDevice::getMasterPort(if_name, idx);
}
void signalInterrupt(int line);
diff --git a/src/dev/x86/intdev.cc b/src/dev/x86/intdev.cc
index 0d038b93d..8580ae943 100644
--- a/src/dev/x86/intdev.cc
+++ b/src/dev/x86/intdev.cc
@@ -43,8 +43,9 @@
#include "dev/x86/intdev.hh"
void
-X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message,
- bool timing)
+X86ISA::IntDev::IntMasterPort::sendMessage(ApicList apics,
+ TriggerIntMessage message,
+ bool timing)
{
ApicList::iterator apicIt;
for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
@@ -67,10 +68,9 @@ X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message,
void
X86ISA::IntDev::init()
{
- if (!intPort.isConnected()) {
+ if (!intMasterPort.isConnected()) {
panic("Int port not connected to anything!");
}
- intPort.sendRangeChange();
}
X86ISA::IntSourcePin *
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 5549df637..bbdd98b24 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2008 The Regents of The University of Michigan
* All rights reserved.
*
@@ -51,15 +63,14 @@ typedef std::list<int> ApicList;
class IntDev
{
protected:
- class IntPort : public MessagePort
+ class IntSlavePort : public MessageSlavePort
{
IntDev * device;
Tick latency;
- Addr intAddr;
public:
- IntPort(const std::string &_name, MemObject * _parent,
- IntDev *dev, Tick _latency) :
- MessagePort(_name, _parent), device(dev), latency(_latency)
+ IntSlavePort(const std::string& _name, MemObject* _parent,
+ IntDev* dev, Tick _latency) :
+ MessageSlavePort(_name, _parent), device(dev), latency(_latency)
{
}
@@ -72,6 +83,18 @@ class IntDev
{
return device->recvMessage(pkt);
}
+ };
+
+ class IntMasterPort : public MessageMasterPort
+ {
+ IntDev* device;
+ Tick latency;
+ public:
+ IntMasterPort(const std::string& _name, MemObject* _parent,
+ IntDev* dev, Tick _latency) :
+ MessageMasterPort(_name, _parent), device(dev), latency(_latency)
+ {
+ }
Tick recvResponse(PacketPtr pkt)
{
@@ -84,11 +107,11 @@ class IntDev
TriggerIntMessage message, bool timing);
};
- IntPort intPort;
+ IntMasterPort intMasterPort;
public:
IntDev(MemObject * parent, Tick latency = 0) :
- intPort(parent->name() + ".int_master", parent, this, latency)
+ intMasterPort(parent->name() + ".int_master", parent, this, latency)
{
}