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-rw-r--r--src/dev/x86/PC.py15
-rw-r--r--src/dev/x86/pc.cc2
2 files changed, 9 insertions, 8 deletions
diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
index 4ba9e7a8a..5165308ed 100644
--- a/src/dev/x86/PC.py
+++ b/src/dev/x86/PC.py
@@ -28,12 +28,13 @@
from m5.params import *
from m5.proxy import *
-from Uart import Uart8250
+
from Device import IsaFake
-from SouthBridge import SouthBridge
-from Platform import Platform
from Pci import PciConfigAll
-from SimConsole import SimConsole
+from Platform import Platform
+from SouthBridge import SouthBridge
+from Terminal import Terminal
+from Uart import Uart8250
def x86IOAddress(port):
IO_address_space_base = 0x8000000000000000
@@ -54,11 +55,11 @@ class PC(Platform):
# but the linux kernel fiddles with them anway.
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
- # Serial port and console
- console = SimConsole()
+ # Serial port and terminal
+ terminal = Terminal()
com_1 = Uart8250()
com_1.pio_addr = x86IOAddress(0x3f8)
- com_1.sim_console = console
+ com_1.terminal = terminal
def attachIO(self, bus):
self.south_bridge.pio = bus.port
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index 0881672d2..d04529ab9 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -39,7 +39,7 @@
#include "arch/x86/x86_traits.hh"
#include "dev/intel_8254_timer.hh"
#include "cpu/intr_control.hh"
-#include "dev/simconsole.hh"
+#include "dev/terminal.hh"
#include "dev/x86/pc.hh"
#include "sim/system.hh"