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-rw-r--r--src/dev/x86/Opteron.py18
-rw-r--r--src/dev/x86/PC.py65
-rw-r--r--src/dev/x86/SConscript7
-rw-r--r--src/dev/x86/pc.cc (renamed from src/dev/x86/opteron.cc)26
-rw-r--r--src/dev/x86/pc.hh (renamed from src/dev/x86/opteron.hh)16
-rw-r--r--src/dev/x86/south_bridge/SConscript42
-rw-r--r--src/dev/x86/south_bridge/SouthBridge.py35
-rw-r--r--src/dev/x86/south_bridge/cmos.cc93
-rw-r--r--src/dev/x86/south_bridge/cmos.hh100
-rw-r--r--src/dev/x86/south_bridge/i8254.cc86
-rw-r--r--src/dev/x86/south_bridge/i8254.hh63
-rw-r--r--src/dev/x86/south_bridge/i8259.cc45
-rw-r--r--src/dev/x86/south_bridge/i8259.hh60
-rw-r--r--src/dev/x86/south_bridge/south_bridge.cc86
-rw-r--r--src/dev/x86/south_bridge/south_bridge.hh84
-rw-r--r--src/dev/x86/south_bridge/speaker.cc64
-rw-r--r--src/dev/x86/south_bridge/speaker.hh60
-rw-r--r--src/dev/x86/south_bridge/sub_device.hh79
18 files changed, 986 insertions, 43 deletions
diff --git a/src/dev/x86/Opteron.py b/src/dev/x86/Opteron.py
deleted file mode 100644
index cb015e2e7..000000000
--- a/src/dev/x86/Opteron.py
+++ /dev/null
@@ -1,18 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Uart import Uart8250
-from Platform import Platform
-from Pci import PciConfigAll
-from SimConsole import SimConsole
-
-class Opteron(Platform):
- type = 'Opteron'
- system = Param.System(Parent.any, "system")
-
- pciconfig = PciConfigAll()
-
- def attachIO(self, bus):
- self.pciconfig.pio = bus.default
- bus.responder_set = True
- bus.responder = self.pciconfig
diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
new file mode 100644
index 000000000..86ae4c3ba
--- /dev/null
+++ b/src/dev/x86/PC.py
@@ -0,0 +1,65 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Uart import Uart8250
+from Device import IsaFake
+from SouthBridge import SouthBridge
+from Platform import Platform
+from Pci import PciConfigAll
+from SimConsole import SimConsole
+
+def x86IOAddress(port):
+ IO_address_space_base = 0x8000000000000000
+ return IO_address_space_base + port;
+
+class PC(Platform):
+ type = 'PC'
+ system = Param.System(Parent.any, "system")
+
+ pciconfig = PciConfigAll()
+
+ south_bridge = SouthBridge()
+
+ # "Non-existant" port used for timing purposes by the linux kernel
+ i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+
+ # Serial port and console
+ console = SimConsole()
+ com_1 = Uart8250()
+ com_1.pio_addr = x86IOAddress(0x3f8)
+ com_1.sim_console = console
+
+ def attachIO(self, bus):
+ self.south_bridge.pio = bus.port
+ self.i_dont_exist.pio = bus.port
+ self.com_1.pio = bus.port
+ self.pciconfig.pio = bus.default
+ bus.responder_set = True
+ bus.responder = self.pciconfig
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index c500531b1..463344001 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -26,12 +26,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-# Authors: Steve Reinhardt
-# Gabe Black
+# Authors: Gabe Black
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
- SimObject('Opteron.py')
+ SimObject('PC.py')
- Source('opteron.cc')
+ Source('pc.cc')
diff --git a/src/dev/x86/opteron.cc b/src/dev/x86/pc.cc
index ba46f2dfa..148ba92f7 100644
--- a/src/dev/x86/opteron.cc
+++ b/src/dev/x86/pc.cc
@@ -29,7 +29,7 @@
*/
/** @file
- * Implementation of Opteron platform.
+ * Implementation of PC platform.
*/
#include <deque>
@@ -39,13 +39,13 @@
#include "arch/x86/x86_traits.hh"
#include "cpu/intr_control.hh"
#include "dev/simconsole.hh"
-#include "dev/x86/opteron.hh"
+#include "dev/x86/pc.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
-Opteron::Opteron(const Params *p)
+PC::PC(const Params *p)
: Platform(p), system(p->system)
{
// set the back pointer from the system to myself
@@ -53,40 +53,40 @@ Opteron::Opteron(const Params *p)
}
Tick
-Opteron::intrFrequency()
+PC::intrFrequency()
{
panic("Need implementation\n");
M5_DUMMY_RETURN
}
void
-Opteron::postConsoleInt()
+PC::postConsoleInt()
{
warn_once("Don't know what interrupt to post for console.\n");
//panic("Need implementation\n");
}
void
-Opteron::clearConsoleInt()
+PC::clearConsoleInt()
{
warn_once("Don't know what interrupt to clear for console.\n");
//panic("Need implementation\n");
}
void
-Opteron::postPciInt(int line)
+PC::postPciInt(int line)
{
panic("Need implementation\n");
}
void
-Opteron::clearPciInt(int line)
+PC::clearPciInt(int line)
{
panic("Need implementation\n");
}
Addr
-Opteron::pciToDma(Addr pciAddr) const
+PC::pciToDma(Addr pciAddr) const
{
panic("Need implementation\n");
M5_DUMMY_RETURN
@@ -94,7 +94,7 @@ Opteron::pciToDma(Addr pciAddr) const
Addr
-Opteron::calcConfigAddr(int bus, int dev, int func)
+PC::calcConfigAddr(int bus, int dev, int func)
{
assert(func < 8);
assert(dev < 32);
@@ -102,8 +102,8 @@ Opteron::calcConfigAddr(int bus, int dev, int func)
return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
}
-Opteron *
-OpteronParams::create()
+PC *
+PCParams::create()
{
- return new Opteron(this);
+ return new PC(this);
}
diff --git a/src/dev/x86/opteron.hh b/src/dev/x86/pc.hh
index 3026bce73..6e3a7f45e 100644
--- a/src/dev/x86/opteron.hh
+++ b/src/dev/x86/pc.hh
@@ -30,29 +30,29 @@
/**
* @file
- * Declaration of top level class for the Opteron platform chips. This class
+ * Declaration of top level class for PC platform components. This class
* just retains pointers to all its children so the children can communicate.
*/
-#ifndef __DEV_Opteron_HH__
-#define __DEV_Opteron_HH__
+#ifndef __DEV_PC_HH__
+#define __DEV_PC_HH__
#include "dev/platform.hh"
-#include "params/Opteron.hh"
+#include "params/PC.hh"
class IdeController;
class System;
-class Opteron : public Platform
+class PC : public Platform
{
public:
/** Pointer to the system */
System *system;
public:
- typedef OpteronParams Params;
+ typedef PCParams Params;
- Opteron(const Params *p);
+ PC(const Params *p);
/**
* Return the interrupting frequency to AlphaAccess
@@ -89,4 +89,4 @@ class Opteron : public Platform
virtual Addr calcConfigAddr(int bus, int dev, int func);
};
-#endif // __DEV_OPTERON_HH__
+#endif // __DEV_PC_HH__
diff --git a/src/dev/x86/south_bridge/SConscript b/src/dev/x86/south_bridge/SConscript
new file mode 100644
index 000000000..a7cb77b9b
--- /dev/null
+++ b/src/dev/x86/south_bridge/SConscript
@@ -0,0 +1,42 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+Import('*')
+
+if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
+ # Main device
+ SimObject('SouthBridge.py')
+ Source('south_bridge.cc')
+
+ # Sub devices
+ Source('cmos.cc')
+ Source('i8254.cc')
+ Source('i8259.cc')
+ Source('speaker.cc')
diff --git a/src/dev/x86/south_bridge/SouthBridge.py b/src/dev/x86/south_bridge/SouthBridge.py
new file mode 100644
index 000000000..bec3c4223
--- /dev/null
+++ b/src/dev/x86/south_bridge/SouthBridge.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import PioDevice
+
+class SouthBridge(PioDevice):
+ type = 'SouthBridge'
+ pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
diff --git a/src/dev/x86/south_bridge/cmos.cc b/src/dev/x86/south_bridge/cmos.cc
new file mode 100644
index 000000000..164b23d84
--- /dev/null
+++ b/src/dev/x86/south_bridge/cmos.cc
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/cmos.hh"
+#include "mem/packet_access.hh"
+
+Tick
+X86ISA::Cmos::read(PacketPtr pkt)
+{
+ assert(pkt->getSize() == 1);
+ switch(pkt->getAddr() - addrRange.start)
+ {
+ case 0x0:
+ pkt->set(address);
+ break;
+ case 0x1:
+ pkt->set(readRegister(address));
+ break;
+ default:
+ panic("Read from undefined CMOS port.\n");
+ }
+ return latency;
+}
+
+Tick
+X86ISA::Cmos::write(PacketPtr pkt)
+{
+ assert(pkt->getSize() == 1);
+ switch(pkt->getAddr() - addrRange.start)
+ {
+ case 0x0:
+ address = pkt->get<uint8_t>();
+ break;
+ case 0x1:
+ writeRegister(address, pkt->get<uint8_t>());
+ break;
+ default:
+ panic("Write to undefined CMOS port.\n");
+ }
+ return latency;
+}
+
+uint8_t
+X86ISA::Cmos::readRegister(uint8_t reg)
+{
+ assert(reg < numRegs);
+ if (reg <= 0xD) {
+ return rtc.readData(reg);
+ } else {
+ warn("Reading non-volitile CMOS address %x as %x.\n", reg, regs[reg]);
+ }
+ return regs[reg];
+}
+
+void
+X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val)
+{
+ assert(reg < numRegs);
+ if (reg <= 0xD) {
+ rtc.writeData(reg, val);
+ return;
+ } else {
+ warn("Writing non-volitile CMOS address %x with %x.\n", reg, val);
+ }
+ regs[reg] = val;
+}
diff --git a/src/dev/x86/south_bridge/cmos.hh b/src/dev/x86/south_bridge/cmos.hh
new file mode 100644
index 000000000..6fd7613bc
--- /dev/null
+++ b/src/dev/x86/south_bridge/cmos.hh
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+#define __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/mc146818.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class Cmos : public SubDevice
+{
+ protected:
+ uint8_t address;
+
+ struct tm foo_time;
+
+ static const int numRegs = 128;
+
+ uint8_t regs[numRegs];
+
+ uint8_t readRegister(uint8_t reg);
+ void writeRegister(uint8_t reg, uint8_t val);
+
+ class X86RTC : public MC146818
+ {
+ public:
+ X86RTC(const std::string &n, const struct tm time,
+ bool bcd, Tick frequency) : MC146818(n, time, bcd, frequency)
+ {
+ }
+ protected:
+ void handleEvent()
+ {
+ return;
+ }
+ } rtc;
+
+ public:
+
+ Cmos() : rtc("rtc", foo_time, true, 5000000000)
+ {
+ memset(regs, 0, numRegs * sizeof(uint8_t));
+ address = 0;
+ }
+
+ Cmos(Tick _latency) : SubDevice(_latency),
+ rtc("rtc", foo_time, true, 5000000000)
+ {
+ memset(regs, 0, numRegs * sizeof(uint8_t));
+ address = 0;
+ }
+
+ Cmos(Addr start, Addr size, Tick _latency) :
+ SubDevice(start, size, _latency),
+ rtc("rtc", foo_time, true, 5000000000)
+ {
+ memset(regs, 0, numRegs * sizeof(uint8_t));
+ address = 0;
+ }
+
+ Tick read(PacketPtr pkt);
+
+ Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_CMOS_HH__
diff --git a/src/dev/x86/south_bridge/i8254.cc b/src/dev/x86/south_bridge/i8254.cc
new file mode 100644
index 000000000..fb6723a51
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8254.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/i8254.hh"
+#include "mem/packet_access.hh"
+
+Tick
+X86ISA::I8254::read(PacketPtr pkt)
+{
+ assert(pkt->getSize() == 1);
+ switch(pkt->getAddr() - addrRange.start)
+ {
+ case 0x0:
+ warn("Reading from timer 0 counter.\n");
+ break;
+ case 0x1:
+ warn("Reading from timer 1 counter.\n");
+ break;
+ case 0x2:
+ warn("Reading from timer 2 counter.\n");
+ break;
+ case 0x3:
+ fatal("Reading from timer control word which is read only.\n");
+ break;
+ default:
+ panic("Read from undefined i8254 register.\n");
+ }
+ return SubDevice::read(pkt);
+}
+
+Tick
+X86ISA::I8254::write(PacketPtr pkt)
+{
+ assert(pkt->getSize() == 1);
+ switch(pkt->getAddr() - addrRange.start)
+ {
+ case 0x0:
+ warn("Writing to timer 0 counter.\n");
+ break;
+ case 0x1:
+ warn("Writing to timer 1 counter.\n");
+ break;
+ case 0x2:
+ warn("Writing to timer 2 counter.\n");
+ break;
+ case 0x3:
+ processControlWord(pkt->get<uint8_t>());
+ return latency;
+ default:
+ panic("Write to undefined i8254 register.\n");
+ }
+ return SubDevice::write(pkt);
+}
+
+void
+X86ISA::I8254::processControlWord(uint8_t word)
+{
+ warn("I8254 received control word %x.\n", word);
+}
diff --git a/src/dev/x86/south_bridge/i8254.hh b/src/dev/x86/south_bridge/i8254.hh
new file mode 100644
index 000000000..f246fd8e4
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8254.hh
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_I8254_HH__
+#define __DEV_X86_SOUTH_BRIDGE_I8254_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class I8254 : public SubDevice
+{
+ protected:
+ void processControlWord(uint8_t word);
+
+ public:
+
+ I8254()
+ {}
+ I8254(Tick _latency) : SubDevice(_latency)
+ {}
+ I8254(Addr start, Addr size, Tick _latency) :
+ SubDevice(start, size, _latency)
+ {}
+
+ Tick read(PacketPtr pkt);
+
+ Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__
diff --git a/src/dev/x86/south_bridge/i8259.cc b/src/dev/x86/south_bridge/i8259.cc
new file mode 100644
index 000000000..0cf83dece
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8259.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/i8259.hh"
+
+Tick
+X86ISA::I8259::read(PacketPtr pkt)
+{
+ warn("Reading from PIC device.\n");
+ return SubDevice::read(pkt);
+}
+
+Tick
+X86ISA::I8259::write(PacketPtr pkt)
+{
+ warn("Writing to PIC device.\n");
+ return SubDevice::write(pkt);
+}
diff --git a/src/dev/x86/south_bridge/i8259.hh b/src/dev/x86/south_bridge/i8259.hh
new file mode 100644
index 000000000..3fda75dfb
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8259.hh
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_I8259_HH__
+#define __DEV_X86_SOUTH_BRIDGE_I8259_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class I8259 : public SubDevice
+{
+ public:
+
+ I8259()
+ {}
+ I8259(Tick _latency) : SubDevice(_latency)
+ {}
+ I8259(Addr start, Addr size, Tick _latency) :
+ SubDevice(start, size, _latency)
+ {}
+
+ Tick read(PacketPtr pkt);
+
+ Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_I8259_HH__
diff --git a/src/dev/x86/south_bridge/south_bridge.cc b/src/dev/x86/south_bridge/south_bridge.cc
new file mode 100644
index 000000000..f25b3b811
--- /dev/null
+++ b/src/dev/x86/south_bridge/south_bridge.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/south_bridge.hh"
+
+using namespace X86ISA;
+
+void
+SouthBridge::addDevice(X86ISA::SubDevice & sub)
+{
+ rangeList.push_back(sub.addrRange);
+ rangeMap.insert(sub.addrRange, &sub);
+}
+
+void
+SouthBridge::addressRanges(AddrRangeList &range_list)
+{
+ range_list = rangeList;
+}
+
+Tick
+SouthBridge::read(PacketPtr pkt)
+{
+ RangeMapIt sub =
+ rangeMap.find(RangeSize(pkt->getAddr(), 1));
+ assert(sub != rangeMap.end());
+ return sub->second->read(pkt);
+}
+
+Tick
+SouthBridge::write(PacketPtr pkt)
+{
+ RangeMapIt sub =
+ rangeMap.find(RangeSize(pkt->getAddr(), 1));
+ assert(sub != rangeMap.end());
+ return sub->second->write(pkt);
+}
+
+SouthBridge::SouthBridge(const Params *p) : PioDevice(p),
+ pic1(0x20, 2, p->pio_latency),
+ pic2(0xA0, 2, p->pio_latency),
+ pit(0x40, 4, p->pio_latency),
+ cmos(0x70, 2, p->pio_latency),
+ speaker(0x61, 1, p->pio_latency)
+{
+ addDevice(pic1);
+ addDevice(pic2);
+ addDevice(pit);
+ addDevice(cmos);
+ addDevice(speaker);
+}
+
+SouthBridge *
+SouthBridgeParams::create()
+{
+ return new SouthBridge(this);
+}
diff --git a/src/dev/x86/south_bridge/south_bridge.hh b/src/dev/x86/south_bridge/south_bridge.hh
new file mode 100644
index 000000000..28936fb91
--- /dev/null
+++ b/src/dev/x86/south_bridge/south_bridge.hh
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
+
+#include "base/range_map.hh"
+#include "dev/io_device.hh"
+#include "dev/x86/south_bridge/cmos.hh"
+#include "dev/x86/south_bridge/i8254.hh"
+#include "dev/x86/south_bridge/i8259.hh"
+#include "dev/x86/south_bridge/speaker.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+#include "params/SouthBridge.hh"
+
+class SouthBridge : public PioDevice
+{
+ protected:
+ // PICs
+ X86ISA::I8259 pic1;
+ X86ISA::I8259 pic2;
+
+ // I8254 Programmable Interval Timer
+ X86ISA::I8254 pit;
+
+ // CMOS apperature
+ X86ISA::Cmos cmos;
+
+ // PC speaker
+ X86ISA::Speaker speaker;
+
+ AddrRangeList rangeList;
+
+ typedef range_map<Addr, X86ISA::SubDevice *> RangeMap;
+ typedef RangeMap::iterator RangeMapIt;
+ RangeMap rangeMap;
+
+
+ void addDevice(X86ISA::SubDevice &);
+
+ public:
+ void addressRanges(AddrRangeList &range_list);
+
+ Tick read(PacketPtr pkt);
+ Tick write(PacketPtr pkt);
+
+ typedef SouthBridgeParams Params;
+ SouthBridge(const Params *p);
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+};
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
diff --git a/src/dev/x86/south_bridge/speaker.cc b/src/dev/x86/south_bridge/speaker.cc
new file mode 100644
index 000000000..734dba4c2
--- /dev/null
+++ b/src/dev/x86/south_bridge/speaker.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "base/bitunion.hh"
+#include "dev/x86/south_bridge/speaker.hh"
+#include "mem/packet_access.hh"
+
+BitUnion8(SpeakerControl)
+ Bitfield<0> gate;
+ Bitfield<1> speaker;
+ Bitfield<5> timer;
+EndBitUnion(SpeakerControl)
+
+Tick
+X86ISA::Speaker::read(PacketPtr pkt)
+{
+ assert(pkt->getAddr() == addrRange.start);
+ assert(pkt->getSize() == 1);
+ SpeakerControl val = 0xFF;
+ warn("Reading from speaker device: gate %s, speaker %s, output %s.\n",
+ val.gate ? "on" : "off",
+ val.speaker ? "on" : "off",
+ val.timer ? "on" : "off");
+ pkt->set((uint8_t)val);
+ return latency;
+}
+
+Tick
+X86ISA::Speaker::write(PacketPtr pkt)
+{
+ assert(pkt->getAddr() == addrRange.start);
+ assert(pkt->getSize() == 1);
+ SpeakerControl val = pkt->get<uint8_t>();
+ warn("Writing to speaker device: gate %s, speaker %s.\n",
+ val.gate ? "on" : "off", val.speaker ? "on" : "off");
+ return latency;
+}
diff --git a/src/dev/x86/south_bridge/speaker.hh b/src/dev/x86/south_bridge/speaker.hh
new file mode 100644
index 000000000..df738e42b
--- /dev/null
+++ b/src/dev/x86/south_bridge/speaker.hh
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class Speaker : public SubDevice
+{
+ public:
+
+ Speaker()
+ {}
+ Speaker(Tick _latency) : SubDevice(_latency)
+ {}
+ Speaker(Addr start, Addr size, Tick _latency) :
+ SubDevice(start, size, _latency)
+ {}
+
+ Tick read(PacketPtr pkt);
+
+ Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
diff --git a/src/dev/x86/south_bridge/sub_device.hh b/src/dev/x86/south_bridge/sub_device.hh
new file mode 100644
index 000000000..3cc51bdd9
--- /dev/null
+++ b/src/dev/x86/south_bridge/sub_device.hh
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "mem/packet.hh"
+
+namespace X86ISA
+{
+
+class SubDevice
+{
+ public:
+
+ Range<Addr> addrRange;
+ Tick latency;
+
+ virtual
+ ~SubDevice()
+ {}
+
+ SubDevice()
+ {}
+ SubDevice(Tick _latency) : latency(_latency)
+ {}
+ SubDevice(Addr start, Addr size, Tick _latency) :
+ addrRange(RangeSize(x86IOAddress(start), size)), latency(_latency)
+ {}
+
+ virtual Tick
+ read(PacketPtr pkt)
+ {
+ assert(pkt->getSize() <= 4);
+ pkt->allocate();
+ const uint32_t neg1 = -1;
+ pkt->setData((uint8_t *)(&neg1));
+ return latency;
+ }
+
+ virtual Tick
+ write(PacketPtr pkt)
+ {
+ return latency;
+ }
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-02 16:50:46 +0000