summaryrefslogtreecommitdiff
path: root/src/dev
diff options
context:
space:
mode:
Diffstat (limited to 'src/dev')
-rw-r--r--src/dev/alpha/tsunami_cchip.cc2
-rw-r--r--src/dev/alpha/tsunami_io.cc2
-rw-r--r--src/dev/alpha/tsunami_pchip.cc2
-rw-r--r--src/dev/baddev.cc2
-rw-r--r--src/dev/isa_fake.cc77
-rw-r--r--src/dev/isa_fake.hh15
-rw-r--r--src/dev/sparc/SConscript1
-rw-r--r--src/dev/sparc/t1000.cc132
-rw-r--r--src/dev/sparc/t1000.hh108
9 files changed, 327 insertions, 14 deletions
diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index 924e1d462..eb51d4e49 100644
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -57,7 +57,7 @@ using namespace TheISA;
TsunamiCChip::TsunamiCChip(Params *p)
: BasicPioDevice(p), tsunami(p->tsunami)
{
- pioSize = 0xfffffff;
+ pioSize = 0x10000000;
drir = 0;
ipint = 0;
diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc
index def214a95..8430856ef 100644
--- a/src/dev/alpha/tsunami_io.cc
+++ b/src/dev/alpha/tsunami_io.cc
@@ -430,7 +430,7 @@ TsunamiIO::TsunamiIO(Params *p)
: BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
rtc(p->name + ".rtc", p->tsunami, p->frequency)
{
- pioSize = 0xff;
+ pioSize = 0x100;
// set the back pointer from tsunami to myself
tsunami->io = this;
diff --git a/src/dev/alpha/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc
index 94a7f96e5..f30199337 100644
--- a/src/dev/alpha/tsunami_pchip.cc
+++ b/src/dev/alpha/tsunami_pchip.cc
@@ -53,7 +53,7 @@ using namespace TheISA;
TsunamiPChip::TsunamiPChip(Params *p)
: BasicPioDevice(p)
{
- pioSize = 0xfff;
+ pioSize = 0x1000;
for (int i = 0; i < 4; i++) {
wsba[i] = 0;
diff --git a/src/dev/baddev.cc b/src/dev/baddev.cc
index 1bab93492..6a7060455 100644
--- a/src/dev/baddev.cc
+++ b/src/dev/baddev.cc
@@ -49,7 +49,7 @@ using namespace TheISA;
BadDevice::BadDevice(Params *p)
: BasicPioDevice(p), devname(p->device_name)
{
- pioSize = 0xf;
+ pioSize = 0x10;
}
Tick
diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc
index 40909c6a1..c36ddeb83 100644
--- a/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@ -47,7 +47,10 @@ IsaFake::IsaFake(Params *p)
if (!params()->retBadAddr)
pioSize = p->pio_size;
- memset(&retData, p->retData, sizeof(retData));
+ retData8 = params()->retData8;
+ retData16 = params()->retData16;
+ retData32 = params()->retData32;
+ retData64 = params()->retData64;
}
Tick
@@ -55,6 +58,9 @@ IsaFake::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
+ if (params()->warnAccess != "")
+ warn("Device %s accessed by read to address %#x size=%d\n",
+ name(), pkt->getAddr(), pkt->getSize());
if (params()->retBadAddr) {
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
@@ -65,16 +71,16 @@ IsaFake::read(PacketPtr pkt)
pkt->getAddr(), pkt->getSize());
switch (pkt->getSize()) {
case sizeof(uint64_t):
- pkt->set(retData);
+ pkt->set(retData64);
break;
case sizeof(uint32_t):
- pkt->set((uint32_t)retData);
+ pkt->set(retData32);
break;
case sizeof(uint16_t):
- pkt->set((uint16_t)retData);
+ pkt->set(retData16);
break;
case sizeof(uint8_t):
- pkt->set((uint8_t)retData);
+ pkt->set(retData8);
break;
default:
panic("invalid access size!\n");
@@ -87,6 +93,27 @@ IsaFake::read(PacketPtr pkt)
Tick
IsaFake::write(PacketPtr pkt)
{
+ if (params()->warnAccess != "") {
+ uint64_t data;
+ switch (pkt->getSize()) {
+ case sizeof(uint64_t):
+ data = pkt->get<uint64_t>();
+ break;
+ case sizeof(uint32_t):
+ data = pkt->get<uint32_t>();
+ break;
+ case sizeof(uint16_t):
+ data = pkt->get<uint16_t>();
+ break;
+ case sizeof(uint8_t):
+ data = pkt->get<uint8_t>();
+ break;
+ default:
+ panic("invalid access size!\n");
+ }
+ warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
+ name(), pkt->getAddr(), pkt->getSize(), data);
+ }
if (params()->retBadAddr) {
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
@@ -94,6 +121,25 @@ IsaFake::write(PacketPtr pkt)
} else {
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
+
+ if (params()->updateData) {
+ switch (pkt->getSize()) {
+ case sizeof(uint64_t):
+ retData64 = pkt->get<uint64_t>();
+ break;
+ case sizeof(uint32_t):
+ retData32 = pkt->get<uint32_t>();
+ break;
+ case sizeof(uint16_t):
+ retData16 = pkt->get<uint16_t>();
+ break;
+ case sizeof(uint8_t):
+ retData8 = pkt->get<uint8_t>();
+ break;
+ default:
+ panic("invalid access size!\n");
+ }
+ }
pkt->result = Packet::Success;
}
return pioDelay;
@@ -105,7 +151,12 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
Param<Tick> pio_latency;
Param<Addr> pio_size;
Param<bool> ret_bad_addr;
- Param<uint8_t> ret_data;
+ Param<bool> update_data;
+ Param<std::string> warn_access;
+ Param<uint8_t> ret_data8;
+ Param<uint16_t> ret_data16;
+ Param<uint32_t> ret_data32;
+ Param<uint64_t> ret_data64;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
@@ -117,7 +168,12 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(pio_size, "Size of address range"),
INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
- INIT_PARAM(ret_data, "Data to return if not bad addr"),
+ INIT_PARAM(update_data, "Update returned data"),
+ INIT_PARAM(warn_access, "Warn if this device is touched"),
+ INIT_PARAM(ret_data8, "Data to return if not bad addr"),
+ INIT_PARAM(ret_data16, "Data to return if not bad addr"),
+ INIT_PARAM(ret_data32, "Data to return if not bad addr"),
+ INIT_PARAM(ret_data64, "Data to return if not bad addr"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object")
@@ -131,7 +187,12 @@ CREATE_SIM_OBJECT(IsaFake)
p->pio_delay = pio_latency;
p->pio_size = pio_size;
p->retBadAddr = ret_bad_addr;
- p->retData = ret_data;
+ p->updateData = update_data;
+ p->warnAccess = warn_access;
+ p->retData8= ret_data8;
+ p->retData16 = ret_data16;
+ p->retData32 = ret_data32;
+ p->retData64 = ret_data64;
p->platform = platform;
p->system = system;
return new IsaFake(p);
diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh
index fee41e325..dc2ad48e8 100644
--- a/src/dev/isa_fake.hh
+++ b/src/dev/isa_fake.hh
@@ -40,6 +40,8 @@
#include "dev/alpha/tsunami.hh"
#include "mem/packet.hh"
+#include <string>
+
/**
* IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
* rites. It is meant to be placed at an address range
@@ -54,11 +56,20 @@ class IsaFake : public BasicPioDevice
{
Addr pio_size;
bool retBadAddr;
- uint8_t retData;
+ bool updateData;
+ uint8_t retData8;
+ uint16_t retData16;
+ uint32_t retData32;
+ uint64_t retData64;
+ std::string warnAccess;
};
protected:
const Params *params() const { return (const Params*)_params; }
- uint64_t retData;
+ uint8_t retData8;
+ uint16_t retData16;
+ uint32_t retData32;
+ uint64_t retData64;
+
public:
/**
diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript
index 701e533a8..c37294f0c 100644
--- a/src/dev/sparc/SConscript
+++ b/src/dev/sparc/SConscript
@@ -37,6 +37,7 @@ Import('env')
sources = []
sources += Split('''
+ t1000.cc
''')
# Convert file names to SCons File objects. This takes care of the
diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc
new file mode 100644
index 000000000..4a8de77a5
--- /dev/null
+++ b/src/dev/sparc/t1000.cc
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Implementation of T1000 platform.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "cpu/intr_control.hh"
+#include "dev/simconsole.hh"
+#include "dev/sparc/t1000.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
+
+T1000::T1000(const string &name, System *s, IntrControl *ic)
+ : Platform(name, ic), system(s)
+{
+ // set the back pointer from the system to myself
+ system->platform = this;
+}
+
+Tick
+T1000::intrFrequency()
+{
+ panic("Need implementation\n");
+}
+
+void
+T1000::postConsoleInt()
+{
+ warn_once("Don't know what interrupt to post for console.\n");
+ //panic("Need implementation\n");
+}
+
+void
+T1000::clearConsoleInt()
+{
+ warn_once("Don't know what interrupt to clear for console.\n");
+ //panic("Need implementation\n");
+}
+
+void
+T1000::postPciInt(int line)
+{
+ panic("Need implementation\n");
+}
+
+void
+T1000::clearPciInt(int line)
+{
+ panic("Need implementation\n");
+}
+
+Addr
+T1000::pciToDma(Addr pciAddr) const
+{
+ panic("Need implementation\n");
+}
+
+
+Addr
+T1000::calcConfigAddr(int bus, int dev, int func)
+{
+ panic("Need implementation\n");
+}
+
+void
+T1000::serialize(std::ostream &os)
+{
+ panic("Need implementation\n");
+}
+
+void
+T1000::unserialize(Checkpoint *cp, const std::string &section)
+{
+ panic("Need implementation\n");
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
+
+ SimObjectParam<System *> system;
+ SimObjectParam<IntrControl *> intrctrl;
+
+END_DECLARE_SIM_OBJECT_PARAMS(T1000)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
+
+ INIT_PARAM(system, "system"),
+ INIT_PARAM(intrctrl, "interrupt controller")
+
+END_INIT_SIM_OBJECT_PARAMS(T1000)
+
+CREATE_SIM_OBJECT(T1000)
+{
+ return new T1000(getInstanceName(), system, intrctrl);
+}
+
+REGISTER_SIM_OBJECT("T1000", T1000)
diff --git a/src/dev/sparc/t1000.hh b/src/dev/sparc/t1000.hh
new file mode 100644
index 000000000..2955763a9
--- /dev/null
+++ b/src/dev/sparc/t1000.hh
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/**
+ * @file
+ * Declaration of top level class for the T1000 platform chips. This class just
+ * retains pointers to all its children so the children can communicate.
+ */
+
+#ifndef __DEV_T1000_HH__
+#define __DEV_T1000_HH__
+
+#include "dev/platform.hh"
+
+class IdeController;
+class System;
+
+class T1000 : public Platform
+{
+ public:
+ /** Pointer to the system */
+ System *system;
+
+ public:
+ /**
+ * Constructor for the Tsunami Class.
+ * @param name name of the object
+ * @param s system the object belongs to
+ * @param intctrl pointer to the interrupt controller
+ */
+ T1000(const std::string &name, System *s, IntrControl *intctrl);
+
+ /**
+ * Return the interrupting frequency to AlphaAccess
+ * @return frequency of RTC interrupts
+ */
+ virtual Tick intrFrequency();
+
+ /**
+ * Cause the cpu to post a serial interrupt to the CPU.
+ */
+ virtual void postConsoleInt();
+
+ /**
+ * Clear a posted CPU interrupt
+ */
+ virtual void clearConsoleInt();
+
+ /**
+ * Cause the chipset to post a cpi interrupt to the CPU.
+ */
+ virtual void postPciInt(int line);
+
+ /**
+ * Clear a posted PCI->CPU interrupt
+ */
+ virtual void clearPciInt(int line);
+
+
+ virtual Addr pciToDma(Addr pciAddr) const;
+
+ /**
+ * Calculate the configuration address given a bus/dev/func.
+ */
+ virtual Addr calcConfigAddr(int bus, int dev, int func);
+
+ /**
+ * Serialize this object to the given output stream.
+ * @param os The stream to serialize to.
+ */
+ virtual void serialize(std::ostream &os);
+
+ /**
+ * Reconstruct the state of this object from a checkpoint.
+ * @param cp The checkpoint use.
+ * @param section The section name of this object
+ */
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+#endif // __DEV_T1000_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 12:14:39 +0000