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-rw-r--r--src/dev/SConscript9
-rw-r--r--src/dev/Terminal.py (renamed from src/dev/SimConsole.py)9
-rw-r--r--src/dev/Uart.py2
-rw-r--r--src/dev/alpha/AlphaBackdoor.py (renamed from src/dev/alpha/AlphaConsole.py)6
-rw-r--r--src/dev/alpha/SConscript6
-rw-r--r--src/dev/alpha/Tsunami.py10
-rw-r--r--src/dev/alpha/backdoor.cc (renamed from src/dev/alpha/console.cc)40
-rw-r--r--src/dev/alpha/backdoor.hh (renamed from src/dev/alpha/console.hh)22
-rw-r--r--src/dev/alpha/tsunami.cc2
-rw-r--r--src/dev/etherdevice.cc367
-rw-r--r--src/dev/etherdevice.hh54
-rw-r--r--src/dev/etherpkt.cc2
-rw-r--r--src/dev/etherpkt.hh17
-rw-r--r--src/dev/i8254xGBe.cc14
-rw-r--r--src/dev/i8254xGBe.hh1
-rwxr-xr-xsrc/dev/mips/Malta.py11
-rw-r--r--src/dev/mips/MipsBackdoor.py (renamed from src/dev/mips/MipsConsole.py)6
-rwxr-xr-xsrc/dev/mips/SConscript4
-rwxr-xr-xsrc/dev/mips/backdoor.cc (renamed from src/dev/mips/console.cc)38
-rwxr-xr-xsrc/dev/mips/backdoor.hh (renamed from src/dev/mips/console.hh)24
-rwxr-xr-xsrc/dev/mips/malta.cc2
-rw-r--r--src/dev/ns_gige.cc373
-rw-r--r--src/dev/ns_gige.hh55
-rw-r--r--src/dev/pktfifo.cc55
-rw-r--r--src/dev/pktfifo.hh108
-rw-r--r--src/dev/platform.hh2
-rw-r--r--src/dev/sinic.cc6
-rw-r--r--src/dev/sparc/T1000.py12
-rw-r--r--src/dev/sparc/t1000.cc2
-rw-r--r--src/dev/terminal.cc (renamed from src/dev/simconsole.cc)90
-rw-r--r--src/dev/terminal.hh (renamed from src/dev/simconsole.hh)36
-rw-r--r--src/dev/uart.cc8
-rw-r--r--src/dev/uart.hh4
-rw-r--r--src/dev/uart8250.cc16
-rw-r--r--src/dev/uart8250.hh2
-rw-r--r--src/dev/x86/PC.py15
-rw-r--r--src/dev/x86/pc.cc2
37 files changed, 768 insertions, 664 deletions
diff --git a/src/dev/SConscript b/src/dev/SConscript
index bd6b16c43..54148b68b 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -39,13 +39,14 @@ if env['FULL_SYSTEM']:
SimObject('Ide.py')
SimObject('Pci.py')
SimObject('Platform.py')
- SimObject('SimConsole.py')
SimObject('SimpleDisk.py')
+ SimObject('Terminal.py')
SimObject('Uart.py')
Source('baddev.cc')
Source('disk_image.cc')
Source('etherbus.cc')
+ Source('etherdevice.cc')
Source('etherdump.cc')
Source('etherint.cc')
Source('etherlink.cc')
@@ -63,14 +64,12 @@ if env['FULL_SYSTEM']:
Source('pcidev.cc')
Source('pktfifo.cc')
Source('platform.cc')
- Source('simconsole.cc')
Source('simple_disk.cc')
Source('sinic.cc')
+ Source('terminal.cc')
Source('uart.cc')
Source('uart8250.cc')
- TraceFlag('Console')
- TraceFlag('ConsoleVerbose')
TraceFlag('DiskImageRead')
TraceFlag('DiskImageWrite')
TraceFlag('DMA')
@@ -92,6 +91,8 @@ if env['FULL_SYSTEM']:
TraceFlag('PciConfigAll')
TraceFlag('SimpleDisk')
TraceFlag('SimpleDiskData')
+ TraceFlag('Terminal')
+ TraceFlag('TerminalVerbose')
TraceFlag('Uart')
CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
diff --git a/src/dev/SimConsole.py b/src/dev/Terminal.py
index bb8420527..d67019198 100644
--- a/src/dev/SimConsole.py
+++ b/src/dev/Terminal.py
@@ -30,10 +30,9 @@ from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-class SimConsole(SimObject):
- type = 'SimConsole'
- append_name = Param.Bool(True, "append name() to filename")
+class Terminal(SimObject):
+ type = 'Terminal'
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
port = Param.TcpPort(3456, "listen port")
- number = Param.Int(0, "console number")
- output = Param.String('console', "file to dump output to")
+ number = Param.Int(0, "terminal number")
+ output = Param.Bool(True, "Enable output dump to file")
diff --git a/src/dev/Uart.py b/src/dev/Uart.py
index e32517a4c..c5db3c42f 100644
--- a/src/dev/Uart.py
+++ b/src/dev/Uart.py
@@ -34,7 +34,7 @@ from Device import BasicPioDevice
class Uart(BasicPioDevice):
type = 'Uart'
abstract = True
- sim_console = Param.SimConsole(Parent.any, "The console")
+ terminal = Param.Terminal(Parent.any, "The terminal")
class Uart8250(Uart):
type = 'Uart8250'
diff --git a/src/dev/alpha/AlphaConsole.py b/src/dev/alpha/AlphaBackdoor.py
index 43c7ef954..fa9627164 100644
--- a/src/dev/alpha/AlphaConsole.py
+++ b/src/dev/alpha/AlphaBackdoor.py
@@ -30,9 +30,9 @@ from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
-class AlphaConsole(BasicPioDevice):
- type = 'AlphaConsole'
+class AlphaBackdoor(BasicPioDevice):
+ type = 'AlphaBackdoor'
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
disk = Param.SimpleDisk("Simple Disk")
- sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
+ terminal = Param.Terminal(Parent.any, "The console terminal")
system = Param.AlphaSystem(Parent.any, "system object")
diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript
index 6bd26a9b1..4dbb73903 100644
--- a/src/dev/alpha/SConscript
+++ b/src/dev/alpha/SConscript
@@ -32,14 +32,14 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
- SimObject('AlphaConsole.py')
+ SimObject('AlphaBackdoor.py')
SimObject('Tsunami.py')
- Source('console.cc')
+ Source('backdoor.cc')
Source('tsunami.cc')
Source('tsunami_cchip.cc')
Source('tsunami_io.cc')
Source('tsunami_pchip.cc')
- TraceFlag('AlphaConsole')
+ TraceFlag('AlphaBackdoor')
TraceFlag('Tsunami')
diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py
index 484976c09..5440486b6 100644
--- a/src/dev/alpha/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -28,12 +28,12 @@
from m5.params import *
from m5.proxy import *
+from BadDevice import BadDevice
+from AlphaBackdoor import AlphaBackdoor
from Device import BasicPioDevice, IsaFake, BadAddr
+from Pci import PciConfigAll
from Platform import Platform
-from AlphaConsole import AlphaConsole
from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
@@ -87,7 +87,7 @@ class Tsunami(Platform):
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
io = TsunamiIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0x801fc0003f8)
- console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+ backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
@@ -120,4 +120,4 @@ class Tsunami(Platform):
self.fb.pio = bus.port
self.io.pio = bus.port
self.uart.pio = bus.port
- self.console.pio = bus.port
+ self.backdoor.pio = bus.port
diff --git a/src/dev/alpha/console.cc b/src/dev/alpha/backdoor.cc
index 493a21f99..3ba6cbd24 100644
--- a/src/dev/alpha/console.cc
+++ b/src/dev/alpha/backdoor.cc
@@ -32,7 +32,7 @@
*/
/** @file
- * Alpha Console Definition
+ * Alpha Console Backdoor Definition
*/
#include <cstddef>
@@ -44,21 +44,21 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "dev/alpha/console.hh"
+#include "dev/alpha/backdoor.hh"
#include "dev/platform.hh"
-#include "dev/simconsole.hh"
#include "dev/simple_disk.hh"
+#include "dev/terminal.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
-#include "params/AlphaConsole.hh"
+#include "params/AlphaBackdoor.hh"
#include "sim/sim_object.hh"
using namespace std;
using namespace AlphaISA;
-AlphaConsole::AlphaConsole(const Params *p)
- : BasicPioDevice(p), disk(p->disk), console(p->sim_console),
+AlphaBackdoor::AlphaBackdoor(const Params *p)
+ : BasicPioDevice(p), disk(p->disk), terminal(p->terminal),
system(p->system), cpu(p->cpu)
{
@@ -81,7 +81,7 @@ AlphaConsole::AlphaConsole(const Params *p)
}
void
-AlphaConsole::startup()
+AlphaBackdoor::startup()
{
system->setAlphaAccess(pioAddr);
alphaAccess->numCPUs = system->getNumCPUs();
@@ -94,7 +94,7 @@ AlphaConsole::startup()
}
Tick
-AlphaConsole::read(PacketPtr pkt)
+AlphaBackdoor::read(PacketPtr pkt)
{
/** XXX Do we want to push the addr munging to a bus brige or something? So
@@ -132,14 +132,14 @@ AlphaConsole::read(PacketPtr pkt)
*/
pkt->setBadAddress();
}
- DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
+ DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr,
pkt->get<uint32_t>());
break;
case sizeof(uint64_t):
switch (daddr)
{
case offsetof(AlphaAccess, inputChar):
- pkt->set(console->console_in());
+ pkt->set(terminal->console_in());
break;
case offsetof(AlphaAccess, cpuClock):
pkt->set(alphaAccess->cpuClock);
@@ -183,7 +183,7 @@ AlphaConsole::read(PacketPtr pkt)
else
panic("Unknown 64bit access, %#x\n", daddr);
}
- DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
+ DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr,
pkt->get<uint64_t>());
break;
default:
@@ -193,7 +193,7 @@ AlphaConsole::read(PacketPtr pkt)
}
Tick
-AlphaConsole::write(PacketPtr pkt)
+AlphaBackdoor::write(PacketPtr pkt)
{
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
@@ -228,7 +228,7 @@ AlphaConsole::write(PacketPtr pkt)
break;
case offsetof(AlphaAccess, outputChar):
- console->out((char)(val & 0xff));
+ terminal->out((char)(val & 0xff));
break;
default:
@@ -248,7 +248,7 @@ AlphaConsole::write(PacketPtr pkt)
}
void
-AlphaConsole::Access::serialize(ostream &os)
+AlphaBackdoor::Access::serialize(ostream &os)
{
SERIALIZE_SCALAR(last_offset);
SERIALIZE_SCALAR(version);
@@ -270,7 +270,7 @@ AlphaConsole::Access::serialize(ostream &os)
}
void
-AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
+AlphaBackdoor::Access::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(last_offset);
UNSERIALIZE_SCALAR(version);
@@ -292,19 +292,19 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
}
void
-AlphaConsole::serialize(ostream &os)
+AlphaBackdoor::serialize(ostream &os)
{
alphaAccess->serialize(os);
}
void
-AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
+AlphaBackdoor::unserialize(Checkpoint *cp, const std::string &section)
{
alphaAccess->unserialize(cp, section);
}
-AlphaConsole *
-AlphaConsoleParams::create()
+AlphaBackdoor *
+AlphaBackdoorParams::create()
{
- return new AlphaConsole(this);
+ return new AlphaBackdoor(this);
}
diff --git a/src/dev/alpha/console.hh b/src/dev/alpha/backdoor.hh
index e77a7fad6..ad3c79823 100644
--- a/src/dev/alpha/console.hh
+++ b/src/dev/alpha/backdoor.hh
@@ -29,28 +29,28 @@
*/
/** @file
- * System Console Interface
+ * System Console Backdoor Interface
*/
-#ifndef __ALPHA_CONSOLE_HH__
-#define __ALPHA_CONSOLE_HH__
+#ifndef __DEV_ALPHA_BACKDOOR_HH__
+#define __DEV_ALPHA_BACKDOOR_HH__
#include "base/range.hh"
#include "dev/alpha/access.h"
#include "dev/io_device.hh"
-#include "params/AlphaConsole.hh"
+#include "params/AlphaBackdoor.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
class BaseCPU;
-class SimConsole;
+class Terminal;
class AlphaSystem;
class SimpleDisk;
/**
* Memory mapped interface to the system console. This device
* represents a shared data region between the OS Kernel and the
- * System Console.
+ * System Console Backdoor.
*
* The system console is a small standalone program that is initially
* run when the system boots. It contains the necessary code to
@@ -72,7 +72,7 @@ class SimpleDisk;
* primarily used doing boot before the kernel has loaded its device
* drivers.
*/
-class AlphaConsole : public BasicPioDevice
+class AlphaBackdoor : public BasicPioDevice
{
protected:
struct Access : public AlphaAccess
@@ -90,7 +90,7 @@ class AlphaConsole : public BasicPioDevice
SimpleDisk *disk;
/** the system console (the terminal) is accessable from the console */
- SimConsole *console;
+ Terminal *terminal;
/** a pointer to the system we are running in */
AlphaSystem *system;
@@ -99,8 +99,8 @@ class AlphaConsole : public BasicPioDevice
BaseCPU *cpu;
public:
- typedef AlphaConsoleParams Params;
- AlphaConsole(const Params *p);
+ typedef AlphaBackdoorParams Params;
+ AlphaBackdoor(const Params *p);
const Params *
params() const
@@ -123,4 +123,4 @@ class AlphaConsole : public BasicPioDevice
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
-#endif // __ALPHA_CONSOLE_HH__
+#endif // __DEV_ALPHA_BACKDOOR_HH__
diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc
index 5bc0de5da..7923fc3f1 100644
--- a/src/dev/alpha/tsunami.cc
+++ b/src/dev/alpha/tsunami.cc
@@ -37,11 +37,11 @@
#include <vector>
#include "cpu/intr_control.hh"
-#include "dev/simconsole.hh"
#include "dev/alpha/tsunami_cchip.hh"
#include "dev/alpha/tsunami_pchip.hh"
#include "dev/alpha/tsunami_io.hh"
#include "dev/alpha/tsunami.hh"
+#include "dev/terminal.hh"
#include "sim/system.hh"
using namespace std;
diff --git a/src/dev/etherdevice.cc b/src/dev/etherdevice.cc
new file mode 100644
index 000000000..5341c02c4
--- /dev/null
+++ b/src/dev/etherdevice.cc
@@ -0,0 +1,367 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Lisa Hsu
+ */
+
+#include "dev/etherdevice.hh"
+#include "sim/stats.hh"
+
+void
+EtherDevice::regStats()
+{
+ txBytes
+ .name(name() + ".txBytes")
+ .desc("Bytes Transmitted")
+ .prereq(txBytes)
+ ;
+
+ rxBytes
+ .name(name() + ".rxBytes")
+ .desc("Bytes Received")
+ .prereq(rxBytes)
+ ;
+
+ txPackets
+ .name(name() + ".txPackets")
+ .desc("Number of Packets Transmitted")
+ .prereq(txBytes)
+ ;
+
+ rxPackets
+ .name(name() + ".rxPackets")
+ .desc("Number of Packets Received")
+ .prereq(rxBytes)
+ ;
+
+ txIpChecksums
+ .name(name() + ".txIpChecksums")
+ .desc("Number of tx IP Checksums done by device")
+ .precision(0)
+ .prereq(txBytes)
+ ;
+
+ rxIpChecksums
+ .name(name() + ".rxIpChecksums")
+ .desc("Number of rx IP Checksums done by device")
+ .precision(0)
+ .prereq(rxBytes)
+ ;
+
+ txTcpChecksums
+ .name(name() + ".txTcpChecksums")
+ .desc("Number of tx TCP Checksums done by device")
+ .precision(0)
+ .prereq(txBytes)
+ ;
+
+ rxTcpChecksums
+ .name(name() + ".rxTcpChecksums")
+ .desc("Number of rx TCP Checksums done by device")
+ .precision(0)
+ .prereq(rxBytes)
+ ;
+
+ txUdpChecksums
+ .name(name() + ".txUdpChecksums")
+ .desc("Number of tx UDP Checksums done by device")
+ .precision(0)
+ .prereq(txBytes)
+ ;
+
+ rxUdpChecksums
+ .name(name() + ".rxUdpChecksums")
+ .desc("Number of rx UDP Checksums done by device")
+ .precision(0)
+ .prereq(rxBytes)
+ ;
+
+ descDmaReads
+ .name(name() + ".descDMAReads")
+ .desc("Number of descriptors the device read w/ DMA")
+ .precision(0)
+ ;
+
+ descDmaWrites
+ .name(name() + ".descDMAWrites")
+ .desc("Number of descriptors the device wrote w/ DMA")
+ .precision(0)
+ ;
+
+ descDmaRdBytes
+ .name(name() + ".descDmaReadBytes")
+ .desc("number of descriptor bytes read w/ DMA")
+ .precision(0)
+ ;
+
+ descDmaWrBytes
+ .name(name() + ".descDmaWriteBytes")
+ .desc("number of descriptor bytes write w/ DMA")
+ .precision(0)
+ ;
+
+ txBandwidth
+ .name(name() + ".txBandwidth")
+ .desc("Transmit Bandwidth (bits/s)")
+ .precision(0)
+ .prereq(txBytes)
+ ;
+
+ rxBandwidth
+ .name(name() + ".rxBandwidth")
+ .desc("Receive Bandwidth (bits/s)")
+ .precision(0)
+ .prereq(rxBytes)
+ ;
+
+ totBandwidth
+ .name(name() + ".totBandwidth")
+ .desc("Total Bandwidth (bits/s)")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
+ totPackets
+ .name(name() + ".totPackets")
+ .desc("Total Packets")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
+ totBytes
+ .name(name() + ".totBytes")
+ .desc("Total Bytes")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
+ totPacketRate
+ .name(name() + ".totPPS")
+ .desc("Total Tranmission Rate (packets/s)")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
+ txPacketRate
+ .name(name() + ".txPPS")
+ .desc("Packet Tranmission Rate (packets/s)")
+ .precision(0)
+ .prereq(txBytes)
+ ;
+
+ rxPacketRate
+ .name(name() + ".rxPPS")
+ .desc("Packet Reception Rate (packets/s)")
+ .precision(0)
+ .prereq(rxBytes)
+ ;
+
+ postedSwi
+ .name(name() + ".postedSwi")
+ .desc("number of software interrupts posted to CPU")
+ .precision(0)
+ ;
+
+ totalSwi
+ .name(name() + ".totalSwi")
+ .desc("total number of Swi written to ISR")
+ .precision(0)
+ ;
+
+ coalescedSwi
+ .name(name() + ".coalescedSwi")
+ .desc("average number of Swi's coalesced into each post")
+ .precision(0)
+ ;
+
+ postedRxIdle
+ .name(name() + ".postedRxIdle")
+ .desc("number of rxIdle interrupts posted to CPU")
+ .precision(0)
+ ;
+
+ totalRxIdle
+ .name(name() + ".totalRxIdle")
+ .desc("total number of RxIdle written to ISR")
+ .precision(0)
+ ;
+
+ coalescedRxIdle
+ .name(name() + ".coalescedRxIdle")
+ .desc("average number of RxIdle's coalesced into each post")
+ .precision(0)
+ ;
+
+ postedRxOk
+ .name(name() + ".postedRxOk")
+ .desc("number of RxOk interrupts posted to CPU")
+ .precision(0)
+ ;
+
+ totalRxOk
+ .name(name() + ".totalRxOk")
+ .desc("total number of RxOk written to ISR")
+ .precision(0)
+ ;
+
+ coalescedRxOk
+ .name(name() + ".coalescedRxOk")
+ .desc("average number of RxOk's coalesced into each post")
+ .precision(0)
+ ;
+
+ postedRxDesc
+ .name(name() + ".postedRxDesc")
+ .desc("number of RxDesc interrupts posted to CPU")
+ .precision(0)
+ ;
+
+ totalRxDesc
+ .name(name() + ".totalRxDesc")
+ .desc("total number of RxDesc written to ISR")
+ .precision(0)
+ ;
+
+ coalescedRxDesc
+ .name(name() + ".coalescedRxDesc")
+ .desc("average number of RxDesc's coalesced into each post")
+ .precision(0)
+ ;
+
+ postedTxOk
+ .name(name() + ".postedTxOk")
+ .desc("number of TxOk interrupts posted to CPU")
+ .precision(0)
+ ;
+
+ totalTxOk
+ .name(name() + ".totalTxOk")
+ .desc("total number of TxOk written to ISR")
+ .precision(0)
+ ;
+
+ coalescedTxOk
+ .name(name() + ".coalescedTxOk")
+ .desc("average number of TxOk's coalesced into each post")
+ .precision(0)
+ ;
+
+ postedTxIdle
+ .name(name() + ".postedTxIdle")
+ .desc("number of TxIdle interrupts posted to CPU")
+ .precision(0)
+ ;
+
+ totalTxIdle
+ .name(name() + ".totalTxIdle")
+ .desc("total number of TxIdle written to ISR")
+ .precision(0)
+ ;
+
+ coalescedTxIdle
+ .name(name() + ".coalescedTxIdle")
+ .desc("average number of TxIdle's coalesced into each post")
+ .precision(0)
+ ;
+
+ postedTxDesc
+ .name(name() + ".postedTxDesc")
+ .desc("number of TxDesc interrupts posted to CPU")
+ .precision(0)
+ ;
+
+ totalTxDesc
+ .name(name() + ".totalTxDesc")
+ .desc("total number of TxDesc written to ISR")
+ .precision(0)
+ ;
+
+ coalescedTxDesc
+ .name(name() + ".coalescedTxDesc")
+ .desc("average number of TxDesc's coalesced into each post")
+ .precision(0)
+ ;
+
+ postedRxOrn
+ .name(name() + ".postedRxOrn")
+ .desc("number of RxOrn posted to CPU")
+ .precision(0)
+ ;
+
+ totalRxOrn
+ .name(name() + ".totalRxOrn")
+ .desc("total number of RxOrn written to ISR")
+ .precision(0)
+ ;
+
+ coalescedRxOrn
+ .name(name() + ".coalescedRxOrn")
+ .desc("average number of RxOrn's coalesced into each post")
+ .precision(0)
+ ;
+
+ coalescedTotal
+ .name(name() + ".coalescedTotal")
+ .desc("average number of interrupts coalesced into each post")
+ .precision(0)
+ ;
+
+ postedInterrupts
+ .name(name() + ".postedInterrupts")
+ .desc("number of posts to CPU")
+ .precision(0)
+ ;
+
+ droppedPackets
+ .name(name() + ".droppedPackets")
+ .desc("number of packets dropped")
+ .precision(0)
+ ;
+
+ coalescedSwi = totalSwi / postedInterrupts;
+ coalescedRxIdle = totalRxIdle / postedInterrupts;
+ coalescedRxOk = totalRxOk / postedInterrupts;
+ coalescedRxDesc = totalRxDesc / postedInterrupts;
+ coalescedTxOk = totalTxOk / postedInterrupts;
+ coalescedTxIdle = totalTxIdle / postedInterrupts;
+ coalescedTxDesc = totalTxDesc / postedInterrupts;
+ coalescedRxOrn = totalRxOrn / postedInterrupts;
+
+ coalescedTotal = (totalSwi + totalRxIdle + totalRxOk + totalRxDesc +
+ totalTxOk + totalTxIdle + totalTxDesc +
+ totalRxOrn) / postedInterrupts;
+
+ txBandwidth = txBytes * Stats::constant(8) / simSeconds;
+ rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
+ totBandwidth = txBandwidth + rxBandwidth;
+ totBytes = txBytes + rxBytes;
+ totPackets = txPackets + rxPackets;
+
+ txPacketRate = txPackets / simSeconds;
+ rxPacketRate = rxPackets / simSeconds;
+}
diff --git a/src/dev/etherdevice.hh b/src/dev/etherdevice.hh
index a0df0d741..e43f3b686 100644
--- a/src/dev/etherdevice.hh
+++ b/src/dev/etherdevice.hh
@@ -36,6 +36,7 @@
#ifndef __DEV_ETHERDEVICE_HH__
#define __DEV_ETHERDEVICE_HH__
+#include "base/statistics.hh"
#include "dev/pcidev.hh"
#include "params/EtherDevice.hh"
#include "sim/sim_object.hh"
@@ -64,6 +65,59 @@ class EtherDevice : public PciDev
/** Additional function to return the Port of a memory object. */
virtual EtherInt *getEthPort(const std::string &if_name, int idx = -1) = 0;
+ public:
+ void regStats();
+
+ protected:
+ Stats::Scalar<> txBytes;
+ Stats::Scalar<> rxBytes;
+ Stats::Scalar<> txPackets;
+ Stats::Scalar<> rxPackets;
+ Stats::Scalar<> txIpChecksums;
+ Stats::Scalar<> rxIpChecksums;
+ Stats::Scalar<> txTcpChecksums;
+ Stats::Scalar<> rxTcpChecksums;
+ Stats::Scalar<> txUdpChecksums;
+ Stats::Scalar<> rxUdpChecksums;
+ Stats::Scalar<> descDmaReads;
+ Stats::Scalar<> descDmaWrites;
+ Stats::Scalar<> descDmaRdBytes;
+ Stats::Scalar<> descDmaWrBytes;
+ Stats::Formula totBandwidth;
+ Stats::Formula totPackets;
+ Stats::Formula totBytes;
+ Stats::Formula totPacketRate;
+ Stats::Formula txBandwidth;
+ Stats::Formula rxBandwidth;
+ Stats::Formula txPacketRate;
+ Stats::Formula rxPacketRate;
+ Stats::Scalar<> postedSwi;
+ Stats::Formula coalescedSwi;
+ Stats::Scalar<> totalSwi;
+ Stats::Scalar<> postedRxIdle;
+ Stats::Formula coalescedRxIdle;
+ Stats::Scalar<> totalRxIdle;
+ Stats::Scalar<> postedRxOk;
+ Stats::Formula coalescedRxOk;
+ Stats::Scalar<> totalRxOk;
+ Stats::Scalar<> postedRxDesc;
+ Stats::Formula coalescedRxDesc;
+ Stats::Scalar<> totalRxDesc;
+ Stats::Scalar<> postedTxOk;
+ Stats::Formula coalescedTxOk;
+ Stats::Scalar<> totalTxOk;
+ Stats::Scalar<> postedTxIdle;
+ Stats::Formula coalescedTxIdle;
+ Stats::Scalar<> totalTxIdle;
+ Stats::Scalar<> postedTxDesc;
+ Stats::Formula coalescedTxDesc;
+ Stats::Scalar<> totalTxDesc;
+ Stats::Scalar<> postedRxOrn;
+ Stats::Formula coalescedRxOrn;
+ Stats::Scalar<> totalRxOrn;
+ Stats::Formula coalescedTotal;
+ Stats::Scalar<> postedInterrupts;
+ Stats::Scalar<> droppedPackets;
};
#endif //__DEV_ETHERDEVICE_HH__
diff --git a/src/dev/etherpkt.cc b/src/dev/etherpkt.cc
index 5c552b4bd..2c8343eb0 100644
--- a/src/dev/etherpkt.cc
+++ b/src/dev/etherpkt.cc
@@ -40,7 +40,6 @@ void
EthPacketData::serialize(const string &base, ostream &os)
{
paramOut(os, base + ".length", length);
- paramOut(os, base + ".slack", slack);
arrayParamOut(os, base + ".data", data, length);
}
@@ -49,7 +48,6 @@ EthPacketData::unserialize(const string &base, Checkpoint *cp,
const string &section)
{
paramIn(cp, section, base + ".length", length);
- paramIn(cp, section, base + ".slack", slack);
if (length)
arrayParamIn(cp, section, base + ".data", data, length);
}
diff --git a/src/dev/etherpkt.hh b/src/dev/etherpkt.hh
index db2e0d6b5..623895ba8 100644
--- a/src/dev/etherpkt.hh
+++ b/src/dev/etherpkt.hh
@@ -60,24 +60,17 @@ class EthPacketData : public RefCounted
*/
int length;
- /*
- * Extra space taken up by the packet in whatever data structure
- * it is in.
- *
- * NOTE: This can only be use by *one* data structure at a time!
- */
- int slack;
-
public:
- EthPacketData() : data(NULL), length(0), slack(0)
+ EthPacketData()
+ : data(NULL), length(0)
{ }
explicit EthPacketData(size_t size)
- : data(new uint8_t[size]), length(0), slack(0)
+ : data(new uint8_t[size]), length(0)
{ }
- EthPacketData(std::auto_ptr<uint8_t> d, int l, int s = 0)
- : data(d.release()), length(l), slack(s)
+ EthPacketData(std::auto_ptr<uint8_t> d, int l)
+ : data(d.release()), length(l)
{ }
~EthPacketData() { if (data) delete [] data; }
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index ff255d5f7..3b1970432 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -584,6 +584,7 @@ IGbE::postInterrupt(IntTypes t, bool now)
if (interEvent.scheduled()) {
interEvent.deschedule();
}
+ postedInterrupts++;
cpuPostInt();
} else {
DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
@@ -740,6 +741,7 @@ IGbE::RxDescCache::pktComplete()
DPRINTF(EthernetDesc, "Checking IP checksum\n");
status |= RXDS_IPCS;
desc->csum = htole(cksum(ip));
+ igbe->rxIpChecksums++;
if (cksum(ip) != 0) {
err |= RXDE_IPE;
DPRINTF(EthernetDesc, "Checksum is bad!!\n");
@@ -750,6 +752,7 @@ IGbE::RxDescCache::pktComplete()
DPRINTF(EthernetDesc, "Checking TCP checksum\n");
status |= RXDS_TCPCS;
desc->csum = htole(cksum(tcp));
+ igbe->rxTcpChecksums++;
if (cksum(tcp) != 0) {
DPRINTF(EthernetDesc, "Checksum is bad!!\n");
err |= RXDE_TCPE;
@@ -761,6 +764,7 @@ IGbE::RxDescCache::pktComplete()
DPRINTF(EthernetDesc, "Checking UDP checksum\n");
status |= RXDS_UDPCS;
desc->csum = htole(cksum(udp));
+ igbe->rxUdpChecksums++;
if (cksum(udp) != 0) {
DPRINTF(EthernetDesc, "Checksum is bad!!\n");
err |= RXDE_TCPE;
@@ -994,6 +998,7 @@ IGbE::TxDescCache::pktComplete()
if (TxdOp::ixsm(desc)) {
ip->sum(0);
ip->sum(cksum(ip));
+ igbe->txIpChecksums++;
DPRINTF(EthernetDesc, "Calculated IP checksum\n");
}
if (TxdOp::txsm(desc)) {
@@ -1002,11 +1007,13 @@ IGbE::TxDescCache::pktComplete()
if (tcp) {
tcp->sum(0);
tcp->sum(cksum(tcp));
+ igbe->txTcpChecksums++;
DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
} else if (udp) {
assert(udp);
udp->sum(0);
udp->sum(cksum(udp));
+ igbe->txUdpChecksums++;
DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
} else {
panic("Told to checksum, but don't know how\n");
@@ -1247,6 +1254,9 @@ IGbE::txStateMachine()
bool
IGbE::ethRxPkt(EthPacketPtr pkt)
{
+ rxBytes += pkt->length;
+ rxPackets++;
+
DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
if (!regs.rctl.en()) {
@@ -1380,6 +1390,10 @@ IGbE::txWire()
}
DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
txFifo.avail());
+
+ txBytes += txFifo.front()->length;
+ txPackets++;
+
txFifo.pop();
} else {
// We'll get woken up when the packet ethTxDone() gets called
diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index 0daf094c1..7957eb515 100644
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -39,7 +39,6 @@
#include <string>
#include "base/inet.hh"
-#include "base/statistics.hh"
#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index d321a6361..d215bf329 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -28,12 +28,13 @@
from m5.params import *
from m5.proxy import *
+
+from BadDevice import BadDevice
from Device import BasicPioDevice
+from MipsBackdoor import MipsBackdoor
+from Pci import PciConfigAll
from Platform import Platform
-from MipsConsole import MipsConsole
from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
class MaltaCChip(BasicPioDevice):
type = 'MaltaCChip'
@@ -56,7 +57,7 @@ class Malta(Platform):
cchip = MaltaCChip(pio_addr=0x801a0000000)
io = MaltaIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0xBFD003F8)
- console = MipsConsole(pio_addr=0xBFD00F00, disk=Parent.simple_disk)
+ backdoor = MipsBackdoor(pio_addr=0xBFD00F00, disk=Parent.simple_disk)
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
@@ -65,4 +66,4 @@ class Malta(Platform):
self.cchip.pio = bus.port
self.io.pio = bus.port
self.uart.pio = bus.port
- self.console.pio = bus.port
+ self.backdoor.pio = bus.port
diff --git a/src/dev/mips/MipsConsole.py b/src/dev/mips/MipsBackdoor.py
index 36575677a..f65250238 100644
--- a/src/dev/mips/MipsConsole.py
+++ b/src/dev/mips/MipsBackdoor.py
@@ -30,9 +30,9 @@ from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
-class MipsConsole(BasicPioDevice):
- type = 'MipsConsole'
+class MipsBackdoor(BasicPioDevice):
+ type = 'MipsBackdoor'
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
disk = Param.SimpleDisk("Simple Disk")
- sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
+ terminal = Param.Terminal(Parent.any, "The console terminal")
system = Param.MipsSystem(Parent.any, "system object")
diff --git a/src/dev/mips/SConscript b/src/dev/mips/SConscript
index 22e91ff09..e83e47ebd 100755
--- a/src/dev/mips/SConscript
+++ b/src/dev/mips/SConscript
@@ -32,13 +32,13 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
- SimObject('MipsConsole.py')
+ SimObject('MipsBackdoor.py')
SimObject('Malta.py')
TraceFlag('Malta')
TraceFlag('MC146818')
- Source('console.cc')
+ Source('backdoor.cc')
Source('malta.cc')
Source('malta_cchip.cc')
Source('malta_io.cc')
diff --git a/src/dev/mips/console.cc b/src/dev/mips/backdoor.cc
index 185e1acbc..313f12567 100755
--- a/src/dev/mips/console.cc
+++ b/src/dev/mips/backdoor.cc
@@ -32,7 +32,7 @@
*/
/** @file
- * Mips Console Definition
+ * Mips Console Backdoor Definition
*/
#include <cstddef>
#include <string>
@@ -43,22 +43,22 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "dev/mips/console.hh"
+#include "dev/mips/backdoor.hh"
#include "dev/platform.hh"
-#include "dev/simconsole.hh"
#include "dev/simple_disk.hh"
+#include "dev/terminal.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
-#include "params/MipsConsole.hh"
+#include "params/MipsBackdoor.hh"
#include "sim/sim_object.hh"
using namespace std;
using namespace MipsISA;
-MipsConsole::MipsConsole(const Params *p)
- : BasicPioDevice(p), disk(p->disk), console(p->sim_console),
+MipsBackdoor::MipsBackdoor(const Params *p)
+ : BasicPioDevice(p), disk(p->disk), terminal(p->terminal),
system(p->system), cpu(p->cpu)
{
@@ -81,7 +81,7 @@ MipsConsole::MipsConsole(const Params *p)
}
void
-MipsConsole::startup()
+MipsBackdoor::startup()
{
system->setMipsAccess(pioAddr);
mipsAccess->numCPUs = system->getNumCPUs();
@@ -94,7 +94,7 @@ MipsConsole::startup()
}
Tick
-MipsConsole::read(PacketPtr pkt)
+MipsBackdoor::read(PacketPtr pkt)
{
/** XXX Do we want to push the addr munging to a bus brige or something? So
@@ -125,7 +125,7 @@ MipsConsole::read(PacketPtr pkt)
pkt->set(mipsAccess->intrClockFrequency);
break;
case offsetof(MipsAccess, inputChar):
- pkt->set(console->console_in());
+ pkt->set(terminal->console_in());
break;
case offsetof(MipsAccess, cpuClock):
pkt->set(mipsAccess->cpuClock);
@@ -169,7 +169,7 @@ MipsConsole::read(PacketPtr pkt)
else
panic("Unknown 32bit access, %#x\n", daddr);
}
- //DPRINTF(MipsConsole, "read: offset=%#x val=%#x\n", daddr,
+ //DPRINTF(MipsBackdoor, "read: offset=%#x val=%#x\n", daddr,
// pkt->get<uint64_t>());
break;
default:
@@ -181,7 +181,7 @@ MipsConsole::read(PacketPtr pkt)
}
Tick
-MipsConsole::write(PacketPtr pkt)
+MipsBackdoor::write(PacketPtr pkt)
{
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
@@ -215,7 +215,7 @@ MipsConsole::write(PacketPtr pkt)
break;
case offsetof(MipsAccess, outputChar):
- console->out((char)(val & 0xff));
+ terminal->out((char)(val & 0xff));
break;
default:
@@ -235,7 +235,7 @@ MipsConsole::write(PacketPtr pkt)
}
void
-MipsConsole::Access::serialize(ostream &os)
+MipsBackdoor::Access::serialize(ostream &os)
{
SERIALIZE_SCALAR(last_offset);
SERIALIZE_SCALAR(version);
@@ -257,7 +257,7 @@ MipsConsole::Access::serialize(ostream &os)
}
void
-MipsConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
+MipsBackdoor::Access::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(last_offset);
UNSERIALIZE_SCALAR(version);
@@ -279,19 +279,19 @@ MipsConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
}
void
-MipsConsole::serialize(ostream &os)
+MipsBackdoor::serialize(ostream &os)
{
mipsAccess->serialize(os);
}
void
-MipsConsole::unserialize(Checkpoint *cp, const std::string &section)
+MipsBackdoor::unserialize(Checkpoint *cp, const std::string &section)
{
mipsAccess->unserialize(cp, section);
}
-MipsConsole *
-MipsConsoleParams::create()
+MipsBackdoor *
+MipsBackdoorParams::create()
{
- return new MipsConsole(this);
+ return new MipsBackdoor(this);
}
diff --git a/src/dev/mips/console.hh b/src/dev/mips/backdoor.hh
index 34792090d..b8cc0ae46 100755
--- a/src/dev/mips/console.hh
+++ b/src/dev/mips/backdoor.hh
@@ -29,28 +29,28 @@
*/
/** @file
- * System Console Interface
+ * System Console Backdoor Interface
*/
-#ifndef __MIPS_CONSOLE_HH__
-#define __MIPS_CONSOLE_HH__
+#ifndef __DEV_MIPS_BACKDOOR_HH__
+#define __DEV_MIPS_BACKDOOR_HH__
#include "base/range.hh"
#include "dev/mips/access.h"
#include "dev/io_device.hh"
-#include "params/MipsConsole.hh"
+#include "params/MipsBackdoor.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
class BaseCPU;
-class SimConsole;
+class Terminal;
class MipsSystem;
class SimpleDisk;
/**
* Memory mapped interface to the system console. This device
* represents a shared data region between the OS Kernel and the
- * System Console.
+ * System Console Backdoor.
*
* The system console is a small standalone program that is initially
* run when the system boots. It contains the necessary code to
@@ -72,7 +72,7 @@ class SimpleDisk;
* primarily used doing boot before the kernel has loaded its device
* drivers.
*/
-class MipsConsole : public BasicPioDevice
+class MipsBackdoor : public BasicPioDevice
{
protected:
struct Access : public MipsAccess
@@ -89,8 +89,8 @@ class MipsConsole : public BasicPioDevice
/** the disk must be accessed from the console */
SimpleDisk *disk;
- /** the system console (the terminal) is accessable from the console */
- SimConsole *console;
+ /** the system terminal is accessable from the console */
+ Terminal *terminal;
/** a pointer to the system we are running in */
MipsSystem *system;
@@ -99,8 +99,8 @@ class MipsConsole : public BasicPioDevice
BaseCPU *cpu;
public:
- typedef MipsConsoleParams Params;
- MipsConsole(const Params *p);
+ typedef MipsBackdoorParams Params;
+ MipsBackdoor(const Params *p);
const Params *
params() const
@@ -123,4 +123,4 @@ class MipsConsole : public BasicPioDevice
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
-#endif // __MIPS_CONSOLE_HH__
+#endif // __DEV_MIPS_BACKDOOR_HH__
diff --git a/src/dev/mips/malta.cc b/src/dev/mips/malta.cc
index 0b1fa15ba..21e79d999 100755
--- a/src/dev/mips/malta.cc
+++ b/src/dev/mips/malta.cc
@@ -38,11 +38,11 @@
#include <vector>
#include "cpu/intr_control.hh"
-#include "dev/simconsole.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_pchip.hh"
#include "dev/mips/malta_io.hh"
#include "dev/mips/malta.hh"
+#include "dev/terminal.hh"
#include "params/Malta.hh"
#include "sim/system.hh"
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index bd48bdca5..f19ca20e5 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -46,7 +46,6 @@
#include "params/NSGigE.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
-#include "sim/stats.hh"
#include "sim/system.hh"
const char *NsRxStateStrings[] =
@@ -131,341 +130,6 @@ NSGigE::NSGigE(Params *p)
NSGigE::~NSGigE()
{}
-void
-NSGigE::regStats()
-{
- txBytes
- .name(name() + ".txBytes")
- .desc("Bytes Transmitted")
- .prereq(txBytes)
- ;
-
- rxBytes
- .name(name() + ".rxBytes")
- .desc("Bytes Received")
- .prereq(rxBytes)
- ;
-
- txPackets
- .name(name() + ".txPackets")
- .desc("Number of Packets Transmitted")
- .prereq(txBytes)
- ;
-
- rxPackets
- .name(name() + ".rxPackets")
- .desc("Number of Packets Received")
- .prereq(rxBytes)
- ;
-
- txIpChecksums
- .name(name() + ".txIpChecksums")
- .desc("Number of tx IP Checksums done by device")
- .precision(0)
- .prereq(txBytes)
- ;
-
- rxIpChecksums
- .name(name() + ".rxIpChecksums")
- .desc("Number of rx IP Checksums done by device")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- txTcpChecksums
- .name(name() + ".txTcpChecksums")
- .desc("Number of tx TCP Checksums done by device")
- .precision(0)
- .prereq(txBytes)
- ;
-
- rxTcpChecksums
- .name(name() + ".rxTcpChecksums")
- .desc("Number of rx TCP Checksums done by device")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- txUdpChecksums
- .name(name() + ".txUdpChecksums")
- .desc("Number of tx UDP Checksums done by device")
- .precision(0)
- .prereq(txBytes)
- ;
-
- rxUdpChecksums
- .name(name() + ".rxUdpChecksums")
- .desc("Number of rx UDP Checksums done by device")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- descDmaReads
- .name(name() + ".descDMAReads")
- .desc("Number of descriptors the device read w/ DMA")
- .precision(0)
- ;
-
- descDmaWrites
- .name(name() + ".descDMAWrites")
- .desc("Number of descriptors the device wrote w/ DMA")
- .precision(0)
- ;
-
- descDmaRdBytes
- .name(name() + ".descDmaReadBytes")
- .desc("number of descriptor bytes read w/ DMA")
- .precision(0)
- ;
-
- descDmaWrBytes
- .name(name() + ".descDmaWriteBytes")
- .desc("number of descriptor bytes write w/ DMA")
- .precision(0)
- ;
-
- txBandwidth
- .name(name() + ".txBandwidth")
- .desc("Transmit Bandwidth (bits/s)")
- .precision(0)
- .prereq(txBytes)
- ;
-
- rxBandwidth
- .name(name() + ".rxBandwidth")
- .desc("Receive Bandwidth (bits/s)")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- totBandwidth
- .name(name() + ".totBandwidth")
- .desc("Total Bandwidth (bits/s)")
- .precision(0)
- .prereq(totBytes)
- ;
-
- totPackets
- .name(name() + ".totPackets")
- .desc("Total Packets")
- .precision(0)
- .prereq(totBytes)
- ;
-
- totBytes
- .name(name() + ".totBytes")
- .desc("Total Bytes")
- .precision(0)
- .prereq(totBytes)
- ;
-
- totPacketRate
- .name(name() + ".totPPS")
- .desc("Total Tranmission Rate (packets/s)")
- .precision(0)
- .prereq(totBytes)
- ;
-
- txPacketRate
- .name(name() + ".txPPS")
- .desc("Packet Tranmission Rate (packets/s)")
- .precision(0)
- .prereq(txBytes)
- ;
-
- rxPacketRate
- .name(name() + ".rxPPS")
- .desc("Packet Reception Rate (packets/s)")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- postedSwi
- .name(name() + ".postedSwi")
- .desc("number of software interrupts posted to CPU")
- .precision(0)
- ;
-
- totalSwi
- .name(name() + ".totalSwi")
- .desc("total number of Swi written to ISR")
- .precision(0)
- ;
-
- coalescedSwi
- .name(name() + ".coalescedSwi")
- .desc("average number of Swi's coalesced into each post")
- .precision(0)
- ;
-
- postedRxIdle
- .name(name() + ".postedRxIdle")
- .desc("number of rxIdle interrupts posted to CPU")
- .precision(0)
- ;
-
- totalRxIdle
- .name(name() + ".totalRxIdle")
- .desc("total number of RxIdle written to ISR")
- .precision(0)
- ;
-
- coalescedRxIdle
- .name(name() + ".coalescedRxIdle")
- .desc("average number of RxIdle's coalesced into each post")
- .precision(0)
- ;
-
- postedRxOk
- .name(name() + ".postedRxOk")
- .desc("number of RxOk interrupts posted to CPU")
- .precision(0)
- ;
-
- totalRxOk
- .name(name() + ".totalRxOk")
- .desc("total number of RxOk written to ISR")
- .precision(0)
- ;
-
- coalescedRxOk
- .name(name() + ".coalescedRxOk")
- .desc("average number of RxOk's coalesced into each post")
- .precision(0)
- ;
-
- postedRxDesc
- .name(name() + ".postedRxDesc")
- .desc("number of RxDesc interrupts posted to CPU")
- .precision(0)
- ;
-
- totalRxDesc
- .name(name() + ".totalRxDesc")
- .desc("total number of RxDesc written to ISR")
- .precision(0)
- ;
-
- coalescedRxDesc
- .name(name() + ".coalescedRxDesc")
- .desc("average number of RxDesc's coalesced into each post")
- .precision(0)
- ;
-
- postedTxOk
- .name(name() + ".postedTxOk")
- .desc("number of TxOk interrupts posted to CPU")
- .precision(0)
- ;
-
- totalTxOk
- .name(name() + ".totalTxOk")
- .desc("total number of TxOk written to ISR")
- .precision(0)
- ;
-
- coalescedTxOk
- .name(name() + ".coalescedTxOk")
- .desc("average number of TxOk's coalesced into each post")
- .precision(0)
- ;
-
- postedTxIdle
- .name(name() + ".postedTxIdle")
- .desc("number of TxIdle interrupts posted to CPU")
- .precision(0)
- ;
-
- totalTxIdle
- .name(name() + ".totalTxIdle")
- .desc("total number of TxIdle written to ISR")
- .precision(0)
- ;
-
- coalescedTxIdle
- .name(name() + ".coalescedTxIdle")
- .desc("average number of TxIdle's coalesced into each post")
- .precision(0)
- ;
-
- postedTxDesc
- .name(name() + ".postedTxDesc")
- .desc("number of TxDesc interrupts posted to CPU")
- .precision(0)
- ;
-
- totalTxDesc
- .name(name() + ".totalTxDesc")
- .desc("total number of TxDesc written to ISR")
- .precision(0)
- ;
-
- coalescedTxDesc
- .name(name() + ".coalescedTxDesc")
- .desc("average number of TxDesc's coalesced into each post")
- .precision(0)
- ;
-
- postedRxOrn
- .name(name() + ".postedRxOrn")
- .desc("number of RxOrn posted to CPU")
- .precision(0)
- ;
-
- totalRxOrn
- .name(name() + ".totalRxOrn")
- .desc("total number of RxOrn written to ISR")
- .precision(0)
- ;
-
- coalescedRxOrn
- .name(name() + ".coalescedRxOrn")
- .desc("average number of RxOrn's coalesced into each post")
- .precision(0)
- ;
-
- coalescedTotal
- .name(name() + ".coalescedTotal")
- .desc("average number of interrupts coalesced into each post")
- .precision(0)
- ;
-
- postedInterrupts
- .name(name() + ".postedInterrupts")
- .desc("number of posts to CPU")
- .precision(0)
- ;
-
- droppedPackets
- .name(name() + ".droppedPackets")
- .desc("number of packets dropped")
- .precision(0)
- ;
-
- coalescedSwi = totalSwi / postedInterrupts;
- coalescedRxIdle = totalRxIdle / postedInterrupts;
- coalescedRxOk = totalRxOk / postedInterrupts;
- coalescedRxDesc = totalRxDesc / postedInterrupts;
- coalescedTxOk = totalTxOk / postedInterrupts;
- coalescedTxIdle = totalTxIdle / postedInterrupts;
- coalescedTxDesc = totalTxDesc / postedInterrupts;
- coalescedRxOrn = totalRxOrn / postedInterrupts;
-
- coalescedTotal = (totalSwi + totalRxIdle + totalRxOk + totalRxDesc +
- totalTxOk + totalTxIdle + totalTxDesc +
- totalRxOrn) / postedInterrupts;
-
- txBandwidth = txBytes * Stats::constant(8) / simSeconds;
- rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
- totBandwidth = txBandwidth + rxBandwidth;
- totBytes = txBytes + rxBytes;
- totPackets = txPackets + rxPackets;
-
- txPacketRate = txPackets / simSeconds;
- rxPacketRate = rxPackets / simSeconds;
-}
-
-
/**
* This is to write to the PCI general configuration registers
*/
@@ -1186,6 +850,7 @@ NSGigE::devIntrPost(uint32_t interrupts)
Tick when = curTick;
if ((regs.isr & regs.imr & ISR_NODELAY) == 0)
when += intrDelay;
+ postedInterrupts++;
cpuIntrPost(when);
}
}
@@ -1226,9 +891,6 @@ NSGigE::devIntrClear(uint32_t interrupts)
postedRxOrn++;
}
- if (regs.isr & regs.imr & ISR_IMPL)
- postedInterrupts++;
-
interrupts &= ~ISR_NOIMPL;
regs.isr &= ~interrupts;
@@ -2036,19 +1698,34 @@ NSGigE::txKick()
IpPtr ip(txPacket);
if (extsts & EXTSTS_UDPPKT) {
UdpPtr udp(ip);
- udp->sum(0);
- udp->sum(cksum(udp));
- txUdpChecksums++;
+ if (udp) {
+ udp->sum(0);
+ udp->sum(cksum(udp));
+ txUdpChecksums++;
+ } else {
+ debug_break();
+ warn_once("UDPPKT set, but not UDP!\n");
+ }
} else if (extsts & EXTSTS_TCPPKT) {
TcpPtr tcp(ip);
- tcp->sum(0);
- tcp->sum(cksum(tcp));
- txTcpChecksums++;
+ if (tcp) {
+ tcp->sum(0);
+ tcp->sum(cksum(tcp));
+ txTcpChecksums++;
+ } else {
+ debug_break();
+ warn_once("TCPPKT set, but not UDP!\n");
+ }
}
if (extsts & EXTSTS_IPPKT) {
- ip->sum(0);
- ip->sum(cksum(ip));
- txIpChecksums++;
+ if (ip) {
+ ip->sum(0);
+ ip->sum(cksum(ip));
+ txIpChecksums++;
+ } else {
+ debug_break();
+ warn_once("IPPKT set, but not UDP!\n");
+ }
}
}
diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh
index dfdd81b66..a55a1c75e 100644
--- a/src/dev/ns_gige.hh
+++ b/src/dev/ns_gige.hh
@@ -38,7 +38,6 @@
#define __DEV_NS_GIGE_HH__
#include "base/inet.hh"
-#include "base/statistics.hh"
#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
@@ -372,60 +371,6 @@ class NSGigE : public EtherDevice
virtual void unserialize(Checkpoint *cp, const std::string &section);
virtual void resume();
-
- public:
- void regStats();
-
- private:
- Stats::Scalar<> txBytes;
- Stats::Scalar<> rxBytes;
- Stats::Scalar<> txPackets;
- Stats::Scalar<> rxPackets;
- Stats::Scalar<> txIpChecksums;
- Stats::Scalar<> rxIpChecksums;
- Stats::Scalar<> txTcpChecksums;
- Stats::Scalar<> rxTcpChecksums;
- Stats::Scalar<> txUdpChecksums;
- Stats::Scalar<> rxUdpChecksums;
- Stats::Scalar<> descDmaReads;
- Stats::Scalar<> descDmaWrites;
- Stats::Scalar<> descDmaRdBytes;
- Stats::Scalar<> descDmaWrBytes;
- Stats::Formula totBandwidth;
- Stats::Formula totPackets;
- Stats::Formula totBytes;
- Stats::Formula totPacketRate;
- Stats::Formula txBandwidth;
- Stats::Formula rxBandwidth;
- Stats::Formula txPacketRate;
- Stats::Formula rxPacketRate;
- Stats::Scalar<> postedSwi;
- Stats::Formula coalescedSwi;
- Stats::Scalar<> totalSwi;
- Stats::Scalar<> postedRxIdle;
- Stats::Formula coalescedRxIdle;
- Stats::Scalar<> totalRxIdle;
- Stats::Scalar<> postedRxOk;
- Stats::Formula coalescedRxOk;
- Stats::Scalar<> totalRxOk;
- Stats::Scalar<> postedRxDesc;
- Stats::Formula coalescedRxDesc;
- Stats::Scalar<> totalRxDesc;
- Stats::Scalar<> postedTxOk;
- Stats::Formula coalescedTxOk;
- Stats::Scalar<> totalTxOk;
- Stats::Scalar<> postedTxIdle;
- Stats::Formula coalescedTxIdle;
- Stats::Scalar<> totalTxIdle;
- Stats::Scalar<> postedTxDesc;
- Stats::Formula coalescedTxDesc;
- Stats::Scalar<> totalTxDesc;
- Stats::Scalar<> postedRxOrn;
- Stats::Formula coalescedRxOrn;
- Stats::Scalar<> totalRxOrn;
- Stats::Formula coalescedTotal;
- Stats::Scalar<> postedInterrupts;
- Stats::Scalar<> droppedPackets;
};
/*
diff --git a/src/dev/pktfifo.cc b/src/dev/pktfifo.cc
index 37f7ff680..97d6c04af 100644
--- a/src/dev/pktfifo.cc
+++ b/src/dev/pktfifo.cc
@@ -40,23 +40,24 @@ PacketFifo::copyout(void *dest, int offset, int len)
if (offset + len >= size())
return false;
- list<EthPacketPtr>::iterator p = fifo.begin();
- list<EthPacketPtr>::iterator end = fifo.end();
+ iterator i = fifo.begin();
+ iterator end = fifo.end();
while (len > 0) {
- while (offset >= (*p)->length) {
- offset -= (*p)->length;
- ++p;
+ EthPacketPtr &pkt = i->packet;
+ while (offset >= pkt->length) {
+ offset -= pkt->length;
+ ++i;
}
- if (p == end)
+ if (i == end)
panic("invalid fifo");
- int size = min((*p)->length - offset, len);
- memcpy(data, (*p)->data, size);
+ int size = min(pkt->length - offset, len);
+ memcpy(data, pkt->data, size);
offset = 0;
len -= size;
data += size;
- ++p;
+ ++i;
}
return true;
@@ -64,6 +65,26 @@ PacketFifo::copyout(void *dest, int offset, int len)
void
+PacketFifoEntry::serialize(const string &base, ostream &os)
+{
+ packet->serialize(base + ".packet", os);
+ paramOut(os, base + ".slack", slack);
+ paramOut(os, base + ".number", number);
+ paramOut(os, base + ".priv", priv);
+}
+
+void
+PacketFifoEntry::unserialize(const string &base, Checkpoint *cp,
+ const string &section)
+{
+ packet = new EthPacketData(16384);
+ packet->unserialize(base + ".packet", cp, section);
+ paramIn(cp, section, base + ".slack", slack);
+ paramIn(cp, section, base + ".number", number);
+ paramIn(cp, section, base + ".priv", priv);
+}
+
+void
PacketFifo::serialize(const string &base, ostream &os)
{
paramOut(os, base + ".size", _size);
@@ -72,11 +93,11 @@ PacketFifo::serialize(const string &base, ostream &os)
paramOut(os, base + ".packets", fifo.size());
int i = 0;
- list<EthPacketPtr>::iterator p = fifo.begin();
- list<EthPacketPtr>::iterator end = fifo.end();
- while (p != end) {
- (*p)->serialize(csprintf("%s.packet%d", base, i), os);
- ++p;
+ iterator entry = fifo.begin();
+ iterator end = fifo.end();
+ while (entry != end) {
+ entry->serialize(csprintf("%s.entry%d", base, i), os);
+ ++entry;
++i;
}
}
@@ -94,8 +115,8 @@ PacketFifo::unserialize(const string &base, Checkpoint *cp,
fifo.clear();
for (int i = 0; i < fifosize; ++i) {
- EthPacketPtr p = new EthPacketData(16384);
- p->unserialize(csprintf("%s.packet%d", base, i), cp, section);
- fifo.push_back(p);
+ PacketFifoEntry entry;
+ entry.unserialize(csprintf("%s.entry%d", base, i), cp, section);
+ fifo.push_back(entry);
}
}
diff --git a/src/dev/pktfifo.hh b/src/dev/pktfifo.hh
index 45157ba41..6ded248be 100644
--- a/src/dev/pktfifo.hh
+++ b/src/dev/pktfifo.hh
@@ -39,20 +39,59 @@
#include "sim/serialize.hh"
class Checkpoint;
+
+struct PacketFifoEntry
+{
+ EthPacketPtr packet;
+ uint64_t number;
+ int slack;
+ int priv;
+
+ PacketFifoEntry()
+ {
+ clear();
+ }
+
+ PacketFifoEntry(const PacketFifoEntry &s)
+ : packet(s.packet), number(s.number), slack(s.slack), priv(s.priv)
+ {
+ }
+
+ PacketFifoEntry(EthPacketPtr p, uint64_t n)
+ : packet(p), number(n), slack(0), priv(-1)
+ {
+ }
+
+ void clear()
+ {
+ packet = NULL;
+ number = 0;
+ slack = 0;
+ priv = -1;
+ }
+
+ void serialize(const std::string &base, std::ostream &os);
+ void unserialize(const std::string &base, Checkpoint *cp,
+ const std::string &section);
+};
+
class PacketFifo
{
public:
- typedef std::list<EthPacketPtr> fifo_list;
+
+ typedef std::list<PacketFifoEntry> fifo_list;
typedef fifo_list::iterator iterator;
protected:
- std::list<EthPacketPtr> fifo;
+ std::list<PacketFifoEntry> fifo;
+ uint64_t _counter;
int _maxsize;
int _size;
int _reserved;
public:
- explicit PacketFifo(int max) : _maxsize(max), _size(0), _reserved(0) {}
+ explicit PacketFifo(int max)
+ : _counter(0), _maxsize(max), _size(0), _reserved(0) {}
virtual ~PacketFifo() {}
int packets() const { return fifo.size(); }
@@ -73,18 +112,21 @@ class PacketFifo
iterator begin() { return fifo.begin(); }
iterator end() { return fifo.end(); }
- EthPacketPtr front() { return fifo.front(); }
+ EthPacketPtr front() { return fifo.begin()->packet; }
bool push(EthPacketPtr ptr)
{
assert(ptr->length);
assert(_reserved <= ptr->length);
- assert(ptr->slack == 0);
if (avail() < ptr->length - _reserved)
return false;
_size += ptr->length;
- fifo.push_back(ptr);
+
+ PacketFifoEntry entry;
+ entry.packet = ptr;
+ entry.number = _counter++;
+ fifo.push_back(entry);
_reserved = 0;
return true;
}
@@ -94,18 +136,17 @@ class PacketFifo
if (empty())
return;
- EthPacketPtr &packet = fifo.front();
- _size -= packet->length;
- _size -= packet->slack;
- packet->slack = 0;
- packet = NULL;
+ iterator entry = fifo.begin();
+ _size -= entry->packet->length;
+ _size -= entry->slack;
+ entry->packet = NULL;
fifo.pop_front();
}
void clear()
{
for (iterator i = begin(); i != end(); ++i)
- (*i)->slack = 0;
+ i->clear();
fifo.clear();
_size = 0;
_reserved = 0;
@@ -113,51 +154,48 @@ class PacketFifo
void remove(iterator i)
{
- EthPacketPtr &packet = *i;
if (i != fifo.begin()) {
iterator prev = i;
--prev;
assert(prev != fifo.end());
- (*prev)->slack += packet->length;
+ prev->slack += i->packet->length;
+ prev->slack += i->slack;
} else {
- _size -= packet->length;
- _size -= packet->slack;
+ _size -= i->packet->length;
+ _size -= i->slack;
}
- packet->slack = 0;
- packet = NULL;
+ i->clear();
fifo.erase(i);
}
bool copyout(void *dest, int offset, int len);
- int countPacketsBefore(iterator end)
+ int countPacketsBefore(iterator i)
{
- iterator i = fifo.begin();
- int count = 0;
-
- while (i != end) {
- ++count;
- ++i;
- }
-
- return count;
+ if (i == fifo.end())
+ return 0;
+ return i->number - fifo.begin()->number;
}
int countPacketsAfter(iterator i)
{
iterator end = fifo.end();
- int count = 0;
+ if (i == end)
+ return 0;
+ return (--end)->number - i->number;
+ }
- while (i != end) {
- ++count;
- ++i;
- }
+ void check()
+ {
+ int total = 0;
+ for (iterator i = begin(); i != end(); ++i)
+ total += i->packet->length + i->slack;
- return count;
+ if (total != _size)
+ panic("total (%d) is not == to size (%d)\n", total, _size);
}
-
/**
* Serialization stuff
*/
diff --git a/src/dev/platform.hh b/src/dev/platform.hh
index 699b168ce..fc556787d 100644
--- a/src/dev/platform.hh
+++ b/src/dev/platform.hh
@@ -46,7 +46,7 @@
class PciConfigAll;
class IntrControl;
-class SimConsole;
+class Terminal;
class Uart;
class System;
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index c63966528..e875a8bcc 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -893,12 +893,12 @@ Device::rxKick()
// Grab a new packet from the fifo.
vnic->rxPacket = rxFifoPtr++;
vnic->rxPacketOffset = 0;
- vnic->rxPacketBytes = (*vnic->rxPacket)->length;
+ vnic->rxPacketBytes = vnic->rxPacket->packet->length;
assert(vnic->rxPacketBytes);
vnic->rxDoneData = 0;
/* scope for variables */ {
- IpPtr ip(*vnic->rxPacket);
+ IpPtr ip(vnic->rxPacket->packet);
if (ip) {
DPRINTF(Ethernet, "ID is %d\n", ip->id());
vnic->rxDoneData |= Regs::RxDone_IpPacket;
@@ -941,7 +941,7 @@ Device::rxKick()
Regs::get_RxData_Addr(vnic->RxData));
rxDmaLen = std::min<int>(Regs::get_RxData_Len(vnic->RxData),
vnic->rxPacketBytes);
- rxDmaData = (*vnic->rxPacket)->data + vnic->rxPacketOffset;
+ rxDmaData = vnic->rxPacket->packet->data + vnic->rxPacketOffset;
rxState = rxCopy;
if (rxDmaAddr == 1LL) {
rxState = rxCopyDone;
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index a033e27e2..cbf390737 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -29,9 +29,9 @@
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Uart import Uart8250
from Platform import Platform
-from SimConsole import SimConsole
+from Terminal import Terminal
+from Uart import Uart8250
class MmDisk(BasicPioDevice):
@@ -98,11 +98,11 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
- hconsole = SimConsole()
+ hterm = Terminal()
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
- pconsole = SimConsole()
+ pterm = Terminal()
puart0 = Uart8250(pio_addr=0x1f10000000)
iob = Iob()
@@ -116,8 +116,8 @@ class T1000(Platform):
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.hvuart.sim_console = self.hconsole
- self.puart0.sim_console = self.pconsole
+ self.hvuart.terminal = self.hterm
+ self.puart0.terminal = self.pterm
self.fake_clk.pio = bus.port
self.fake_membnks.pio = bus.port
self.fake_l2_1.pio = bus.port
diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc
index 49e44af55..d42b442a1 100644
--- a/src/dev/sparc/t1000.cc
+++ b/src/dev/sparc/t1000.cc
@@ -37,8 +37,8 @@
#include <vector>
#include "cpu/intr_control.hh"
-#include "dev/simconsole.hh"
#include "dev/sparc/t1000.hh"
+#include "dev/terminal.hh"
#include "sim/system.hh"
using namespace std;
diff --git a/src/dev/simconsole.cc b/src/dev/terminal.cc
index e8dc1b210..47f280ad3 100644
--- a/src/dev/simconsole.cc
+++ b/src/dev/terminal.cc
@@ -30,7 +30,7 @@
*/
/* @file
- * Implements the user interface to a serial console
+ * Implements the user interface to a serial terminal
*/
#include <sys/ioctl.h>
@@ -50,7 +50,7 @@
#include "base/socket.hh"
#include "base/trace.hh"
#include "dev/platform.hh"
-#include "dev/simconsole.hh"
+#include "dev/terminal.hh"
#include "dev/uart.hh"
using namespace std;
@@ -59,50 +59,46 @@ using namespace std;
/*
* Poll event for the listen socket
*/
-SimConsole::ListenEvent::ListenEvent(SimConsole *c, int fd, int e)
- : PollEvent(fd, e), cons(c)
+Terminal::ListenEvent::ListenEvent(Terminal *t, int fd, int e)
+ : PollEvent(fd, e), term(t)
{
}
void
-SimConsole::ListenEvent::process(int revent)
+Terminal::ListenEvent::process(int revent)
{
- cons->accept();
+ term->accept();
}
/*
* Poll event for the data socket
*/
-SimConsole::DataEvent::DataEvent(SimConsole *c, int fd, int e)
- : PollEvent(fd, e), cons(c)
+Terminal::DataEvent::DataEvent(Terminal *t, int fd, int e)
+ : PollEvent(fd, e), term(t)
{
}
void
-SimConsole::DataEvent::process(int revent)
+Terminal::DataEvent::process(int revent)
{
if (revent & POLLIN)
- cons->data();
+ term->data();
else if (revent & POLLNVAL)
- cons->detach();
+ term->detach();
}
/*
- * SimConsole code
+ * Terminal code
*/
-SimConsole::SimConsole(const Params *p)
+Terminal::Terminal(const Params *p)
: SimObject(p), listenEvent(NULL), dataEvent(NULL), number(p->number),
data_fd(-1), txbuf(16384), rxbuf(16384), outfile(NULL)
#if TRACING_ON == 1
, linebuf(16384)
#endif
{
- if (!p->output.empty()) {
- if (p->append_name)
- outfile = simout.find(p->output + "." + p->name);
- else
- outfile = simout.find(p->output);
-
+ if (p->output) {
+ outfile = simout.find(p->name);
outfile->setf(ios::unitbuf);
}
@@ -110,7 +106,7 @@ SimConsole::SimConsole(const Params *p)
listen(p->port);
}
-SimConsole::~SimConsole()
+Terminal::~Terminal()
{
if (data_fd != -1)
::close(data_fd);
@@ -123,15 +119,15 @@ SimConsole::~SimConsole()
}
///////////////////////////////////////////////////////////////////////
-// socket creation and console attach
+// socket creation and terminal attach
//
void
-SimConsole::listen(int port)
+Terminal::listen(int port)
{
while (!listener.listen(port, true)) {
- DPRINTF(Console,
- ": can't bind address console port %d inuse PID %d\n",
+ DPRINTF(Terminal,
+ ": can't bind address terminal port %d inuse PID %d\n",
port, getpid());
port++;
}
@@ -147,14 +143,14 @@ SimConsole::listen(int port)
}
void
-SimConsole::accept()
+Terminal::accept()
{
if (!listener.islistening())
panic("%s: cannot accept a connection if not listening!", name());
int fd = listener.accept(true);
if (data_fd != -1) {
- char message[] = "console already attached!\n";
+ char message[] = "terminal already attached!\n";
::write(fd, message, sizeof(message));
::close(fd);
return;
@@ -165,7 +161,7 @@ SimConsole::accept()
pollQueue.schedule(dataEvent);
stringstream stream;
- ccprintf(stream, "==== m5 slave console: Console %d ====", number);
+ ccprintf(stream, "==== m5 slave terminal: Terminal %d ====", number);
// we need an actual carriage return followed by a newline for the
// terminal
@@ -173,13 +169,13 @@ SimConsole::accept()
write((const uint8_t *)stream.str().c_str(), stream.str().size());
- DPRINTFN("attach console %d\n", number);
+ DPRINTFN("attach terminal %d\n", number);
txbuf.readall(data_fd);
}
void
-SimConsole::detach()
+Terminal::detach()
{
if (data_fd != -1) {
::close(data_fd);
@@ -190,11 +186,11 @@ SimConsole::detach()
delete dataEvent;
dataEvent = NULL;
- DPRINTFN("detach console %d\n", number);
+ DPRINTFN("detach terminal %d\n", number);
}
void
-SimConsole::data()
+Terminal::data()
{
uint8_t buf[1024];
int len;
@@ -208,10 +204,10 @@ SimConsole::data()
}
size_t
-SimConsole::read(uint8_t *buf, size_t len)
+Terminal::read(uint8_t *buf, size_t len)
{
if (data_fd < 0)
- panic("Console not properly attached.\n");
+ panic("Terminal not properly attached.\n");
size_t ret;
do {
@@ -230,12 +226,12 @@ SimConsole::read(uint8_t *buf, size_t len)
return ret;
}
-// Console output.
+// Terminal output.
size_t
-SimConsole::write(const uint8_t *buf, size_t len)
+Terminal::write(const uint8_t *buf, size_t len)
{
if (data_fd < 0)
- panic("Console not properly attached.\n");
+ panic("Terminal not properly attached.\n");
size_t ret;
for (;;) {
@@ -257,7 +253,7 @@ SimConsole::write(const uint8_t *buf, size_t len)
#define RECEIVE_ERROR (ULL(3) << 62)
uint8_t
-SimConsole::in()
+Terminal::in()
{
bool empty;
uint8_t c;
@@ -268,14 +264,14 @@ SimConsole::in()
empty = rxbuf.empty();
- DPRINTF(ConsoleVerbose, "in: \'%c\' %#02x more: %d\n",
+ DPRINTF(TerminalVerbose, "in: \'%c\' %#02x more: %d\n",
isprint(c) ? c : ' ', c, !empty);
return c;
}
uint64_t
-SimConsole::console_in()
+Terminal::console_in()
{
uint64_t value;
@@ -287,16 +283,16 @@ SimConsole::console_in()
value = RECEIVE_NONE;
}
- DPRINTF(ConsoleVerbose, "console_in: return: %#x\n", value);
+ DPRINTF(TerminalVerbose, "console_in: return: %#x\n", value);
return value;
}
void
-SimConsole::out(char c)
+Terminal::out(char c)
{
#if TRACING_ON == 1
- if (DTRACE(Console)) {
+ if (DTRACE(Terminal)) {
static char last = '\0';
if (c != '\n' && c != '\r' ||
@@ -306,7 +302,7 @@ SimConsole::out(char c)
char *buffer = new char[size + 1];
linebuf.read(buffer, size);
buffer[size] = '\0';
- DPRINTF(Console, "%s\n", buffer);
+ DPRINTF(Terminal, "%s\n", buffer);
delete [] buffer;
} else {
linebuf.write(c);
@@ -325,13 +321,13 @@ SimConsole::out(char c)
if (outfile)
outfile->write(&c, 1);
- DPRINTF(ConsoleVerbose, "out: \'%c\' %#02x\n",
+ DPRINTF(TerminalVerbose, "out: \'%c\' %#02x\n",
isprint(c) ? c : ' ', (int)c);
}
-SimConsole *
-SimConsoleParams::create()
+Terminal *
+TerminalParams::create()
{
- return new SimConsole(this);
+ return new Terminal(this);
}
diff --git a/src/dev/simconsole.hh b/src/dev/terminal.hh
index c8d453960..d2499b6b2 100644
--- a/src/dev/simconsole.hh
+++ b/src/dev/terminal.hh
@@ -30,11 +30,11 @@
*/
/* @file
- * User Console Interface
+ * User Terminal Interface
*/
-#ifndef __CONSOLE_HH__
-#define __CONSOLE_HH__
+#ifndef __DEV_TERMINAL_HH__
+#define __DEV_TERMINAL_HH__
#include <iostream>
@@ -43,12 +43,12 @@
#include "base/pollevent.hh"
#include "base/socket.hh"
#include "sim/sim_object.hh"
-#include "params/SimConsole.hh"
+#include "params/Terminal.hh"
-class ConsoleListener;
+class TerminalListener;
class Uart;
-class SimConsole : public SimObject
+class Terminal : public SimObject
{
public:
Uart *uart;
@@ -57,10 +57,10 @@ class SimConsole : public SimObject
class ListenEvent : public PollEvent
{
protected:
- SimConsole *cons;
+ Terminal *term;
public:
- ListenEvent(SimConsole *c, int fd, int e);
+ ListenEvent(Terminal *t, int fd, int e);
void process(int revent);
};
@@ -70,10 +70,10 @@ class SimConsole : public SimObject
class DataEvent : public PollEvent
{
protected:
- SimConsole *cons;
+ Terminal *term;
public:
- DataEvent(SimConsole *c, int fd, int e);
+ DataEvent(Terminal *t, int fd, int e);
void process(int revent);
};
@@ -85,9 +85,9 @@ class SimConsole : public SimObject
int data_fd;
public:
- typedef SimConsoleParams Params;
- SimConsole(const Params *p);
- ~SimConsole();
+ typedef TerminalParams Params;
+ Terminal(const Params *p);
+ ~Terminal();
protected:
ListenSocket listener;
@@ -119,10 +119,10 @@ class SimConsole : public SimObject
/////////////////
// OS interface
- // Get a character from the console.
+ // Get a character from the terminal.
uint8_t in();
- // get a character from the console in the console specific format
+ // get a character from the terminal in the console specific format
// corresponds to GETC:
// retval<63:61>
// 000: success: character received
@@ -136,11 +136,11 @@ class SimConsole : public SimObject
// Interrupts are cleared when the buffer is empty.
uint64_t console_in();
- // Send a character to the console
+ // Send a character to the terminal
void out(char c);
- //Ask the console if data is available
+ // Ask the terminal if data is available
bool dataAvailable() { return !rxbuf.empty(); }
};
-#endif // __CONSOLE_HH__
+#endif // __DEV_TERMINAL_HH__
diff --git a/src/dev/uart.cc b/src/dev/uart.cc
index c9a2ae964..ab0ebde2c 100644
--- a/src/dev/uart.cc
+++ b/src/dev/uart.cc
@@ -32,17 +32,17 @@
* Implements a base class for UARTs
*/
-#include "dev/simconsole.hh"
-#include "dev/uart.hh"
#include "dev/platform.hh"
+#include "dev/terminal.hh"
+#include "dev/uart.hh"
using namespace std;
Uart::Uart(const Params *p)
- : BasicPioDevice(p), platform(p->platform), cons(p->sim_console)
+ : BasicPioDevice(p), platform(p->platform), term(p->terminal)
{
status = 0;
// set back pointers
- cons->uart = this;
+ term->uart = this;
}
diff --git a/src/dev/uart.hh b/src/dev/uart.hh
index f5d5e2855..ba10c204c 100644
--- a/src/dev/uart.hh
+++ b/src/dev/uart.hh
@@ -39,7 +39,7 @@
#include "dev/io_device.hh"
#include "params/Uart.hh"
-class SimConsole;
+class Terminal;
class Platform;
const int RX_INT = 0x1;
@@ -51,7 +51,7 @@ class Uart : public BasicPioDevice
protected:
int status;
Platform *platform;
- SimConsole *cons;
+ Terminal *term;
public:
typedef UartParams Params;
diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc
index b4dc93645..eefda76e5 100644
--- a/src/dev/uart8250.cc
+++ b/src/dev/uart8250.cc
@@ -38,9 +38,9 @@
#include "base/inifile.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
-#include "dev/simconsole.hh"
-#include "dev/uart8250.hh"
#include "dev/platform.hh"
+#include "dev/terminal.hh"
+#include "dev/uart8250.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
@@ -120,8 +120,8 @@ Uart8250::read(PacketPtr pkt)
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // read byte
- if (cons->dataAvailable())
- pkt->set(cons->in());
+ if (term->dataAvailable())
+ pkt->set(term->in());
else {
pkt->set((uint8_t)0);
// A limited amount of these are ok.
@@ -130,7 +130,7 @@ Uart8250::read(PacketPtr pkt)
status &= ~RX_INT;
platform->clearConsoleInt();
- if (cons->dataAvailable() && (IER & UART_IER_RDI))
+ if (term->dataAvailable() && (IER & UART_IER_RDI))
rxIntrEvent.scheduleIntr();
} else { // dll divisor latch
;
@@ -165,7 +165,7 @@ Uart8250::read(PacketPtr pkt)
uint8_t lsr;
lsr = 0;
// check if there are any bytes to be read
- if (cons->dataAvailable())
+ if (term->dataAvailable())
lsr = UART_LSR_DR;
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
pkt->set(lsr);
@@ -201,7 +201,7 @@ Uart8250::write(PacketPtr pkt)
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // write byte
- cons->out(pkt->get<uint8_t>());
+ term->out(pkt->get<uint8_t>());
platform->clearConsoleInt();
status &= ~TX_INT;
if (UART_IER_THRI & IER)
@@ -237,7 +237,7 @@ Uart8250::write(PacketPtr pkt)
status &= ~TX_INT;
}
- if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
+ if ((UART_IER_RDI & IER) && term->dataAvailable()) {
DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
rxIntrEvent.scheduleIntr();
} else {
diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh
index 2c69667e1..79c31d5cf 100644
--- a/src/dev/uart8250.hh
+++ b/src/dev/uart8250.hh
@@ -65,7 +65,7 @@ const uint8_t UART_LSR_DR = 0x01;
const uint8_t UART_MCR_LOOP = 0x10;
-class SimConsole;
+class Terminal;
class Platform;
class Uart8250 : public Uart
diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
index 4ba9e7a8a..5165308ed 100644
--- a/src/dev/x86/PC.py
+++ b/src/dev/x86/PC.py
@@ -28,12 +28,13 @@
from m5.params import *
from m5.proxy import *
-from Uart import Uart8250
+
from Device import IsaFake
-from SouthBridge import SouthBridge
-from Platform import Platform
from Pci import PciConfigAll
-from SimConsole import SimConsole
+from Platform import Platform
+from SouthBridge import SouthBridge
+from Terminal import Terminal
+from Uart import Uart8250
def x86IOAddress(port):
IO_address_space_base = 0x8000000000000000
@@ -54,11 +55,11 @@ class PC(Platform):
# but the linux kernel fiddles with them anway.
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
- # Serial port and console
- console = SimConsole()
+ # Serial port and terminal
+ terminal = Terminal()
com_1 = Uart8250()
com_1.pio_addr = x86IOAddress(0x3f8)
- com_1.sim_console = console
+ com_1.terminal = terminal
def attachIO(self, bus):
self.south_bridge.pio = bus.port
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index 0881672d2..d04529ab9 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -39,7 +39,7 @@
#include "arch/x86/x86_traits.hh"
#include "dev/intel_8254_timer.hh"
#include "cpu/intr_control.hh"
-#include "dev/simconsole.hh"
+#include "dev/terminal.hh"
#include "dev/x86/pc.hh"
#include "sim/system.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-25 04:55:01 +0000