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-rw-r--r--src/dev/alpha_console.cc2
-rw-r--r--src/dev/io_device.cc57
-rw-r--r--src/dev/io_device.hh18
-rw-r--r--src/dev/ns_gige.cc2
-rw-r--r--src/dev/sinic.cc2
-rw-r--r--src/dev/tsunami_cchip.cc14
6 files changed, 58 insertions, 37 deletions
diff --git a/src/dev/alpha_console.cc b/src/dev/alpha_console.cc
index aa3261f01..181bbf934 100644
--- a/src/dev/alpha_console.cc
+++ b/src/dev/alpha_console.cc
@@ -43,7 +43,7 @@
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "dev/alpha_console.hh"
#include "dev/platform.hh"
#include "dev/simconsole.hh"
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index f0509429f..485216874 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -120,19 +120,32 @@ DmaPort::DmaPort(DmaDevice *dev, Platform *p)
bool
DmaPort::recvTiming(Packet *pkt)
{
- if (pkt->senderState) {
+
+
+ if (pkt->result == Packet::Nacked) {
+ DPRINTF(DMA, "Received nacked Pkt %#x with State: %#x Addr: %#x\n",
+ pkt, pkt->senderState, pkt->getAddr());
+ pkt->reinitNacked();
+ sendDma(pkt, true);
+ } else if (pkt->senderState) {
DmaReqState *state;
- DPRINTF(DMA, "Received response Packet %#x with senderState: %#x\n",
- pkt, pkt->senderState);
+ DPRINTF(DMA, "Received response Pkt %#x with State: %#x Addr: %#x\n",
+ pkt, pkt->senderState, pkt->getAddr());
state = dynamic_cast<DmaReqState*>(pkt->senderState);
+ pendingCount--;
+
+ assert(pendingCount >= 0);
assert(state);
- state->completionEvent->process();
+
+ state->numBytes += pkt->req->getSize();
+ if (state->totBytes == state->numBytes) {
+ state->completionEvent->process();
+ delete state;
+ }
delete pkt->req;
delete pkt;
} else {
- DPRINTF(DMA, "Received response Packet %#x with no senderState\n", pkt);
- delete pkt->req;
- delete pkt;
+ panic("Got packet without sender state... huh?\n");
}
return true;
@@ -154,8 +167,6 @@ DmaPort::recvRetry()
if (result) {
DPRINTF(DMA, "-- Done\n");
transmitList.pop_front();
- pendingCount--;
- assert(pendingCount >= 0);
} else {
DPRINTF(DMA, "-- Failed, queued\n");
}
@@ -169,7 +180,7 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
{
assert(event);
- int prevSize = 0;
+ DmaReqState *reqState = new DmaReqState(event, this, size);
for (ChunkGenerator gen(addr, size, peerBlockSize());
!gen.done(); gen.next()) {
@@ -178,15 +189,10 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
// Increment the data pointer on a write
if (data)
- pkt->dataStatic(data + prevSize);
+ pkt->dataStatic(data + gen.complete());
- prevSize += gen.size();
+ pkt->senderState = reqState;
- // Set the last bit of the dma as the final packet for this dma
- // and set it's completion event.
- if (prevSize == size) {
- pkt->senderState = new DmaReqState(event, true);
- }
assert(pendingCount >= 0);
pendingCount++;
sendDma(pkt);
@@ -195,7 +201,7 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
void
-DmaPort::sendDma(Packet *pkt)
+DmaPort::sendDma(Packet *pkt, bool front)
{
// some kind of selction between access methods
// more work is going to have to be done to make
@@ -203,22 +209,25 @@ DmaPort::sendDma(Packet *pkt)
/* MemState state = device->platform->system->memState;
if (state == Timing) { */
- DPRINTF(DMA, "Attempting to send Packet %#x with senderState: %#x\n",
- pkt, pkt->senderState);
+ DPRINTF(DMA, "Attempting to send Packet %#x with addr: %#x\n",
+ pkt, pkt->getAddr());
if (transmitList.size() || !sendTiming(pkt)) {
- transmitList.push_back(pkt);
+ if (front)
+ transmitList.push_front(pkt);
+ else
+ transmitList.push_back(pkt);
DPRINTF(DMA, "-- Failed: queued\n");
} else {
DPRINTF(DMA, "-- Done\n");
- pendingCount--;
- assert(pendingCount >= 0);
}
/* } else if (state == Atomic) {
sendAtomic(pkt);
if (pkt->senderState) {
DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
assert(state);
- state->completionEvent->schedule(curTick + (pkt->time - pkt->req->getTime()) +1);
+ state->completionEvent->schedule(curTick + (pkt->time -
+ pkt->req->getTime()) +1);
+ delete state;
}
pendingCount--;
assert(pendingCount >= 0);
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 3cb18c9fa..195ca0fb7 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -121,10 +121,22 @@ class PioPort : public Port
struct DmaReqState : public Packet::SenderState
{
+ /** Event to call on the device when this transaction (all packets)
+ * complete. */
Event *completionEvent;
+
+ /** Where we came from for some sanity checking. */
+ Port *outPort;
+
+ /** Total number of bytes that this transaction involves. */
+ Addr totBytes;
+
+ /** Number of bytes that have been acked for this transaction. */
+ Addr numBytes;
+
bool final;
- DmaReqState(Event *ce, bool f)
- : completionEvent(ce), final(f)
+ DmaReqState(Event *ce, Port *p, Addr tb)
+ : completionEvent(ce), outPort(p), totBytes(tb), numBytes(0)
{}
};
@@ -155,7 +167,7 @@ class DmaPort : public Port
virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
- void sendDma(Packet *pkt);
+ void sendDma(Packet *pkt, bool front = false);
public:
DmaPort(DmaDevice *dev, Platform *p);
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 1f2fea418..decffaf73 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -37,7 +37,7 @@
#include "arch/alpha/ev5.hh"
#include "base/inet.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
#include "dev/ns_gige.hh"
#include "dev/pciconfigall.hh"
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index d186c0036..a0223733b 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -33,7 +33,7 @@
#include <string>
#include "base/inet.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
diff --git a/src/dev/tsunami_cchip.cc b/src/dev/tsunami_cchip.cc
index e4be98642..3feb7439f 100644
--- a/src/dev/tsunami_cchip.cc
+++ b/src/dev/tsunami_cchip.cc
@@ -43,7 +43,7 @@
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/port.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@@ -368,7 +368,7 @@ TsunamiCChip::write(Packet *pkt)
void
TsunamiCChip::clearIPI(uint64_t ipintr)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (ipintr) {
@@ -394,7 +394,7 @@ TsunamiCChip::clearIPI(uint64_t ipintr)
void
TsunamiCChip::clearITI(uint64_t itintr)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (itintr) {
@@ -414,7 +414,7 @@ TsunamiCChip::clearITI(uint64_t itintr)
void
TsunamiCChip::reqIPI(uint64_t ipreq)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (ipreq) {
@@ -441,7 +441,7 @@ TsunamiCChip::reqIPI(uint64_t ipreq)
void
TsunamiCChip::postRTC()
{
- int size = tsunami->intrctrl->cpu->system->execContexts.size();
+ int size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
for (int i = 0; i < size; i++) {
@@ -459,7 +459,7 @@ void
TsunamiCChip::postDRIR(uint32_t interrupt)
{
uint64_t bitvector = ULL(1) << interrupt;
- uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+ uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
drir |= bitvector;
@@ -477,7 +477,7 @@ void
TsunamiCChip::clearDRIR(uint32_t interrupt)
{
uint64_t bitvector = ULL(1) << interrupt;
- uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+ uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
if (drir & bitvector)
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 10:50:47 +0000