3 files changed, 44 insertions, 3 deletions

diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index e0272c655..baf13c49a 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -656,7 +656,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet)
         return false;
 
     pktPtr = packet;
-
+    pktDone = false;
     igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
             packet->length, &pktEvent, packet->data);
     return true;
@@ -683,8 +683,12 @@ IGbE::RxDescCache::pktComplete()
 
     uint8_t status = RXDS_DD | RXDS_EOP;
     uint8_t err = 0;
+
     IpPtr ip(pktPtr);
+
     if (ip) {
+        DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id());
+
         if (igbe->regs.rxcsum.ipofld()) {
             DPRINTF(EthernetDesc, "Checking IP checksum\n");
             status |= RXDS_IPCS;
@@ -715,7 +719,10 @@ IGbE::RxDescCache::pktComplete()
                 err |= RXDE_TCPE;
             }
         }
-    } // if ip
+    } else { // if ip
+        DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
+    }
+
 
     desc->status = htole(status);
     desc->errors = htole(err);
@@ -912,10 +919,20 @@ IGbE::TxDescCache::pktComplete()
 
     DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
 
+    if (DTRACE(EthernetDesc)) {
+        IpPtr ip(pktPtr);
+        if (ip)
+            DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n",
+                    ip->id());
+        else
+            DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
+    }
+
     // Checksums are only ofloaded for new descriptor types
     if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
         DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
         IpPtr ip(pktPtr);
+
         if (TxdOp::ixsm(desc)) {
             ip->sum(0);
             ip->sum(cksum(ip));
@@ -1192,6 +1209,7 @@ IGbE::rxStateMachine()
 
     // If the packet is done check for interrupts/descriptors/etc
     if (rxDescCache.packetDone()) {
+        rxDmaPacket = false;
         DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n");
         int descLeft = rxDescCache.descLeft();
         switch (regs.rctl.rdmts()) {
@@ -1236,6 +1254,12 @@ IGbE::rxStateMachine()
         return;
     }
 
+    if (rxDmaPacket) {
+        DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
+        rxTick = false;
+        return;
+    }
+
     if (!rxDescCache.descUnused()) {
         DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n");
         rxTick = false;
@@ -1262,6 +1286,7 @@ IGbE::rxStateMachine()
     rxFifo.pop();
     DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
     rxTick = false;
+    rxDmaPacket = true;
 }
 
 void
diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index 2dec3b08c..b6da53b09 100644
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -80,6 +80,8 @@ class IGbE : public PciDev
     bool txTick;
     bool txFifoTick;
 
+    bool rxDmaPacket;
+
     // Event and function to deal with RDTR timer expiring
     void rdtrProcess() {
         rxDescCache.writeback(0);
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index d430ace72..6528bd81c 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -218,6 +218,9 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
 
     DmaReqState *reqState = new DmaReqState(event, this, size);
 
+
+    DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
+            event->scheduled());
     for (ChunkGenerator gen(addr, size, peerBlockSize());
          !gen.done(); gen.next()) {
             Request *req = new Request(gen.addr(), gen.size(), 0);
@@ -231,6 +234,8 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
 
             assert(pendingCount >= 0);
             pendingCount++;
+            DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(),
+                    gen.size());
             queueDma(pkt);
     }
 
@@ -281,19 +286,28 @@ DmaPort::sendDma()
 
         if (transmitList.size() && backoffTime && !inRetry &&
                 !backoffEvent.scheduled()) {
+            DPRINTF(DMA, "-- Scheduling backoff timer for %d\n",
+                    backoffTime+curTick);
             backoffEvent.schedule(backoffTime+curTick);
         }
     } else if (state == System::Atomic) {
         transmitList.pop_front();
 
         Tick lat;
+        DPRINTF(DMA, "--Sending  DMA for addr: %#x size: %d\n",
+                pkt->req->getPaddr(), pkt->req->getSize());
         lat = sendAtomic(pkt);
         assert(pkt->senderState);
         DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
         assert(state);
-
         state->numBytes += pkt->req->getSize();
+
+        DPRINTF(DMA, "--Received response for  DMA for addr: %#x size: %d nb: %d, tot: %d sched %d\n",
+                pkt->req->getPaddr(), pkt->req->getSize(), state->numBytes,
+                state->totBytes, state->completionEvent->scheduled());
+
         if (state->totBytes == state->numBytes) {
+            assert(!state->completionEvent->scheduled());
             state->completionEvent->schedule(curTick + lat);
             delete state;
             delete pkt->req;